SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_por_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_io_div2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_daon_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
u_d0_lc_io_div4_shadowed |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_lc_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_d0_sys |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | u_daon_sys_io_div4 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_device |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_spi_host1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_usb |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
100.00 | 100.00 | 100.00 | 100.00 | u_d0_usb_aon |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c0 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c1 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.67 | 100.00 | 90.00 | 100.00 | u_d0_i2c2 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
99.55 | 100.00 | 98.21 | 100.00 | 100.00 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 16665 | 16665 | 0 | 0 |
OutputsKnown_A | 398474296 | 230462715 | 0 | 0 |
gen_no_flops.OutputDelay_A | 398474296 | 230462715 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 16665 | 16665 | 0 | 0 |
T1 | 33 | 33 | 0 | 0 |
T2 | 33 | 33 | 0 | 0 |
T3 | 33 | 33 | 0 | 0 |
T4 | 33 | 33 | 0 | 0 |
T5 | 33 | 33 | 0 | 0 |
T6 | 33 | 33 | 0 | 0 |
T7 | 33 | 33 | 0 | 0 |
T8 | 33 | 33 | 0 | 0 |
T9 | 33 | 33 | 0 | 0 |
T10 | 33 | 33 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 398474296 | 230462715 | 0 | 0 |
T1 | 936496 | 670362 | 0 | 0 |
T2 | 129565 | 103313 | 0 | 0 |
T3 | 9291243 | 7258791 | 0 | 0 |
T4 | 134603 | 100738 | 0 | 0 |
T5 | 152620 | 123522 | 0 | 0 |
T6 | 985443 | 763521 | 0 | 0 |
T7 | 68319 | 43668 | 0 | 0 |
T8 | 530862 | 273179 | 0 | 0 |
T9 | 84226 | 51532 | 0 | 0 |
T10 | 61578 | 41500 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 398474296 | 230462715 | 0 | 0 |
T1 | 936496 | 670362 | 0 | 0 |
T2 | 129565 | 103313 | 0 | 0 |
T3 | 9291243 | 7258791 | 0 | 0 |
T4 | 134603 | 100738 | 0 | 0 |
T5 | 152620 | 123522 | 0 | 0 |
T6 | 985443 | 763521 | 0 | 0 |
T7 | 68319 | 43668 | 0 | 0 |
T8 | 530862 | 273179 | 0 | 0 |
T9 | 84226 | 51532 | 0 | 0 |
T10 | 61578 | 41500 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 13560952 | 8079195 | 0 | 0 |
gen_no_flops.OutputDelay_A | 13560952 | 8079195 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13560952 | 8079195 | 0 | 0 |
T1 | 33104 | 24026 | 0 | 0 |
T2 | 4541 | 3889 | 0 | 0 |
T3 | 312267 | 242535 | 0 | 0 |
T4 | 4267 | 3298 | 0 | 0 |
T5 | 5772 | 5122 | 0 | 0 |
T6 | 33795 | 26177 | 0 | 0 |
T7 | 2847 | 2196 | 0 | 0 |
T8 | 21454 | 12763 | 0 | 0 |
T9 | 2690 | 1708 | 0 | 0 |
T10 | 1930 | 1276 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 13560952 | 8079195 | 0 | 0 |
T1 | 33104 | 24026 | 0 | 0 |
T2 | 4541 | 3889 | 0 | 0 |
T3 | 312267 | 242535 | 0 | 0 |
T4 | 4267 | 3298 | 0 | 0 |
T5 | 5772 | 5122 | 0 | 0 |
T6 | 33795 | 26177 | 0 | 0 |
T7 | 2847 | 2196 | 0 | 0 |
T8 | 21454 | 12763 | 0 | 0 |
T9 | 2690 | 1708 | 0 | 0 |
T10 | 1930 | 1276 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 145 | 0 | 0 | |
CONT_ASSIGN | 155 | 1 | 1 | 100.00 |
CONT_ASSIGN | 168 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
145 | unreachable | ||
146 | unreachable | ||
148 | unreachable | ||
155 | 1 | 1 | |
168 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 505 | 505 | 0 | 0 |
OutputsKnown_A | 12028542 | 6949485 | 0 | 0 |
gen_no_flops.OutputDelay_A | 12028542 | 6949485 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 505 | 505 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T5 | 1 | 1 | 0 | 0 |
T6 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T8 | 1 | 1 | 0 | 0 |
T9 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 12028542 | 6949485 | 0 | 0 |
T1 | 28231 | 20198 | 0 | 0 |
T2 | 3907 | 3107 | 0 | 0 |
T3 | 280593 | 219258 | 0 | 0 |
T4 | 4073 | 3045 | 0 | 0 |
T5 | 4589 | 3700 | 0 | 0 |
T6 | 29739 | 23042 | 0 | 0 |
T7 | 2046 | 1296 | 0 | 0 |
T8 | 15919 | 8138 | 0 | 0 |
T9 | 2548 | 1557 | 0 | 0 |
T10 | 1864 | 1257 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |