Line Coverage for Module :
prim_generic_clock_mux2
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Module :
prim_generic_clock_mux2
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Module :
prim_generic_clock_mux2
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
1330498 |
1298178 |
0 |
0 |
selKnown1 |
183040 |
150720 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1330498 |
1298178 |
0 |
0 |
T1 |
3067 |
3003 |
0 |
0 |
T2 |
669 |
605 |
0 |
0 |
T3 |
22048 |
21984 |
0 |
0 |
T4 |
347 |
283 |
0 |
0 |
T5 |
999 |
935 |
0 |
0 |
T6 |
2773 |
2709 |
0 |
0 |
T7 |
669 |
605 |
0 |
0 |
T8 |
3444 |
3380 |
0 |
0 |
T9 |
350 |
286 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
137 |
0 |
0 |
T12 |
0 |
470 |
0 |
0 |
T13 |
0 |
13 |
0 |
0 |
T23 |
0 |
21 |
0 |
0 |
T57 |
0 |
53 |
0 |
0 |
T61 |
0 |
8 |
0 |
0 |
T87 |
0 |
8 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
183040 |
150720 |
0 |
0 |
T1 |
704 |
640 |
0 |
0 |
T2 |
64 |
0 |
0 |
0 |
T3 |
4160 |
4096 |
0 |
0 |
T4 |
128 |
64 |
0 |
0 |
T5 |
64 |
0 |
0 |
0 |
T6 |
768 |
704 |
0 |
0 |
T7 |
64 |
0 |
0 |
0 |
T8 |
640 |
576 |
0 |
0 |
T9 |
128 |
64 |
0 |
0 |
T10 |
64 |
0 |
0 |
0 |
T11 |
0 |
448 |
0 |
0 |
T61 |
0 |
64 |
0 |
0 |
T87 |
0 |
64 |
0 |
0 |
T88 |
0 |
832 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22442 |
21937 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22442 |
21937 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22511 |
22006 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22511 |
22006 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23464 |
22959 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23464 |
22959 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
397 |
396 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23530 |
23025 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23530 |
23025 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
390 |
389 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23548 |
23043 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23548 |
23043 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
395 |
394 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23604 |
23099 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23604 |
23099 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
391 |
390 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23657 |
23152 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23657 |
23152 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
393 |
392 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
7 |
6 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22442 |
21937 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22442 |
21937 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
6 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23698 |
23193 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23698 |
23193 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
392 |
391 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23777 |
23272 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23777 |
23272 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
396 |
395 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
23815 |
23310 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
23815 |
23310 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
395 |
394 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
22561 |
22056 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
22561 |
22056 |
0 |
0 |
T1 |
53 |
52 |
0 |
0 |
T2 |
12 |
11 |
0 |
0 |
T3 |
378 |
377 |
0 |
0 |
T4 |
6 |
5 |
0 |
0 |
T5 |
18 |
17 |
0 |
0 |
T6 |
48 |
47 |
0 |
0 |
T7 |
12 |
11 |
0 |
0 |
T8 |
60 |
59 |
0 |
0 |
T9 |
6 |
5 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T12 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
7452 |
6947 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
7452 |
6947 |
0 |
0 |
T1 |
8 |
7 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
69 |
68 |
0 |
0 |
T4 |
1 |
0 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
5 |
4 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
8 |
7 |
0 |
0 |
T9 |
1 |
0 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
9 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T13 |
0 |
13 |
0 |
0 |
T23 |
0 |
21 |
0 |
0 |
T57 |
0 |
53 |
0 |
0 |
T88 |
0 |
8 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9767 |
9262 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9767 |
9262 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |
Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Line No. | Total | Covered | Percent |
TOTAL | | 1 | 1 | 100.00 |
CONT_ASSIGN | 17 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
17 |
1 |
1 |
Cond Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
| Total | Covered | Percent |
Conditions | 9 | 9 | 100.00 |
Logical | 9 | 9 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 17
EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
--------1------- ----------2----------
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (sel_i & clk1_i)
--1-- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Covered | T1,T3,T4 |
1 | 1 | Covered | T1,T3,T4 |
LINE 17
SUB-EXPRESSION (((~sel_i)) & clk0_i)
-----1---- ---2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T4 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
selKnown0 |
9301 |
8796 |
0 |
0 |
selKnown1 |
2860 |
2355 |
0 |
0 |
selKnown0
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
9301 |
8796 |
0 |
0 |
T1 |
18 |
17 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
133 |
132 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
16 |
15 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
17 |
16 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
16 |
0 |
0 |
T12 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
selKnown1
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
2860 |
2355 |
0 |
0 |
T1 |
11 |
10 |
0 |
0 |
T2 |
1 |
0 |
0 |
0 |
T3 |
65 |
64 |
0 |
0 |
T4 |
2 |
1 |
0 |
0 |
T5 |
1 |
0 |
0 |
0 |
T6 |
12 |
11 |
0 |
0 |
T7 |
1 |
0 |
0 |
0 |
T8 |
10 |
9 |
0 |
0 |
T9 |
2 |
1 |
0 |
0 |
T10 |
1 |
0 |
0 |
0 |
T11 |
0 |
7 |
0 |
0 |
T61 |
0 |
1 |
0 |
0 |
T87 |
0 |
1 |
0 |
0 |
T88 |
0 |
13 |
0 |
0 |