Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T7,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T61
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T62,T55
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T61,T62
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T62,T55
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13560952	14163	0	0
gen_assertions[0].RstEnOn_A	13560952	1110	0	0
gen_assertions[0].RstNOff_A	13560952	14163	0	0
gen_assertions[0].RstNOn_A	13560952	1110	0	0
gen_assertions[1].RstEnOff_A	54243684	12924	0	0
gen_assertions[1].RstEnOn_A	54243684	1115	0	0
gen_assertions[1].RstNOff_A	54243684	12924	0	0
gen_assertions[1].RstNOn_A	54243684	1115	0	0
gen_assertions[2].RstEnOff_A	27122668	12942	0	0
gen_assertions[2].RstEnOn_A	27122668	1083	0	0
gen_assertions[2].RstNOff_A	27122668	12942	0	0
gen_assertions[2].RstNOn_A	27122668	1083	0	0
gen_assertions[3].RstEnOff_A	27122513	12998	0	0
gen_assertions[3].RstEnOn_A	27122513	1140	0	0
gen_assertions[3].RstNOff_A	27122513	12998	0	0
gen_assertions[3].RstNOn_A	27122513	1140	0	0
gen_assertions[4].RstEnOff_A	1711728	22406	0	0
gen_assertions[4].RstEnOn_A	1711728	1205	0	0
gen_assertions[4].RstNOff_A	1711728	22406	0	0
gen_assertions[4].RstNOn_A	1711728	1205	0	0
gen_assertions[5].RstEnOff_A	13560952	14397	0	0
gen_assertions[5].RstEnOn_A	13560952	1232	0	0
gen_assertions[5].RstNOff_A	13560952	14397	0	0
gen_assertions[5].RstNOn_A	13560952	1232	0	0
gen_assertions[6].RstEnOff_A	13560952	14476	0	0
gen_assertions[6].RstEnOn_A	13560952	1306	0	0
gen_assertions[6].RstNOff_A	13560952	14476	0	0
gen_assertions[6].RstNOn_A	13560952	1306	0	0
gen_assertions[7].RstEnOff_A	13560952	14514	0	0
gen_assertions[7].RstEnOn_A	13560952	1344	0	0
gen_assertions[7].RstNOff_A	13560952	14514	0	0
gen_assertions[7].RstNOn_A	13560952	1344	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14163	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	264	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1110	0	0
T2	4541	3	0	0
T3	312267	20	0	0
T4	4267	0	0	0
T5	5772	1	0	0
T6	33795	0	0	0
T7	2847	6	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T23	0	3	0	0
T56	0	1	0	0
T57	0	26	0	0
T62	0	4	0	0
T75	1585	0	0	0
T90	0	1	0	0
T91	0	8	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14163	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	264	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1110	0	0
T2	4541	3	0	0
T3	312267	20	0	0
T4	4267	0	0	0
T5	5772	1	0	0
T6	33795	0	0	0
T7	2847	6	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T23	0	3	0	0
T56	0	1	0	0
T57	0	26	0	0
T62	0	4	0	0
T75	1585	0	0	0
T90	0	1	0	0
T91	0	8	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54243684	12924	0	0
T1	132425	31	0	0
T2	18169	8	0	0
T3	124905	244	0	0
T4	17071	4	0	0
T5	23096	14	0	0
T6	135171	30	0	0
T7	11391	8	0	0
T8	85833	41	0	0
T9	10765	4	0	0
T10	7725	0	0	0
T11	0	32	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54243684	1115	0	0
T3	124905	14	0	0
T4	17071	0	0	0
T5	23096	0	0	0
T6	135171	0	0	0
T7	11391	3	0	0
T8	85833	0	0	0
T9	10765	0	0	0
T10	7725	0	0	0
T12	23376	0	0	0
T23	0	5	0	0
T24	0	13	0	0
T27	0	10	0	0
T30	0	5	0	0
T55	0	1	0	0
T57	0	30	0	0
T62	0	5	0	0
T75	6346	0	0	0
T91	0	9	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54243684	12924	0	0
T1	132425	31	0	0
T2	18169	8	0	0
T3	124905	244	0	0
T4	17071	4	0	0
T5	23096	14	0	0
T6	135171	30	0	0
T7	11391	8	0	0
T8	85833	41	0	0
T9	10765	4	0	0
T10	7725	0	0	0
T11	0	32	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54243684	1115	0	0
T3	124905	14	0	0
T4	17071	0	0	0
T5	23096	0	0	0
T6	135171	0	0	0
T7	11391	3	0	0
T8	85833	0	0	0
T9	10765	0	0	0
T10	7725	0	0	0
T12	23376	0	0	0
T23	0	5	0	0
T24	0	13	0	0
T27	0	10	0	0
T30	0	5	0	0
T55	0	1	0	0
T57	0	30	0	0
T62	0	5	0	0
T75	6346	0	0	0
T91	0	9	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122668	12942	0	0
T1	66217	31	0	0
T2	9084	8	0	0
T3	624537	249	0	0
T4	8534	4	0	0
T5	11548	14	0	0
T6	67596	30	0	0
T7	5695	8	0	0
T8	42910	41	0	0
T9	5383	5	0	0
T10	3862	0	0	0
T11	0	32	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122668	1083	0	0
T3	624537	18	0	0
T4	8534	0	0	0
T5	11548	0	0	0
T6	67596	0	0	0
T7	5695	0	0	0
T8	42910	0	0	0
T9	5383	1	0	0
T10	3862	0	0	0
T12	11684	0	0	0
T23	0	5	0	0
T24	0	14	0	0
T27	0	4	0	0
T30	0	1	0	0
T53	0	8	0	0
T54	0	8	0	0
T57	0	28	0	0
T62	0	6	0	0
T75	3172	0	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122668	12942	0	0
T1	66217	31	0	0
T2	9084	8	0	0
T3	624537	249	0	0
T4	8534	4	0	0
T5	11548	14	0	0
T6	67596	30	0	0
T7	5695	8	0	0
T8	42910	41	0	0
T9	5383	5	0	0
T10	3862	0	0	0
T11	0	32	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122668	1083	0	0
T3	624537	18	0	0
T4	8534	0	0	0
T5	11548	0	0	0
T6	67596	0	0	0
T7	5695	0	0	0
T8	42910	0	0	0
T9	5383	1	0	0
T10	3862	0	0	0
T12	11684	0	0	0
T23	0	5	0	0
T24	0	14	0	0
T27	0	4	0	0
T30	0	1	0	0
T53	0	8	0	0
T54	0	8	0	0
T57	0	28	0	0
T62	0	6	0	0
T75	3172	0	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122513	12998	0	0
T1	66212	31	0	0
T2	9084	8	0	0
T3	624544	245	0	0
T4	8534	4	0	0
T5	11547	14	0	0
T6	67597	30	0	0
T7	5695	8	0	0
T8	42911	41	0	0
T9	5386	5	0	0
T10	3863	0	0	0
T11	0	32	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122513	1140	0	0
T3	624544	13	0	0
T4	8534	0	0	0
T5	11547	0	0	0
T6	67597	0	0	0
T7	5695	0	0	0
T8	42911	0	0	0
T9	5386	1	0	0
T10	3863	0	0	0
T12	11684	0	0	0
T23	0	4	0	0
T24	0	15	0	0
T27	0	7	0	0
T53	0	8	0	0
T55	0	1	0	0
T57	0	27	0	0
T61	0	1	0	0
T62	0	8	0	0
T75	3172	0	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122513	12998	0	0
T1	66212	31	0	0
T2	9084	8	0	0
T3	624544	245	0	0
T4	8534	4	0	0
T5	11547	14	0	0
T6	67597	30	0	0
T7	5695	8	0	0
T8	42911	41	0	0
T9	5386	5	0	0
T10	3863	0	0	0
T11	0	32	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27122513	1140	0	0
T3	624544	13	0	0
T4	8534	0	0	0
T5	11547	0	0	0
T6	67597	0	0	0
T7	5695	0	0	0
T8	42911	0	0	0
T9	5386	1	0	0
T10	3863	0	0	0
T12	11684	0	0	0
T23	0	4	0	0
T24	0	15	0	0
T27	0	7	0	0
T53	0	8	0	0
T55	0	1	0	0
T57	0	27	0	0
T61	0	1	0	0
T62	0	8	0	0
T75	3172	0	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1711728	22406	0	0
T1	4220	52	0	0
T2	566	10	0	0
T3	39456	391	0	0
T4	531	6	0	0
T5	720	18	0	0
T6	4271	48	0	0
T7	354	10	0	0
T8	2757	60	0	0
T9	335	7	0	0
T10	239	1	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1711728	1205	0	0
T3	39456	16	0	0
T4	531	0	0	0
T5	720	0	0	0
T6	4271	0	0	0
T7	354	0	0	0
T8	2757	0	0	0
T9	335	1	0	0
T10	239	0	0	0
T12	732	0	0	0
T23	0	2	0	0
T24	0	14	0	0
T27	0	10	0	0
T53	0	9	0	0
T54	0	11	0	0
T57	0	31	0	0
T61	0	1	0	0
T62	0	7	0	0
T75	196	0	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1711728	22406	0	0
T1	4220	52	0	0
T2	566	10	0	0
T3	39456	391	0	0
T4	531	6	0	0
T5	720	18	0	0
T6	4271	48	0	0
T7	354	10	0	0
T8	2757	60	0	0
T9	335	7	0	0
T10	239	1	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1711728	1205	0	0
T3	39456	16	0	0
T4	531	0	0	0
T5	720	0	0	0
T6	4271	0	0	0
T7	354	0	0	0
T8	2757	0	0	0
T9	335	1	0	0
T10	239	0	0	0
T12	732	0	0	0
T23	0	2	0	0
T24	0	14	0	0
T27	0	10	0	0
T53	0	9	0	0
T54	0	11	0	0
T57	0	31	0	0
T61	0	1	0	0
T62	0	7	0	0
T75	196	0	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14397	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	259	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1232	0	0
T3	312267	16	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	5	0	0
T24	0	13	0	0
T27	0	10	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	1	0	0
T57	0	26	0	0
T62	0	10	0	0
T75	1585	0	0	0
T92	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14397	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	259	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1232	0	0
T3	312267	16	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	5	0	0
T24	0	13	0	0
T27	0	10	0	0
T53	0	6	0	0
T54	0	11	0	0
T55	0	1	0	0
T57	0	26	0	0
T62	0	10	0	0
T75	1585	0	0	0
T92	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14476	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	263	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1306	0	0
T3	312267	19	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	5	0	0
T24	0	16	0	0
T27	0	6	0	0
T53	0	7	0	0
T54	0	13	0	0
T57	0	28	0	0
T61	0	1	0	0
T62	0	7	0	0
T75	1585	0	0	0
T93	0	4	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14476	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	263	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1306	0	0
T3	312267	19	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	5	0	0
T24	0	16	0	0
T27	0	6	0	0
T53	0	7	0	0
T54	0	13	0	0
T57	0	28	0	0
T61	0	1	0	0
T62	0	7	0	0
T75	1585	0	0	0
T93	0	4	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14514	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	262	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1344	0	0
T3	312267	17	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	4	0	0
T24	0	14	0	0
T27	0	7	0	0
T53	0	9	0	0
T54	0	14	0	0
T55	0	1	0	0
T57	0	30	0	0
T62	0	12	0	0
T75	1585	0	0	0
T92	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	14514	0	0
T1	33104	35	0	0
T2	4541	11	0	0
T3	312267	262	0	0
T4	4267	4	0	0
T5	5772	17	0	0
T6	33795	32	0	0
T7	2847	11	0	0
T8	21454	43	0	0
T9	2690	4	0	0
T10	1930	0	0	0
T11	0	32	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13560952	1344	0	0
T3	312267	17	0	0
T4	4267	0	0	0
T5	5772	0	0	0
T6	33795	0	0	0
T7	2847	0	0	0
T8	21454	0	0	0
T9	2690	0	0	0
T10	1930	0	0	0
T12	5841	0	0	0
T23	0	4	0	0
T24	0	14	0	0
T27	0	7	0	0
T53	0	9	0	0
T54	0	14	0	0
T55	0	1	0	0
T57	0	30	0	0
T62	0	12	0	0
T75	1585	0	0	0
T92	0	1	0	0