Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_mubi4_sender
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender 100.00 100.00 100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_por_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_io_div2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_daon_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_d0_lc_io_div4_shadowed


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_lc_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_d0_sys


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 u_daon_sys_io_div4


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_device


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_spi_host1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_usb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_d0_usb_aon


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c0


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
96.67 100.00 90.00 100.00 u_d0_i2c2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00



Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_flops.u_prim_flop 100.00 100.00 100.00

Line Coverage for Module : prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Module : prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 915444328 488848696 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 915444328 488848696 0 0
T1 2234982 1428928 0 0
T2 306578 223114 0 0
T3 9557086 14259245 0 0
T4 288018 210607 0 0
T5 389718 272767 0 0
T6 2281506 1610184 0 0
T7 192200 102508 0 0
T8 1448590 627303 0 0
T9 181702 108640 0 0
T10 130338 85545 0 0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 33686668 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 33686668 0 0
T1 137941 100152 0 0
T2 18926 16207 0 0
T3 130108 101083 0 0
T4 17778 13736 0 0
T5 24059 21346 0 0
T6 140836 109090 0 0
T7 11865 9155 0 0
T8 89401 53251 0 0
T9 11221 7129 0 0
T10 8047 5321 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 54243684 32337252 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54243684 32337252 0 0
T1 132425 96133 0 0
T2 18169 15559 0 0
T3 124905 970405 0 0
T4 17071 13191 0 0
T5 23096 20492 0 0
T6 135171 104710 0 0
T7 11391 8788 0 0
T8 85833 51116 0 0
T9 10765 6838 0 0
T10 7725 5108 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122668 16164788 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122668 16164788 0 0
T1 66217 48066 0 0
T2 9084 7780 0 0
T3 624537 485135 0 0
T4 8534 6592 0 0
T5 11548 10246 0 0
T6 67596 52351 0 0
T7 5695 4394 0 0
T8 42910 25549 0 0
T9 5383 3419 0 0
T10 3862 2554 0 0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 8079195 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 8079195 0 0
T1 33104 24026 0 0
T2 4541 3889 0 0
T3 312267 242535 0 0
T4 4267 3298 0 0
T5 5772 5122 0 0
T6 33795 26177 0 0
T7 2847 2196 0 0
T8 21454 12763 0 0
T9 2690 1708 0 0
T10 1930 1276 0 0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122513 16164746 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122513 16164746 0 0
T1 66212 48063 0 0
T2 9084 7780 0 0
T3 624544 485151 0 0
T4 8534 6593 0 0
T5 11547 10246 0 0
T6 67597 52352 0 0
T7 5695 4394 0 0
T8 42911 25548 0 0
T9 5386 3421 0 0
T10 3863 2554 0 0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 29989281 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 29989281 0 0
T1 137941 86342 0 0
T2 18926 13318 0 0
T3 130108 929395 0 0
T4 17778 12938 0 0
T5 24059 15922 0 0
T6 140836 97982 0 0
T7 11865 5774 0 0
T8 89401 36242 0 0
T9 11221 6740 0 0
T10 8047 5315 0 0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 29230715 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 29230715 0 0
T1 137941 84842 0 0
T2 18926 13157 0 0
T3 130108 918494 0 0
T4 17778 12773 0 0
T5 24059 15717 0 0
T6 140836 96653 0 0
T7 11865 5615 0 0
T8 89401 34748 0 0
T9 11221 6574 0 0
T10 8047 5248 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 29989189 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 29989189 0 0
T1 137941 86342 0 0
T2 18926 13318 0 0
T3 130108 929395 0 0
T4 17778 12938 0 0
T5 24059 15922 0 0
T6 140836 97982 0 0
T7 11865 5774 0 0
T8 89401 36242 0 0
T9 11221 6740 0 0
T10 8047 5315 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 29232094 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 29232094 0 0
T1 137941 84842 0 0
T2 18926 13157 0 0
T3 130108 918494 0 0
T4 17778 12773 0 0
T5 24059 15717 0 0
T6 140836 96653 0 0
T7 11865 5615 0 0
T8 89401 34748 0 0
T9 11221 6574 0 0
T10 8047 5248 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1711728 889309 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1711728 889309 0 0
T1 4220 2613 0 0
T2 566 387 0 0
T3 39456 27860 0 0
T4 531 382 0 0
T5 720 461 0 0
T6 4271 2938 0 0
T7 354 163 0 0
T8 2757 1100 0 0
T9 335 194 0 0
T10 239 158 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 54243684 28789875 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54243684 28789875 0 0
T1 132425 82866 0 0
T2 18169 12783 0 0
T3 124905 892203 0 0
T4 17071 12421 0 0
T5 23096 15285 0 0
T6 135171 94048 0 0
T7 11391 5543 0 0
T8 85833 34785 0 0
T9 10765 6464 0 0
T10 7725 5102 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 54243684 28059524 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54243684 28059524 0 0
T1 132425 81434 0 0
T2 18169 12631 0 0
T3 124905 881732 0 0
T4 17071 12261 0 0
T5 23096 15085 0 0
T6 135171 92768 0 0
T7 11391 5391 0 0
T8 85833 33353 0 0
T9 10765 6304 0 0
T10 7725 5038 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122668 14384344 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122668 14384344 0 0
T1 66217 41416 0 0
T2 9084 6386 0 0
T3 624537 445918 0 0
T4 8534 6206 0 0
T5 11548 7634 0 0
T6 67596 47007 0 0
T7 5695 2766 0 0
T8 42910 17363 0 0
T9 5383 3231 0 0
T10 3862 2551 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122668 14019532 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122668 14019532 0 0
T1 66217 40700 0 0
T2 9084 6310 0 0
T3 624537 440682 0 0
T4 8534 6126 0 0
T5 11548 7534 0 0
T6 67596 46367 0 0
T7 5695 2690 0 0
T8 42910 16647 0 0
T9 5383 3151 0 0
T10 3862 2519 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 7164368 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 7164368 0 0
T1 33104 20641 0 0
T2 4541 3175 0 0
T3 312267 222491 0 0
T4 4267 3097 0 0
T5 5772 3790 0 0
T6 33795 23443 0 0
T7 2847 1365 0 0
T8 21454 8601 0 0
T9 2690 1607 0 0
T10 1930 1274 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6981821 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6981821 0 0
T1 33104 20283 0 0
T2 4541 3137 0 0
T3 312267 219873 0 0
T4 4267 3057 0 0
T5 5772 3740 0 0
T6 33795 23123 0 0
T7 2847 1327 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 7164368 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 7164368 0 0
T1 33104 20641 0 0
T2 4541 3175 0 0
T3 312267 222491 0 0
T4 4267 3097 0 0
T5 5772 3790 0 0
T6 33795 23443 0 0
T7 2847 1365 0 0
T8 21454 8601 0 0
T9 2690 1607 0 0
T10 1930 1274 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6981821 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6981821 0 0
T1 33104 20283 0 0
T2 4541 3137 0 0
T3 312267 219873 0 0
T4 4267 3057 0 0
T5 5772 3740 0 0
T6 33795 23123 0 0
T7 2847 1327 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122513 14384339 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122513 14384339 0 0
T1 66212 41412 0 0
T2 9084 6386 0 0
T3 624544 445933 0 0
T4 8534 6207 0 0
T5 11547 7634 0 0
T6 67597 47008 0 0
T7 5695 2766 0 0
T8 42911 17363 0 0
T9 5386 3233 0 0
T10 3863 2551 0 0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122513 14019487 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122513 14019487 0 0
T1 66212 40696 0 0
T2 9084 6310 0 0
T3 624544 440697 0 0
T4 8534 6127 0 0
T5 11547 7534 0 0
T6 67597 46368 0 0
T7 5695 2690 0 0
T8 42911 16647 0 0
T9 5386 3153 0 0
T10 3863 2519 0 0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 56505406 28926454 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 56505406 28926454 0 0
T1 137941 84014 0 0
T2 18926 12879 0 0
T3 130108 912330 0 0
T4 17778 12714 0 0
T5 24059 15282 0 0
T6 140836 95839 0 0
T7 11865 5386 0 0
T8 89401 33776 0 0
T9 11221 6462 0 0
T10 8047 5248 0 0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 7091401 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 7091401 0 0
T1 33104 20441 0 0
T2 4541 3108 0 0
T3 312267 221013 0 0
T4 4267 3083 0 0
T5 5772 3686 0 0
T6 33795 23247 0 0
T7 2847 1310 0 0
T8 21454 8368 0 0
T9 2690 1580 0 0
T10 1930 1274 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6827440 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6827440 0 0
T1 33104 20283 0 0
T2 4541 3127 0 0
T3 312267 214597 0 0
T4 4267 3057 0 0
T5 5772 3734 0 0
T6 33795 23123 0 0
T7 2847 1297 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 54243684 27449044 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 54243684 27449044 0 0
T1 132425 81434 0 0
T2 18169 12631 0 0
T3 124905 866192 0 0
T4 17071 12261 0 0
T5 23096 15085 0 0
T6 135171 92768 0 0
T7 11391 5352 0 0
T8 85833 33353 0 0
T9 10765 6304 0 0
T10 7725 5038 0 0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122668 13731033 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122668 13731033 0 0
T1 66217 40700 0 0
T2 9084 6310 0 0
T3 624537 432622 0 0
T4 8534 6126 0 0
T5 11548 7534 0 0
T6 67596 46367 0 0
T7 5695 2690 0 0
T8 42910 16647 0 0
T9 5383 3094 0 0
T10 3862 2519 0 0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 27122513 13712104 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 27122513 13712104 0 0
T1 66212 40696 0 0
T2 9084 6310 0 0
T3 624544 435287 0 0
T4 8534 6127 0 0
T5 11547 7534 0 0
T6 67597 46368 0 0
T7 5695 2690 0 0
T8 42911 16647 0 0
T9 5386 3100 0 0
T10 3863 2519 0 0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1711728 848053 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1711728 848053 0 0
T1 4220 2568 0 0
T2 566 384 0 0
T3 39456 27080 0 0
T4 531 376 0 0
T5 720 455 0 0
T6 4271 2895 0 0
T7 354 156 0 0
T8 2757 1057 0 0
T9 335 185 0 0
T10 239 156 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6833722 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6833722 0 0
T1 33104 20283 0 0
T2 4541 3137 0 0
T3 312267 215557 0 0
T4 4267 3057 0 0
T5 5772 3740 0 0
T6 33795 23123 0 0
T7 2847 1327 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6837909 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6837909 0 0
T1 33104 20283 0 0
T2 4541 3137 0 0
T3 312267 216098 0 0
T4 4267 3057 0 0
T5 5772 3740 0 0
T6 33795 23123 0 0
T7 2847 1327 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 13560952 6838472 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 13560952 6838472 0 0
T1 33104 20283 0 0
T2 4541 3137 0 0
T3 312267 217317 0 0
T4 4267 3057 0 0
T5 5772 3740 0 0
T6 33795 23123 0 0
T7 2847 1327 0 0
T8 21454 8243 0 0
T9 2690 1567 0 0
T10 1930 1258 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1711728 1029932 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1711728 1029932 0 0
T1 4220 3093 0 0
T2 566 487 0 0
T3 39456 30789 0 0
T4 531 413 0 0
T5 720 641 0 0
T6 4271 3327 0 0
T7 354 275 0 0
T8 2757 1682 0 0
T9 335 215 0 0
T10 239 160 0 0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3400
CONT_ASSIGN8211100.00
CONT_ASSIGN8511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 unreachable
82 1 1
85 1 1


Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
OutputsKnown_A 1711728 1010416 0 0


OutputsKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1711728 1010416 0 0
T1 4220 3057 0 0
T2 566 485 0 0
T3 39456 30523 0 0
T4 531 409 0 0
T5 720 639 0 0
T6 4271 3295 0 0
T7 354 273 0 0
T8 2757 1648 0 0
T9 335 211 0 0
T10 239 158 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%