Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rstmgr_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg 100.00 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.65 98.40 99.85 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.55 100.00 98.21 100.00 100.00 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_alert_info 100.00 100.00
u_alert_info_attr 33.33 33.33
u_alert_info_ctrl_en 100.00 100.00 100.00 100.00
u_alert_info_ctrl_index 100.00 100.00 100.00 100.00
u_alert_regwen 100.00 100.00 100.00 100.00
u_alert_test_fatal_cnsty_fault 100.00 100.00
u_alert_test_fatal_fault 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_cpu_info 100.00 100.00
u_cpu_info_attr 33.33 33.33
u_cpu_info_ctrl_en 100.00 100.00 100.00 100.00
u_cpu_info_ctrl_index 100.00 100.00 100.00 100.00
u_cpu_regwen 100.00 100.00 100.00 100.00
u_err_code_fsm_err 96.30 88.89 100.00 100.00
u_err_code_reg_intg_err 96.30 88.89 100.00 100.00
u_err_code_reset_consistency_err 96.30 88.89 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.97 97.14 98.75 100.00 100.00
u_reset_info_hw_req 100.00 100.00 100.00 100.00
u_reset_info_low_power_exit 100.00 100.00 100.00 100.00
u_reset_info_por 100.00 100.00 100.00 100.00
u_reset_info_sw_reset 100.00 100.00 100.00 100.00
u_reset_req 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_sw_rst_ctrl_n_0 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_1 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_2 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_3 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_4 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_5 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_6 100.00 100.00 100.00 100.00
u_sw_rst_ctrl_n_7 100.00 100.00 100.00 100.00
u_sw_rst_regwen_0 100.00 100.00 100.00 100.00
u_sw_rst_regwen_1 100.00 100.00 100.00 100.00
u_sw_rst_regwen_2 100.00 100.00 100.00 100.00
u_sw_rst_regwen_3 100.00 100.00 100.00 100.00
u_sw_rst_regwen_4 100.00 100.00 100.00 100.00
u_sw_rst_regwen_5 100.00 100.00 100.00 100.00
u_sw_rst_regwen_6 100.00 100.00 100.00 100.00
u_sw_rst_regwen_7 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : rstmgr_reg_top
Line No.TotalCoveredPercent
TOTAL178178100.00
ALWAYS7344100.00
CONT_ASSIGN8211100.00
CONT_ASSIGN9411100.00
CONT_ASSIGN9511100.00
CONT_ASSIGN12311100.00
CONT_ASSIGN12411100.00
CONT_ASSIGN22611100.00
CONT_ASSIGN24111100.00
CONT_ASSIGN25711100.00
CONT_ASSIGN43311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN88011100.00
CONT_ASSIGN91211100.00
CONT_ASSIGN94411100.00
CONT_ASSIGN97611100.00
CONT_ASSIGN100811100.00
CONT_ASSIGN104011100.00
CONT_ASSIGN107211100.00
CONT_ASSIGN110411100.00
ALWAYS12182929100.00
CONT_ASSIGN124911100.00
ALWAYS125311100.00
CONT_ASSIGN128511100.00
CONT_ASSIGN128711100.00
CONT_ASSIGN128911100.00
CONT_ASSIGN129011100.00
CONT_ASSIGN129211100.00
CONT_ASSIGN129311100.00
CONT_ASSIGN129511100.00
CONT_ASSIGN129711100.00
CONT_ASSIGN129911100.00
CONT_ASSIGN130111100.00
CONT_ASSIGN130211100.00
CONT_ASSIGN130411100.00
CONT_ASSIGN130511100.00
CONT_ASSIGN130711100.00
CONT_ASSIGN130911100.00
CONT_ASSIGN131011100.00
CONT_ASSIGN131111100.00
CONT_ASSIGN131211100.00
CONT_ASSIGN131411100.00
CONT_ASSIGN131511100.00
CONT_ASSIGN131711100.00
CONT_ASSIGN131911100.00
CONT_ASSIGN132011100.00
CONT_ASSIGN132111100.00
CONT_ASSIGN132211100.00
CONT_ASSIGN132411100.00
CONT_ASSIGN132511100.00
CONT_ASSIGN132711100.00
CONT_ASSIGN132811100.00
CONT_ASSIGN133011100.00
CONT_ASSIGN133111100.00
CONT_ASSIGN133311100.00
CONT_ASSIGN133411100.00
CONT_ASSIGN133611100.00
CONT_ASSIGN133711100.00
CONT_ASSIGN133911100.00
CONT_ASSIGN134011100.00
CONT_ASSIGN134211100.00
CONT_ASSIGN134311100.00
CONT_ASSIGN134511100.00
CONT_ASSIGN134611100.00
CONT_ASSIGN134811100.00
CONT_ASSIGN134911100.00
CONT_ASSIGN135111100.00
CONT_ASSIGN135211100.00
CONT_ASSIGN135411100.00
CONT_ASSIGN135511100.00
CONT_ASSIGN135711100.00
CONT_ASSIGN135811100.00
CONT_ASSIGN136011100.00
CONT_ASSIGN136111100.00
CONT_ASSIGN136311100.00
CONT_ASSIGN136411100.00
CONT_ASSIGN136611100.00
CONT_ASSIGN136711100.00
CONT_ASSIGN136911100.00
ALWAYS13732929100.00
ALWAYS14063838100.00
CONT_ASSIGN153900
CONT_ASSIGN154711100.00
CONT_ASSIGN154811100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
73 1 1
74 1 1
75 1 1
76 1 1
MISSING_ELSE
82 1 1
94 1 1
95 1 1
123 1 1
124 1 1
226 1 1
241 1 1
257 1 1
433 1 1
554 1 1
880 1 1
912 1 1
944 1 1
976 1 1
1008 1 1
1040 1 1
1072 1 1
1104 1 1
1218 1 1
1219 1 1
1220 1 1
1221 1 1
1222 1 1
1223 1 1
1224 1 1
1225 1 1
1226 1 1
1227 1 1
1228 1 1
1229 1 1
1230 1 1
1231 1 1
1232 1 1
1233 1 1
1234 1 1
1235 1 1
1236 1 1
1237 1 1
1238 1 1
1239 1 1
1240 1 1
1241 1 1
1242 1 1
1243 1 1
1244 1 1
1245 1 1
1246 1 1
1249 1 1
1253 1 1
1285 1 1
1287 1 1
1289 1 1
1290 1 1
1292 1 1
1293 1 1
1295 1 1
1297 1 1
1299 1 1
1301 1 1
1302 1 1
1304 1 1
1305 1 1
1307 1 1
1309 1 1
1310 1 1
1311 1 1
1312 1 1
1314 1 1
1315 1 1
1317 1 1
1319 1 1
1320 1 1
1321 1 1
1322 1 1
1324 1 1
1325 1 1
1327 1 1
1328 1 1
1330 1 1
1331 1 1
1333 1 1
1334 1 1
1336 1 1
1337 1 1
1339 1 1
1340 1 1
1342 1 1
1343 1 1
1345 1 1
1346 1 1
1348 1 1
1349 1 1
1351 1 1
1352 1 1
1354 1 1
1355 1 1
1357 1 1
1358 1 1
1360 1 1
1361 1 1
1363 1 1
1364 1 1
1366 1 1
1367 1 1
1369 1 1
1373 1 1
1374 1 1
1375 1 1
1376 1 1
1377 1 1
1378 1 1
1379 1 1
1380 1 1
1381 1 1
1382 1 1
1383 1 1
1384 1 1
1385 1 1
1386 1 1
1387 1 1
1388 1 1
1389 1 1
1390 1 1
1391 1 1
1392 1 1
1393 1 1
1394 1 1
1395 1 1
1396 1 1
1397 1 1
1398 1 1
1399 1 1
1400 1 1
1401 1 1
1406 1 1
1407 1 1
1409 1 1
1410 1 1
1414 1 1
1418 1 1
1419 1 1
1420 1 1
1421 1 1
1425 1 1
1429 1 1
1430 1 1
1434 1 1
1438 1 1
1442 1 1
1446 1 1
1447 1 1
1451 1 1
1455 1 1
1459 1 1
1463 1 1
1467 1 1
1471 1 1
1475 1 1
1479 1 1
1483 1 1
1487 1 1
1491 1 1
1495 1 1
1499 1 1
1503 1 1
1507 1 1
1511 1 1
1515 1 1
1519 1 1
1523 1 1
1524 1 1
1525 1 1
1539 unreachable
1547 1 1
1548 1 1


Cond Coverage for Module : rstmgr_reg_top
TotalCoveredPercent
Conditions331331100.00
Logical331331100.00
Non-Logical00
Event00

 LINE       63
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT65,T69,T95
11CoveredT1,T2,T3

 LINE       75
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT72,T73,T74
10CoveredT64,T65,T69

 LINE       82
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT72,T73,T74
010CoveredT64,T65,T69
100CoveredT64,T65,T69

 LINE       124
 EXPRESSION ((devmode_i & addrmiss) | wr_err | intg_err)
             -----------1----------   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT64,T65,T69
010CoveredT68,T95,T96
100CoveredT68,T95,T96

 LINE       124
 SUB-EXPRESSION (devmode_i & addrmiss)
                 ----1----   ----2---
-1--2-StatusTests
01Unreachable
10CoveredT1,T2,T3
11CoveredT68,T65,T69

 LINE       433
 EXPRESSION (alert_info_ctrl_we & alert_regwen_qs)
             ---------1--------   -------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT64,T65,T66
11CoveredT1,T2,T3

 LINE       554
 EXPRESSION (cpu_info_ctrl_we & cpu_regwen_qs)
             --------1-------   ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT64,T65,T66
11CoveredT1,T2,T3

 LINE       880
 EXPRESSION (sw_rst_ctrl_n_0_we & sw_rst_regwen_0_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T54,T67
11CoveredT2,T3,T5

 LINE       912
 EXPRESSION (sw_rst_ctrl_n_1_we & sw_rst_regwen_1_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T54,T63
11CoveredT2,T3,T5

 LINE       944
 EXPRESSION (sw_rst_ctrl_n_2_we & sw_rst_regwen_2_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT61,T62,T56
11CoveredT2,T3,T5

 LINE       976
 EXPRESSION (sw_rst_ctrl_n_3_we & sw_rst_regwen_3_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T56,T54
11CoveredT2,T3,T5

 LINE       1008
 EXPRESSION (sw_rst_ctrl_n_4_we & sw_rst_regwen_4_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T55,T54
11CoveredT2,T3,T5

 LINE       1040
 EXPRESSION (sw_rst_ctrl_n_5_we & sw_rst_regwen_5_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT61,T62,T56
11CoveredT2,T3,T5

 LINE       1072
 EXPRESSION (sw_rst_ctrl_n_6_we & sw_rst_regwen_6_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT62,T55,T54
11CoveredT2,T3,T5

 LINE       1104
 EXPRESSION (sw_rst_ctrl_n_7_we & sw_rst_regwen_7_qs)
             ---------1--------   ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT9,T62,T56
11CoveredT2,T3,T5

 LINE       1219
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_TEST_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1220
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_REQ_OFFSET)
            --------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       1221
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_RESET_INFO_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1222
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_REGWEN_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1223
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_CTRL_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1224
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_ATTR_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1225
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ALERT_INFO_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       1226
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_REGWEN_OFFSET)
            ---------------------------1--------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1227
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_CTRL_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1228
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_ATTR_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1229
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_CPU_INFO_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T4

 LINE       1230
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_0_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1231
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_1_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1232
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_2_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1233
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_3_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1234
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_4_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1235
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_5_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1236
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_6_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1237
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_REGWEN_7_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1238
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_0_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1239
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_1_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1240
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_2_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1241
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_3_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1242
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_4_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1243
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_5_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1244
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_6_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1245
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_SW_RST_CTRL_N_7_OFFSET)
            -----------------------------1-----------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1246
 EXPRESSION (reg_addr == rstmgr_reg_pkg::RSTMGR_ERR_CODE_OFFSET)
            --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T5

 LINE       1249
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       1249
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       1253
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | (addr_hit[27] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT64,T68,T69

 LINE       1253
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b1 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b1 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b1 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b1 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))) | 
     22  (addr_hit[21] & ((|(4'b1 & (~reg_be))))) | 
     23  (addr_hit[22] & ((|(4'b1 & (~reg_be))))) | 
     24  (addr_hit[23] & ((|(4'b1 & (~reg_be))))) | 
     25  (addr_hit[24] & ((|(4'b1 & (~reg_be))))) | 
     26  (addr_hit[25] & ((|(4'b1 & (~reg_be))))) | 
     27  (addr_hit[26] & ((|(4'b1 & (~reg_be))))) | 
     28  (addr_hit[27] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT1,T2,T3
28 (addr_hit[27] & ((|(4'...CoveredT1,T3,T5
27 (addr_hit[26] & ((|(4'...CoveredT1,T2,T3
26 (addr_hit[25] & ((|(4'...CoveredT1,T2,T3
25 (addr_hit[24] & ((|(4'...CoveredT1,T2,T3
24 (addr_hit[23] & ((|(4'...CoveredT1,T2,T3
23 (addr_hit[22] & ((|(4'...CoveredT1,T2,T3
22 (addr_hit[21] & ((|(4'...CoveredT1,T2,T3
21 (addr_hit[20] & ((|(4'...CoveredT1,T2,T3
20 (addr_hit[19] & ((|(4'...CoveredT1,T2,T3
19 (addr_hit[18] & ((|(4'...CoveredT1,T3,T5
18 (addr_hit[17] & ((|(4'...CoveredT1,T3,T5
17 (addr_hit[16] & ((|(4'...CoveredT1,T3,T5
16 (addr_hit[15] & ((|(4'...CoveredT1,T3,T5
15 (addr_hit[14] & ((|(4'...CoveredT1,T3,T5
14 (addr_hit[13] & ((|(4'...CoveredT1,T3,T5
13 (addr_hit[12] & ((|(4'...CoveredT1,T3,T5
12 (addr_hit[11] & ((|(4'...CoveredT1,T3,T5
11 (addr_hit[10] & ((|(4'...CoveredT1,T3,T4
10 (addr_hit[9] & ((|(4'b...CoveredT1,T3,T5
9 (addr_hit[8] & ((|(4'b...CoveredT1,T3,T5
8 (addr_hit[7] & ((|(4'b...CoveredT1,T3,T5
7 (addr_hit[6] & ((|(4'b...CoveredT1,T3,T4
6 (addr_hit[5] & ((|(4'b...CoveredT1,T3,T5
5 (addr_hit[4] & ((|(4'b...CoveredT1,T3,T5
4 (addr_hit[3] & ((|(4'b...CoveredT1,T3,T5
3 (addr_hit[2] & ((|(4'b...CoveredT1,T2,T3
2 (addr_hit[1] & ((|(4'b...CoveredT1,T3,T5
1 (addr_hit[0] & ((|(4'b...CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       1253
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T4
11CoveredT1,T3,T4

 LINE       1253
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1253
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[21] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[22] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[23] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[24] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[25] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[26] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       1253
 SUB-EXPRESSION (addr_hit[27] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T5
11CoveredT1,T3,T5

 LINE       1285
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T105,T96
111CoveredT10,T75,T76

 LINE       1290
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT68,T96,T99
111CoveredT1,T3,T4

 LINE       1293
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T105,T96
111CoveredT1,T2,T3

 LINE       1302
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T69,T95
111CoveredT64,T65,T66

 LINE       1305
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T65,T69
111CoveredT1,T2,T3

 LINE       1310
 EXPRESSION (addr_hit[5] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT105,T123,T124
111CoveredT1,T3,T6

 LINE       1311
 EXPRESSION (addr_hit[6] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT123,T124,T125
111CoveredT1,T3,T4

 LINE       1312
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT69,T105,T96
111CoveredT64,T65,T66

 LINE       1315
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T69,T97
111CoveredT1,T2,T3

 LINE       1320
 EXPRESSION (addr_hit[9] & reg_re & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT98,T126,T127
111CoveredT1,T3,T6

 LINE       1321
 EXPRESSION (addr_hit[10] & reg_re & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T4
110CoveredT128,T124,T127
111CoveredT1,T3,T4

 LINE       1322
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T95,T100
111CoveredT9,T61,T62

 LINE       1325
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT64,T68,T97
111CoveredT9,T61,T62

 LINE       1328
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T96,T99
111CoveredT9,T61,T62

 LINE       1331
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT69,T96,T101
111CoveredT9,T61,T62

 LINE       1334
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T95,T96
111CoveredT9,T61,T62

 LINE       1337
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT68,T96,T97
111CoveredT9,T61,T62

 LINE       1340
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT65,T97,T99
111CoveredT9,T61,T62

 LINE       1343
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T5
110CoveredT96,T97,T99
111CoveredT9,T61,T62

 LINE       1346
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T96,T101
111CoveredT2,T3,T5

 LINE       1349
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT64,T68,T96
111CoveredT2,T3,T5

 LINE       1352
 EXPRESSION (addr_hit[21] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT96,T97,T99
111CoveredT2,T3,T5

 LINE       1355
 EXPRESSION (addr_hit[22] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T96,T97
111CoveredT2,T3,T5

 LINE       1358
 EXPRESSION (addr_hit[23] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT64,T68,T95
111CoveredT2,T3,T5

 LINE       1361
 EXPRESSION (addr_hit[24] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT69,T96,T99
111CoveredT2,T3,T5

 LINE       1364
 EXPRESSION (addr_hit[25] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T96,T97
111CoveredT2,T3,T5

 LINE       1367
 EXPRESSION (addr_hit[26] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT68,T97,T99
111CoveredT2,T3,T5

Branch Coverage for Module : rstmgr_reg_top
Line No.TotalCoveredPercent
Branches 34 34 100.00
TERNARY 1249 2 2 100.00
IF 73 3 3 100.00
CASE 1407 29 29 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv' or '../src/lowrisc_systems_rstmgr_reg_0.1/rtl/autogen/rstmgr_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 1249 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 73 if ((!rst_ni)) -2-: 75 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T64,T65,T69
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 1407 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : rstmgr_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 12844749 1000914 0 0
reAfterRv 12844749 1000807 0 0
rePulse 12844749 536785 0 0
wePulse 12844749 464022 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 12844749 1000914 0 0
T1 28231 2686 0 0
T2 3907 206 0 0
T3 280593 19657 0 0
T4 4073 212 0 0
T5 4589 314 0 0
T6 29739 2414 0 0
T7 2046 223 0 0
T8 15919 2951 0 0
T9 2548 379 0 0
T10 1864 16 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 12844749 1000807 0 0
T1 28231 2686 0 0
T2 3907 206 0 0
T3 280593 19657 0 0
T4 4073 212 0 0
T5 4589 312 0 0
T6 29739 2414 0 0
T7 2046 217 0 0
T8 15919 2951 0 0
T9 2548 379 0 0
T10 1864 16 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 12844749 536785 0 0
T1 28231 1505 0 0
T2 3907 99 0 0
T3 280593 10868 0 0
T4 4073 99 0 0
T5 4589 153 0 0
T6 29739 1344 0 0
T7 2046 106 0 0
T8 15919 1611 0 0
T9 2548 186 0 0
T10 1864 0 0 0
T11 0 1393 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 12844749 464022 0 0
T1 28231 1181 0 0
T2 3907 107 0 0
T3 280593 8789 0 0
T4 4073 113 0 0
T5 4589 159 0 0
T6 29739 1070 0 0
T7 2046 111 0 0
T8 15919 1340 0 0
T9 2548 193 0 0
T10 1864 16 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%