Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12844749	7573	0	0
alert_regwen_rd_A	12844749	5647	0	0
cpu_regwen_rd_A	12844749	5566	0	0
sw_rst_ctrl_n_0_rd_A	12844749	9977	0	0
sw_rst_ctrl_n_1_rd_A	12844749	9801	0	0
sw_rst_ctrl_n_2_rd_A	12844749	9858	0	0
sw_rst_ctrl_n_3_rd_A	12844749	9522	0	0
sw_rst_ctrl_n_4_rd_A	12844749	10020	0	0
sw_rst_ctrl_n_5_rd_A	12844749	9706	0	0
sw_rst_ctrl_n_6_rd_A	12844749	9802	0	0
sw_rst_ctrl_n_7_rd_A	12844749	9998	0	0
sw_rst_regwen_0_rd_A	12844749	6126	0	0
sw_rst_regwen_1_rd_A	12844749	6018	0	0
sw_rst_regwen_2_rd_A	12844749	6073	0	0
sw_rst_regwen_3_rd_A	12844749	6151	0	0
sw_rst_regwen_4_rd_A	12844749	6077	0	0
sw_rst_regwen_5_rd_A	12844749	6148	0	0
sw_rst_regwen_6_rd_A	12844749	6343	0	0
sw_rst_regwen_7_rd_A	12844749	5915	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	7573	0	0
T64	11141	1	0	0
T65	23193	4	0	0
T68	5729	197	0	0
T69	22454	3	0	0
T70	3560	2	0	0
T71	2654	28	0	0
T95	2517	46	0	0
T96	4171	411	0	0
T105	21480	1	0	0
T109	2885	7	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	5647	0	0
T3	280593	412	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	38	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	26	0	0
T12	5104	0	0	0
T27	0	217	0	0
T53	0	93	0	0
T69	0	71	0	0
T70	0	16	0	0
T75	1495	0	0	0
T88	0	54	0	0
T105	0	59	0	0
T114	0	38	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	5566	0	0
T3	280593	449	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	37	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	12	0	0
T12	5104	0	0	0
T27	0	208	0	0
T53	0	101	0	0
T69	0	102	0	0
T70	0	30	0	0
T75	1495	0	0	0
T88	0	101	0	0
T105	0	58	0	0
T114	0	49	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9977	0	0
T2	3907	34	0	0
T3	280593	629	0	0
T4	4073	0	0	0
T5	4589	40	0	0
T6	29739	45	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	47	0	0
T27	0	238	0	0
T53	0	144	0	0
T75	1495	0	0	0
T88	0	77	0	0
T90	0	15	0	0
T129	0	15	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9801	0	0
T2	3907	41	0	0
T3	280593	718	0	0
T4	4073	0	0	0
T5	4589	27	0	0
T6	29739	40	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	58	0	0
T27	0	251	0	0
T53	0	143	0	0
T75	1495	0	0	0
T88	0	55	0	0
T90	0	16	0	0
T129	0	13	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9858	0	0
T2	3907	48	0	0
T3	280593	608	0	0
T4	4073	0	0	0
T5	4589	27	0	0
T6	29739	24	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	48	0	0
T27	0	262	0	0
T53	0	176	0	0
T75	1495	0	0	0
T88	0	63	0	0
T90	0	28	0	0
T129	0	11	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9522	0	0
T2	3907	40	0	0
T3	280593	635	0	0
T4	4073	0	0	0
T5	4589	41	0	0
T6	29739	35	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	11	0	0
T27	0	254	0	0
T53	0	147	0	0
T75	1495	0	0	0
T88	0	92	0	0
T90	0	15	0	0
T129	0	3	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	10020	0	0
T2	3907	41	0	0
T3	280593	660	0	0
T4	4073	0	0	0
T5	4589	54	0	0
T6	29739	47	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	18	0	0
T27	0	260	0	0
T53	0	166	0	0
T75	1495	0	0	0
T88	0	57	0	0
T90	0	17	0	0
T129	0	2	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9706	0	0
T2	3907	50	0	0
T3	280593	646	0	0
T4	4073	0	0	0
T5	4589	28	0	0
T6	29739	12	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	62	0	0
T27	0	241	0	0
T53	0	155	0	0
T75	1495	0	0	0
T88	0	46	0	0
T90	0	14	0	0
T129	0	8	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9802	0	0
T2	3907	30	0	0
T3	280593	639	0	0
T4	4073	0	0	0
T5	4589	50	0	0
T6	29739	33	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	29	0	0
T27	0	195	0	0
T53	0	156	0	0
T75	1495	0	0	0
T88	0	83	0	0
T90	0	9	0	0
T129	0	9	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	9998	0	0
T2	3907	41	0	0
T3	280593	673	0	0
T4	4073	0	0	0
T5	4589	57	0	0
T6	29739	59	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	28	0	0
T27	0	259	0	0
T53	0	123	0	0
T75	1495	0	0	0
T88	0	61	0	0
T90	0	15	0	0
T129	0	6	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6126	0	0
T3	280593	400	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	60	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	19	0	0
T12	5104	0	0	0
T27	0	201	0	0
T53	0	61	0	0
T63	0	9	0	0
T75	1495	0	0	0
T88	0	74	0	0
T130	0	28	0	0
T131	0	9	0	0
T132	0	21	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6018	0	0
T3	280593	436	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	33	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	33	0	0
T12	5104	0	0	0
T27	0	201	0	0
T53	0	54	0	0
T63	0	4	0	0
T75	1495	0	0	0
T88	0	92	0	0
T130	0	12	0	0
T131	0	2	0	0
T132	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6073	0	0
T3	280593	432	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	16	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	25	0	0
T12	5104	0	0	0
T27	0	229	0	0
T53	0	84	0	0
T63	0	3	0	0
T75	1495	0	0	0
T88	0	103	0	0
T130	0	30	0	0
T131	0	1	0	0
T132	0	37	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6151	0	0
T3	280593	423	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	17	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	60	0	0
T12	5104	0	0	0
T27	0	186	0	0
T53	0	94	0	0
T63	0	6	0	0
T75	1495	0	0	0
T88	0	67	0	0
T130	0	10	0	0
T131	0	11	0	0
T132	0	24	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6077	0	0
T3	280593	452	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	36	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	35	0	0
T12	5104	0	0	0
T27	0	142	0	0
T53	0	93	0	0
T63	0	5	0	0
T75	1495	0	0	0
T88	0	61	0	0
T130	0	16	0	0
T131	0	12	0	0
T132	0	30	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6148	0	0
T3	280593	409	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	19	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	22	0	0
T12	5104	0	0	0
T27	0	171	0	0
T53	0	105	0	0
T75	1495	0	0	0
T88	0	86	0	0
T130	0	26	0	0
T131	0	3	0	0
T132	0	34	0	0
T133	0	9	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	6343	0	0
T3	280593	448	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	20	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	23	0	0
T12	5104	0	0	0
T27	0	186	0	0
T53	0	73	0	0
T63	0	9	0	0
T75	1495	0	0	0
T88	0	66	0	0
T130	0	15	0	0
T131	0	19	0	0
T132	0	46	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12844749	5915	0	0
T3	280593	416	0	0
T4	4073	0	0	0
T5	4589	0	0	0
T6	29739	33	0	0
T7	2046	0	0	0
T8	15919	0	0	0
T9	2548	0	0	0
T10	1864	0	0	0
T11	0	38	0	0
T12	5104	0	0	0
T27	0	156	0	0
T53	0	97	0	0
T63	0	2	0	0
T75	1495	0	0	0
T88	0	49	0	0
T130	0	12	0	0
T131	0	12	0	0
T132	0	28	0	0