Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12028542	13210	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12028542	121785	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12028542	6991081	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12028542	194847	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12028542	13210	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12028542	121785	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12028542	6991081	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12028542	194847	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	13210	0	0
T1	28231	35	0	0
T2	3907	11	0	0
T3	280593	245	0	0
T4	4073	4	0	0
T5	4589	17	0	0
T6	29739	32	0	0
T7	2046	11	0	0
T8	15919	43	0	0
T9	2548	4	0	0
T10	1864	0	0	0
T11	0	32	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	121785	0	0
T1	28231	319	0	0
T2	3907	99	0	0
T3	280593	2229	0	0
T4	4073	37	0	0
T5	4589	153	0	0
T6	29739	296	0	0
T7	2046	99	0	0
T8	15919	396	0	0
T9	2548	37	0	0
T10	1864	0	0	0
T11	0	289	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	6991081	0	0
T1	28231	20277	0	0
T2	3907	3116	0	0
T3	280593	219763	0	0
T4	4073	3063	0	0
T5	4589	3708	0	0
T6	29739	23098	0	0
T7	2046	1317	0	0
T8	15919	8235	0	0
T9	2548	1562	0	0
T10	1864	1261	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	194847	0	0
T1	28231	519	0	0
T2	3907	166	0	0
T3	280593	3707	0	0
T4	4073	51	0	0
T5	4589	257	0	0
T6	29739	492	0	0
T7	2046	154	0	0
T8	15919	629	0	0
T9	2548	64	0	0
T10	1864	0	0	0
T11	0	470	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	13210	0	0
T1	28231	35	0	0
T2	3907	11	0	0
T3	280593	245	0	0
T4	4073	4	0	0
T5	4589	17	0	0
T6	29739	32	0	0
T7	2046	11	0	0
T8	15919	43	0	0
T9	2548	4	0	0
T10	1864	0	0	0
T11	0	32	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	121785	0	0
T1	28231	319	0	0
T2	3907	99	0	0
T3	280593	2229	0	0
T4	4073	37	0	0
T5	4589	153	0	0
T6	29739	296	0	0
T7	2046	99	0	0
T8	15919	396	0	0
T9	2548	37	0	0
T10	1864	0	0	0
T11	0	289	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	6991081	0	0
T1	28231	20277	0	0
T2	3907	3116	0	0
T3	280593	219763	0	0
T4	4073	3063	0	0
T5	4589	3708	0	0
T6	29739	23098	0	0
T7	2046	1317	0	0
T8	15919	8235	0	0
T9	2548	1562	0	0
T10	1864	1261	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028542	194847	0	0
T1	28231	519	0	0
T2	3907	166	0	0
T3	280593	3707	0	0
T4	4073	51	0	0
T5	4589	257	0	0
T6	29739	492	0	0
T7	2046	154	0	0
T8	15919	629	0	0
T9	2548	64	0	0
T10	1864	0	0	0
T11	0	470	0	0