Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	585643	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

352910

1

T1

1129

T3

1096

T4

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	500672	1			T1	1500		T2	1		T3	1500
values[0x0]	218582	1			T1	858		T3	874		T4	12
values[0x1]	219299	1			T1	842		T3	826		T4	11

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	491477	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

447076

1

T1

1470

T3

1394

T4

5

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3587	1			T1	9		T3	14		T8	1
valid_sources[0x01]	4002	1			T1	15		T3	13		T4	1
valid_sources[0x02]	3438	1			T1	10		T3	6		T8	1
valid_sources[0x03]	3041	1			T1	11		T3	9		T9	70
valid_sources[0x04]	3503	1			T1	6		T3	5		T21	12
valid_sources[0x05]	3346	1			T1	4		T3	17		T8	1
valid_sources[0x06]	2929	1			T1	12		T3	21		T8	4
valid_sources[0x07]	3189	1			T1	15		T3	16		T8	1
valid_sources[0x08]	3129	1			T1	2		T3	23		T21	34
valid_sources[0x09]	4274	1			T1	9		T3	5		T9	128
valid_sources[0x0a]	4177	1			T1	29		T3	15		T4	1
valid_sources[0x0b]	3277	1			T1	9		T3	20		T8	2
valid_sources[0x0c]	3037	1			T1	11		T3	15		T8	1
valid_sources[0x0d]	3056	1			T1	17		T3	15		T8	1
valid_sources[0x0e]	2935	1			T1	25		T3	3		T8	4
valid_sources[0x0f]	3320	1			T1	5		T3	9		T21	18
valid_sources[0x10]	3092	1			T1	3		T3	5		T4	2
valid_sources[0x11]	3289	1			T1	16		T3	10		T11	3
valid_sources[0x12]	4177	1			T1	8		T3	10		T8	2
valid_sources[0x13]	3608	1			T1	24		T3	18		T8	2
valid_sources[0x14]	3311	1			T1	8		T3	5		T8	2
valid_sources[0x15]	2519	1			T1	13		T3	1		T8	1
valid_sources[0x16]	3186	1			T1	8		T3	14		T21	47
valid_sources[0x17]	3960	1			T1	12		T3	8		T8	3
valid_sources[0x18]	3103	1			T1	8		T3	3		T8	1
valid_sources[0x19]	3880	1			T1	27		T3	14		T8	2
valid_sources[0x1a]	3541	1			T1	8		T3	7		T21	8
valid_sources[0x1b]	4697	1			T1	11		T3	4		T21	9
valid_sources[0x1c]	3365	1			T1	8		T3	15		T8	1
valid_sources[0x1d]	4404	1			T1	16		T3	5		T8	2
valid_sources[0x1e]	3450	1			T1	9		T3	28		T8	3
valid_sources[0x1f]	6537	1			T1	12		T3	11		T11	5
valid_sources[0x20]	3400	1			T1	2		T11	5		T21	8
valid_sources[0x21]	3830	1			T1	5		T3	19		T8	1
valid_sources[0x22]	2973	1			T1	12		T3	13		T9	14
valid_sources[0x23]	3992	1			T3	9		T4	1		T8	1
valid_sources[0x24]	3076	1			T1	10		T3	3		T4	2
valid_sources[0x25]	2901	1			T1	6		T3	24		T8	2
valid_sources[0x26]	3328	1			T1	14		T3	8		T8	1
valid_sources[0x27]	3731	1			T1	10		T3	9		T8	1
valid_sources[0x28]	2978	1			T1	6		T3	4		T9	79
valid_sources[0x29]	3664	1			T1	5		T3	5		T8	2
valid_sources[0x2a]	3199	1			T1	3		T3	6		T11	1
valid_sources[0x2b]	2467	1			T1	22		T3	8		T8	4
valid_sources[0x2c]	3682	1			T1	6		T3	8		T8	1
valid_sources[0x2d]	3097	1			T1	12		T3	27		T8	1
valid_sources[0x2e]	3377	1			T1	33		T3	18		T7	70
valid_sources[0x2f]	4652	1			T1	10		T3	5		T8	1
valid_sources[0x30]	3343	1			T1	14		T3	28		T8	5
valid_sources[0x31]	4535	1			T1	7		T3	12		T8	1
valid_sources[0x32]	2783	1			T1	17		T3	12		T68	1
valid_sources[0x33]	4437	1			T1	13		T3	5		T8	3
valid_sources[0x34]	3180	1			T1	17		T3	31		T11	1
valid_sources[0x35]	2712	1			T1	13		T3	17		T8	2
valid_sources[0x36]	3534	1			T1	9		T3	18		T21	18
valid_sources[0x37]	2785	1			T1	14		T3	7		T8	1
valid_sources[0x38]	4025	1			T1	23		T3	21		T11	2
valid_sources[0x39]	2885	1			T1	8		T3	10		T8	1
valid_sources[0x3a]	3233	1			T1	18		T3	9		T11	1
valid_sources[0x3b]	2822	1			T1	13		T3	9		T8	1
valid_sources[0x3c]	3444	1			T1	7		T3	1		T8	1
valid_sources[0x3d]	3457	1			T1	23		T3	20		T8	2
valid_sources[0x3e]	3020	1			T1	33		T3	12		T8	1
valid_sources[0x3f]	2908	1			T1	4		T3	5		T7	113
valid_sources[0x40]	4552	1			T1	9		T3	10		T21	7
valid_sources[0x41]	3527	1			T1	19		T3	18		T8	1
valid_sources[0x42]	3512	1			T1	15		T3	5		T68	2
valid_sources[0x43]	3625	1			T1	11		T3	4		T9	87
valid_sources[0x44]	2868	1			T1	17		T3	2		T8	2
valid_sources[0x45]	2953	1			T1	10		T3	18		T8	3
valid_sources[0x46]	3360	1			T1	17		T3	10		T7	226
valid_sources[0x47]	3578	1			T1	9		T3	21		T8	1
valid_sources[0x48]	3231	1			T1	21		T3	13		T5	1
valid_sources[0x49]	7584	1			T1	7		T3	2		T9	20
valid_sources[0x4a]	2680	1			T1	12		T3	22		T8	2
valid_sources[0x4b]	3440	1			T1	6		T3	3		T8	1
valid_sources[0x4c]	2851	1			T1	5		T3	11		T21	30
valid_sources[0x4d]	2894	1			T1	17		T3	6		T8	5
valid_sources[0x4e]	4687	1			T1	23		T3	5		T8	2
valid_sources[0x4f]	3365	1			T1	16		T3	7		T6	345
valid_sources[0x50]	3311	1			T1	17		T3	13		T8	1
valid_sources[0x51]	3428	1			T1	17		T3	26		T21	12
valid_sources[0x52]	2870	1			T1	17		T3	6		T21	5
valid_sources[0x53]	3314	1			T1	23		T3	15		T8	1
valid_sources[0x54]	3360	1			T1	22		T3	12		T8	3
valid_sources[0x55]	2859	1			T1	13		T3	11		T8	1
valid_sources[0x56]	3599	1			T1	8		T3	24		T7	180
valid_sources[0x57]	2665	1			T1	10		T3	11		T8	6
valid_sources[0x58]	3067	1			T1	14		T3	8		T8	4
valid_sources[0x59]	2574	1			T1	11		T3	14		T7	9
valid_sources[0x5a]	2827	1			T1	18		T3	10		T8	3
valid_sources[0x5b]	3923	1			T1	19		T3	28		T8	2
valid_sources[0x5c]	4588	1			T1	14		T3	8		T8	3
valid_sources[0x5d]	3442	1			T1	14		T3	22		T21	6
valid_sources[0x5e]	6224	1			T1	12		T3	9		T11	1
valid_sources[0x5f]	2944	1			T1	10		T3	9		T11	1
valid_sources[0x60]	2824	1			T1	8		T3	10		T8	2
valid_sources[0x61]	3693	1			T1	5		T3	26		T4	1
valid_sources[0x62]	3208	1			T1	13		T3	12		T8	4
valid_sources[0x63]	3026	1			T1	13		T3	11		T8	1
valid_sources[0x64]	6782	1			T1	6		T3	4		T21	18
valid_sources[0x65]	2924	1			T1	17		T3	2		T9	131
valid_sources[0x66]	4431	1			T1	6		T3	16		T21	9
valid_sources[0x67]	3287	1			T1	17		T3	3		T8	2
valid_sources[0x68]	4016	1			T1	19		T3	17		T4	1
valid_sources[0x69]	3850	1			T1	4		T3	16		T7	155
valid_sources[0x6a]	2969	1			T1	24		T3	15		T8	1
valid_sources[0x6b]	3133	1			T1	6		T3	24		T11	2
valid_sources[0x6c]	3725	1			T1	10		T3	8		T8	2
valid_sources[0x6d]	3278	1			T1	6		T3	26		T8	1
valid_sources[0x6e]	3291	1			T1	18		T3	15		T8	1
valid_sources[0x6f]	2616	1			T1	17		T3	2		T11	4
valid_sources[0x70]	3552	1			T1	29		T3	6		T8	1
valid_sources[0x71]	3422	1			T1	8		T3	13		T11	2
valid_sources[0x72]	5636	1			T1	8		T3	16		T8	3
valid_sources[0x73]	6442	1			T1	7		T3	13		T8	5
valid_sources[0x74]	3944	1			T1	10		T3	23		T8	1
valid_sources[0x75]	2725	1			T1	17		T3	10		T8	1
valid_sources[0x76]	6712	1			T1	9		T3	6		T8	2
valid_sources[0x77]	3580	1			T1	10		T3	6		T8	1
valid_sources[0x78]	3836	1			T1	13		T3	10		T21	1
valid_sources[0x79]	2927	1			T1	12		T3	22		T8	1
valid_sources[0x7a]	3126	1			T1	10		T3	5		T8	1
valid_sources[0x7b]	5327	1			T1	12		T8	1		T9	124
valid_sources[0x7c]	3589	1			T1	7		T3	12		T8	2
valid_sources[0x7d]	3157	1			T1	13		T3	7		T8	2
valid_sources[0x7e]	2804	1			T1	14		T3	4		T8	2
valid_sources[0x7f]	4131	1			T1	19		T3	8		T7	70
valid_sources[0x80]	3728	1			T1	19		T3	1		T21	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

235364

1

T1

701

T3

658

T6

78

values[0x0]

all_enables

biggest_size

76733

1

T1

282

T3

299

T4

4

values[0x1]

all_enables

biggest_size

40813

1

T1

146

T3

139

T6

14