Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'sh00000006,32'sh00000009)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	58.33	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val	16.67	1	100	1	64	64
mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
16.67	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	5	1	16.67

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	5	1	16.67	100	1	1	0

---

Group Instance : mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	5	1	16.67

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
others[0]	0	1	1
others[1]	0	1	1
others[2]	0	1	1
others[3]	0	1	1
false	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

true

4978

1

T1

25

T3

25

T7

19

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	697	1			T22	5		T46	10		T81	4
others[1]	650	1			T22	5		T46	4		T81	8
others[2]	682	1			T22	8		T46	5		T81	7
others[3]	1185	1			T22	7		T46	10		T81	9
false	21906	1			T1	102		T2	2		T3	102
true	2139	1			T7	7		T8	1		T11	1