Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.923359019

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.2689485651
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.3378294717
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.2526613503
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2764998838
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.3787591654
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.499225225
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.2964490862
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.4018568519
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.2375835906



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.4018568519 May 27 12:37:56 AM PDT 23 May 27 12:37:59 AM PDT 23 9191555709 ps
T2 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3378294717 May 27 12:38:05 AM PDT 23 May 27 12:38:08 AM PDT 23 11070202781 ps
T3 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.499225225 May 27 12:37:56 AM PDT 23 May 27 12:38:00 AM PDT 23 10237483560 ps
T4 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2375835906 May 27 12:39:27 AM PDT 23 May 27 12:39:30 AM PDT 23 9683568678 ps
T5 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2964490862 May 27 12:38:00 AM PDT 23 May 27 12:38:03 AM PDT 23 10370606838 ps
T6 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2764998838 May 27 12:37:54 AM PDT 23 May 27 12:37:57 AM PDT 23 11070310150 ps
T7 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2526613503 May 27 12:38:02 AM PDT 23 May 27 12:38:05 AM PDT 23 11337887039 ps
T8 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3787591654 May 27 12:37:58 AM PDT 23 May 27 12:38:01 AM PDT 23 9526174713 ps
T9 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2689485651 May 27 12:37:54 AM PDT 23 May 27 12:37:56 AM PDT 23 9429323935 ps
T10 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.923359019 May 27 12:38:06 AM PDT 23 May 27 12:38:09 AM PDT 23 9683977840 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.923359019
Short name T10
Test name
Test status
Simulation time 9683977840 ps
CPU time 2.66 seconds
Started May 27 12:38:06 AM PDT 23
Finished May 27 12:38:09 AM PDT 23
Peak memory 162364 kb
Host smart-c1b94d8b-34e9-45fd-82e5-9aba0ce6e8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923359019 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.923359019
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2689485651
Short name T9
Test name
Test status
Simulation time 9429323935 ps
CPU time 2.51 seconds
Started May 27 12:37:54 AM PDT 23
Finished May 27 12:37:56 AM PDT 23
Peak memory 161904 kb
Host smart-266570fc-346a-466d-9202-24789655882d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689485651 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.2689485651
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3378294717
Short name T2
Test name
Test status
Simulation time 11070202781 ps
CPU time 2.95 seconds
Started May 27 12:38:05 AM PDT 23
Finished May 27 12:38:08 AM PDT 23
Peak memory 162352 kb
Host smart-6ed093b4-d822-4869-901b-ee557d7a2bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378294717 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.3378294717
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2526613503
Short name T7
Test name
Test status
Simulation time 11337887039 ps
CPU time 2.88 seconds
Started May 27 12:38:02 AM PDT 23
Finished May 27 12:38:05 AM PDT 23
Peak memory 162308 kb
Host smart-471c04ed-dcda-4820-8725-ebff6cc2b83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526613503 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.2526613503
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2764998838
Short name T6
Test name
Test status
Simulation time 11070310150 ps
CPU time 2.82 seconds
Started May 27 12:37:54 AM PDT 23
Finished May 27 12:37:57 AM PDT 23
Peak memory 161944 kb
Host smart-1e172aee-52af-49cc-a5ea-56b3f6ad8bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764998838 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2764998838
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3787591654
Short name T8
Test name
Test status
Simulation time 9526174713 ps
CPU time 2.6 seconds
Started May 27 12:37:58 AM PDT 23
Finished May 27 12:38:01 AM PDT 23
Peak memory 161780 kb
Host smart-921f6d14-5c4a-47d0-b482-8fa78a5d7fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787591654 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.3787591654
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.499225225
Short name T3
Test name
Test status
Simulation time 10237483560 ps
CPU time 2.72 seconds
Started May 27 12:37:56 AM PDT 23
Finished May 27 12:38:00 AM PDT 23
Peak memory 162380 kb
Host smart-f74def90-0565-47b1-a3d2-e5156bf3c4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499225225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.499225225
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2964490862
Short name T5
Test name
Test status
Simulation time 10370606838 ps
CPU time 2.72 seconds
Started May 27 12:38:00 AM PDT 23
Finished May 27 12:38:03 AM PDT 23
Peak memory 161904 kb
Host smart-6bd47f6d-cdb6-4ec5-a7fa-f7c8d99e0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964490862 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2964490862
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.4018568519
Short name T1
Test name
Test status
Simulation time 9191555709 ps
CPU time 2.54 seconds
Started May 27 12:37:56 AM PDT 23
Finished May 27 12:37:59 AM PDT 23
Peak memory 161784 kb
Host smart-d02dec1e-7a65-4787-a7bd-d7f15f4e9dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018568519 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.4018568519
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2375835906
Short name T4
Test name
Test status
Simulation time 9683568678 ps
CPU time 2.57 seconds
Started May 27 12:39:27 AM PDT 23
Finished May 27 12:39:30 AM PDT 23
Peak memory 161900 kb
Host smart-fc0756aa-4219-4daa-b845-3099a3087955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375835906 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2375835906
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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