Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1418784378

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.3316641734
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.84810520
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.421366136
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2698644311
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.114309027
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.3649107600
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.4178574148
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.2276873691
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.2189281689



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2698644311 Sep 27 01:34:03 PM PDT 23 Sep 27 01:34:06 PM PDT 23 9429351011 ps
T2 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.4178574148 Sep 27 01:34:12 PM PDT 23 Sep 27 01:34:15 PM PDT 23 9526189878 ps
T3 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.84810520 Sep 27 01:33:29 PM PDT 23 Sep 27 01:33:32 PM PDT 23 9969325301 ps
T4 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.114309027 Sep 27 01:33:24 PM PDT 23 Sep 27 01:33:27 PM PDT 23 10237484029 ps
T5 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2276873691 Sep 27 01:33:33 PM PDT 23 Sep 27 01:33:37 PM PDT 23 10114219385 ps
T6 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3316641734 Sep 27 01:33:24 PM PDT 23 Sep 27 01:33:28 PM PDT 23 9683518577 ps
T7 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.3649107600 Sep 27 01:34:20 PM PDT 23 Sep 27 01:34:23 PM PDT 23 9271458168 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.421366136 Sep 27 01:34:08 PM PDT 23 Sep 27 01:34:11 PM PDT 23 10114086805 ps
T9 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1418784378 Sep 27 01:33:30 PM PDT 23 Sep 27 01:33:33 PM PDT 23 8893163802 ps
T10 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2189281689 Sep 27 01:35:04 PM PDT 23 Sep 27 01:35:07 PM PDT 23 11070258509 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1418784378
Short name T9
Test name
Test status
Simulation time 8893163802 ps
CPU time 2.64 seconds
Started Sep 27 01:33:30 PM PDT 23
Finished Sep 27 01:33:33 PM PDT 23
Peak memory 162724 kb
Host smart-cc61c400-f7b8-41ea-8846-916096aa7835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418784378 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1418784378
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3316641734
Short name T6
Test name
Test status
Simulation time 9683518577 ps
CPU time 2.7 seconds
Started Sep 27 01:33:24 PM PDT 23
Finished Sep 27 01:33:28 PM PDT 23
Peak memory 162704 kb
Host smart-89e962a5-a262-4111-82a7-3ffdf5f08b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316641734 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.3316641734
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.84810520
Short name T3
Test name
Test status
Simulation time 9969325301 ps
CPU time 2.77 seconds
Started Sep 27 01:33:29 PM PDT 23
Finished Sep 27 01:33:32 PM PDT 23
Peak memory 162632 kb
Host smart-90d803bc-19dd-436f-bff4-cad6444db278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84810520 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.84810520
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.421366136
Short name T8
Test name
Test status
Simulation time 10114086805 ps
CPU time 2.93 seconds
Started Sep 27 01:34:08 PM PDT 23
Finished Sep 27 01:34:11 PM PDT 23
Peak memory 162828 kb
Host smart-2f5d6aac-36e3-40c3-9f51-fa1755ed2130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421366136 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.421366136
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2698644311
Short name T1
Test name
Test status
Simulation time 9429351011 ps
CPU time 2.73 seconds
Started Sep 27 01:34:03 PM PDT 23
Finished Sep 27 01:34:06 PM PDT 23
Peak memory 162656 kb
Host smart-a737434a-7cb4-4762-a476-d0ea07f6ca98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698644311 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2698644311
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.114309027
Short name T4
Test name
Test status
Simulation time 10237484029 ps
CPU time 2.8 seconds
Started Sep 27 01:33:24 PM PDT 23
Finished Sep 27 01:33:27 PM PDT 23
Peak memory 162680 kb
Host smart-1449f9e8-11a6-4c4d-9488-4dc9f8cb17f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114309027 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.114309027
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.3649107600
Short name T7
Test name
Test status
Simulation time 9271458168 ps
CPU time 2.7 seconds
Started Sep 27 01:34:20 PM PDT 23
Finished Sep 27 01:34:23 PM PDT 23
Peak memory 162736 kb
Host smart-b57d919d-8c0f-4db1-9315-2225802c5686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649107600 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.3649107600
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.4178574148
Short name T2
Test name
Test status
Simulation time 9526189878 ps
CPU time 2.72 seconds
Started Sep 27 01:34:12 PM PDT 23
Finished Sep 27 01:34:15 PM PDT 23
Peak memory 162736 kb
Host smart-47ddb156-bea8-4672-807f-7dfac63c81b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178574148 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.4178574148
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2276873691
Short name T5
Test name
Test status
Simulation time 10114219385 ps
CPU time 2.75 seconds
Started Sep 27 01:33:33 PM PDT 23
Finished Sep 27 01:33:37 PM PDT 23
Peak memory 162616 kb
Host smart-404a938d-5481-40a3-8fb7-99c55e38b0fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276873691 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.2276873691
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2189281689
Short name T10
Test name
Test status
Simulation time 11070258509 ps
CPU time 2.94 seconds
Started Sep 27 01:35:04 PM PDT 23
Finished Sep 27 01:35:07 PM PDT 23
Peak memory 162672 kb
Host smart-e21962e0-fb7b-4efe-bd82-cba999c80336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189281689 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2189281689
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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