Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2848038167

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.616660022
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.2094333548
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.280649043
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1112071226
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.2330309214
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.2673007625
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.2145966480
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.530543861
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.1581437761



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.280649043 Oct 01 12:19:23 PM PDT 23 Oct 01 12:19:25 PM PDT 23 9067963479 ps
T2 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2848038167 Oct 01 12:14:20 PM PDT 23 Oct 01 12:14:23 PM PDT 23 10769792791 ps
T3 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2094333548 Oct 01 12:14:42 PM PDT 23 Oct 01 12:14:45 PM PDT 23 10114199071 ps
T4 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.1581437761 Oct 01 12:21:47 PM PDT 23 Oct 01 12:21:50 PM PDT 23 9683959380 ps
T5 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2673007625 Oct 01 12:14:16 PM PDT 23 Oct 01 12:14:19 PM PDT 23 10114116133 ps
T6 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.530543861 Oct 01 12:21:26 PM PDT 23 Oct 01 12:21:29 PM PDT 23 9153216434 ps
T7 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2330309214 Oct 01 12:17:31 PM PDT 23 Oct 01 12:17:35 PM PDT 23 10619487277 ps
T8 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2145966480 Oct 01 12:15:11 PM PDT 23 Oct 01 12:15:14 PM PDT 23 8854701204 ps
T9 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.616660022 Oct 01 12:21:17 PM PDT 23 Oct 01 12:21:22 PM PDT 23 8726177157 ps
T10 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1112071226 Oct 01 12:14:49 PM PDT 23 Oct 01 12:14:52 PM PDT 23 11203236828 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2848038167
Short name T2
Test name
Test status
Simulation time 10769792791 ps
CPU time 2.91 seconds
Started Oct 01 12:14:20 PM PDT 23
Finished Oct 01 12:14:23 PM PDT 23
Peak memory 162756 kb
Host smart-4dbe1155-d72e-41e1-a1b6-fa3c4c1027ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848038167 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.2848038167
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.616660022
Short name T9
Test name
Test status
Simulation time 8726177157 ps
CPU time 2.51 seconds
Started Oct 01 12:21:17 PM PDT 23
Finished Oct 01 12:21:22 PM PDT 23
Peak memory 162560 kb
Host smart-c2458831-0050-49ec-ba23-08e6202be88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616660022 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.616660022
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2094333548
Short name T3
Test name
Test status
Simulation time 10114199071 ps
CPU time 2.79 seconds
Started Oct 01 12:14:42 PM PDT 23
Finished Oct 01 12:14:45 PM PDT 23
Peak memory 162620 kb
Host smart-615b1a84-faac-4465-9d47-45eee160c5bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094333548 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.2094333548
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.280649043
Short name T1
Test name
Test status
Simulation time 9067963479 ps
CPU time 2.65 seconds
Started Oct 01 12:19:23 PM PDT 23
Finished Oct 01 12:19:25 PM PDT 23
Peak memory 162192 kb
Host smart-e1a3a538-4678-4d68-80f8-dfac90d0f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280649043 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.280649043
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1112071226
Short name T10
Test name
Test status
Simulation time 11203236828 ps
CPU time 3.04 seconds
Started Oct 01 12:14:49 PM PDT 23
Finished Oct 01 12:14:52 PM PDT 23
Peak memory 162712 kb
Host smart-a7a69d19-1543-46a1-af92-ec0c29f9d1b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112071226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1112071226
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2330309214
Short name T7
Test name
Test status
Simulation time 10619487277 ps
CPU time 2.99 seconds
Started Oct 01 12:17:31 PM PDT 23
Finished Oct 01 12:17:35 PM PDT 23
Peak memory 162748 kb
Host smart-fb7843c6-3f2b-4593-90de-5f34bd60d663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330309214 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.2330309214
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2673007625
Short name T5
Test name
Test status
Simulation time 10114116133 ps
CPU time 2.84 seconds
Started Oct 01 12:14:16 PM PDT 23
Finished Oct 01 12:14:19 PM PDT 23
Peak memory 162748 kb
Host smart-5ee713cd-6898-4748-9041-3867384f368c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673007625 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.2673007625
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2145966480
Short name T8
Test name
Test status
Simulation time 8854701204 ps
CPU time 2.58 seconds
Started Oct 01 12:15:11 PM PDT 23
Finished Oct 01 12:15:14 PM PDT 23
Peak memory 162708 kb
Host smart-44e358aa-8284-4b6e-8842-9638f933b03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145966480 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2145966480
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.530543861
Short name T6
Test name
Test status
Simulation time 9153216434 ps
CPU time 2.6 seconds
Started Oct 01 12:21:26 PM PDT 23
Finished Oct 01 12:21:29 PM PDT 23
Peak memory 162512 kb
Host smart-421d8464-9062-4ae8-a803-1ff092fb7f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530543861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.530543861
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.1581437761
Short name T4
Test name
Test status
Simulation time 9683959380 ps
CPU time 2.71 seconds
Started Oct 01 12:21:47 PM PDT 23
Finished Oct 01 12:21:50 PM PDT 23
Peak memory 162176 kb
Host smart-4077bc27-591d-4588-a4ef-b3c2b3f9902d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581437761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.1581437761
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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