Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.950367175

Tests that do not contribute to grading

Name
/workspace/coverage/default/0.rstmgr_cnsty_chk_test.4071728594
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.1898814237
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.1111904370
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.4289781809
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.1113222532
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1438183504
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.3234615263
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.3605193059
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.4213619561



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1111904370 Oct 04 12:22:39 PM PDT 23 Oct 04 12:22:42 PM PDT 23 9969282503 ps
T2 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1898814237 Oct 04 12:39:56 PM PDT 23 Oct 04 12:39:59 PM PDT 23 9812191297 ps
T3 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.950367175 Oct 04 12:39:56 PM PDT 23 Oct 04 12:39:59 PM PDT 23 9526218197 ps
T4 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.4213619561 Oct 04 12:39:54 PM PDT 23 Oct 04 12:39:57 PM PDT 23 9271476299 ps
T5 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3605193059 Oct 04 12:32:57 PM PDT 23 Oct 04 12:33:00 PM PDT 23 9046523083 ps
T6 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3234615263 Oct 04 12:21:31 PM PDT 23 Oct 04 12:21:35 PM PDT 23 10932627287 ps
T7 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.4289781809 Oct 04 12:32:59 PM PDT 23 Oct 04 12:33:02 PM PDT 23 8764406820 ps
T8 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.4071728594 Oct 04 12:29:57 PM PDT 23 Oct 04 12:30:00 PM PDT 23 9289666370 ps
T9 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1438183504 Oct 04 12:17:13 PM PDT 23 Oct 04 12:17:16 PM PDT 23 10769627088 ps
T10 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1113222532 Oct 04 12:27:39 PM PDT 23 Oct 04 12:27:43 PM PDT 23 9969203798 ps

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.950367175
Short name T3
Test name
Test status
Simulation time 9526218197 ps
CPU time 2.7 seconds
Started Oct 04 12:39:56 PM PDT 23
Finished Oct 04 12:39:59 PM PDT 23
Peak memory 162664 kb
Host smart-73a116b7-779d-4dd6-8c2e-b13473837926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950367175 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.950367175
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.4071728594
Short name T8
Test name
Test status
Simulation time 9289666370 ps
CPU time 2.67 seconds
Started Oct 04 12:29:57 PM PDT 23
Finished Oct 04 12:30:00 PM PDT 23
Peak memory 162520 kb
Host smart-206b0459-9346-458c-9681-0198d4f2550b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071728594 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.4071728594
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1898814237
Short name T2
Test name
Test status
Simulation time 9812191297 ps
CPU time 2.82 seconds
Started Oct 04 12:39:56 PM PDT 23
Finished Oct 04 12:39:59 PM PDT 23
Peak memory 162564 kb
Host smart-69bd1919-4b2d-4156-ba22-7569a260cda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898814237 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1898814237
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1111904370
Short name T1
Test name
Test status
Simulation time 9969282503 ps
CPU time 2.77 seconds
Started Oct 04 12:22:39 PM PDT 23
Finished Oct 04 12:22:42 PM PDT 23
Peak memory 162460 kb
Host smart-681c3f66-84cf-4903-a243-6efb8f3aed85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111904370 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1111904370
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.4289781809
Short name T7
Test name
Test status
Simulation time 8764406820 ps
CPU time 2.57 seconds
Started Oct 04 12:32:59 PM PDT 23
Finished Oct 04 12:33:02 PM PDT 23
Peak memory 162592 kb
Host smart-8fa60e83-c962-4eae-a58c-9910bc8e30ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289781809 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.4289781809
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1113222532
Short name T10
Test name
Test status
Simulation time 9969203798 ps
CPU time 2.77 seconds
Started Oct 04 12:27:39 PM PDT 23
Finished Oct 04 12:27:43 PM PDT 23
Peak memory 162468 kb
Host smart-87a6540d-cb8b-4bb1-b03f-db02edaad37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113222532 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1113222532
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1438183504
Short name T9
Test name
Test status
Simulation time 10769627088 ps
CPU time 2.99 seconds
Started Oct 04 12:17:13 PM PDT 23
Finished Oct 04 12:17:16 PM PDT 23
Peak memory 162400 kb
Host smart-d825b54b-c61c-41f6-a4fd-f6278d0a13eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438183504 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1438183504
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3234615263
Short name T6
Test name
Test status
Simulation time 10932627287 ps
CPU time 2.98 seconds
Started Oct 04 12:21:31 PM PDT 23
Finished Oct 04 12:21:35 PM PDT 23
Peak memory 162592 kb
Host smart-9b51cf00-21c6-425c-b9bd-6ee765a8930d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234615263 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.3234615263
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3605193059
Short name T5
Test name
Test status
Simulation time 9046523083 ps
CPU time 2.64 seconds
Started Oct 04 12:32:57 PM PDT 23
Finished Oct 04 12:33:00 PM PDT 23
Peak memory 162596 kb
Host smart-07cb6b4b-01c4-47b9-8fc0-f3a810ca86a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605193059 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.3605193059
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.4213619561
Short name T4
Test name
Test status
Simulation time 9271476299 ps
CPU time 2.64 seconds
Started Oct 04 12:39:54 PM PDT 23
Finished Oct 04 12:39:57 PM PDT 23
Peak memory 162516 kb
Host smart-721e32f3-0dab-4f3c-9d3c-05663de1f186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213619561 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.4213619561
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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