Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.4050942188

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.4104973721
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.3390431296
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.631163850
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1033498454
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.801777225
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.988783713
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.2516606861
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.1273704088
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.228012757



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.988783713 Oct 08 12:23:26 PM PDT 23 Oct 08 12:23:30 PM PDT 23 9969328243 ps
T2 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.4104973721 Oct 08 12:44:05 PM PDT 23 Oct 08 12:44:08 PM PDT 23 9969405250 ps
T3 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.4050942188 Oct 08 12:23:31 PM PDT 23 Oct 08 12:23:34 PM PDT 23 9812240030 ps
T4 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1033498454 Oct 08 12:27:35 PM PDT 23 Oct 08 12:27:37 PM PDT 23 9192478372 ps
T5 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.631163850 Oct 08 12:42:29 PM PDT 23 Oct 08 12:42:32 PM PDT 23 11337988274 ps
T6 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.801777225 Oct 08 12:41:09 PM PDT 23 Oct 08 12:41:12 PM PDT 23 11203294359 ps
T7 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2516606861 Oct 08 12:41:02 PM PDT 23 Oct 08 12:41:05 PM PDT 23 10492058166 ps
T8 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3390431296 Oct 08 12:24:17 PM PDT 23 Oct 08 12:24:20 PM PDT 23 9526188145 ps
T9 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.228012757 Oct 08 12:40:59 PM PDT 23 Oct 08 12:41:02 PM PDT 23 9526166330 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.1273704088 Oct 08 12:24:17 PM PDT 23 Oct 08 12:24:20 PM PDT 23 9683569907 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.4050942188
Short name T3
Test name
Test status
Simulation time 9812240030 ps
CPU time 2.78 seconds
Started Oct 08 12:23:31 PM PDT 23
Finished Oct 08 12:23:34 PM PDT 23
Peak memory 162820 kb
Host smart-04f54d7c-7f44-41e4-8458-3cca66891dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050942188 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.4050942188
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.4104973721
Short name T2
Test name
Test status
Simulation time 9969405250 ps
CPU time 2.81 seconds
Started Oct 08 12:44:05 PM PDT 23
Finished Oct 08 12:44:08 PM PDT 23
Peak memory 162668 kb
Host smart-b1d6ee59-1c28-42ce-8c7c-78e9d827d3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104973721 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.4104973721
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3390431296
Short name T8
Test name
Test status
Simulation time 9526188145 ps
CPU time 2.77 seconds
Started Oct 08 12:24:17 PM PDT 23
Finished Oct 08 12:24:20 PM PDT 23
Peak memory 162720 kb
Host smart-afb355b8-3f2e-4c1c-8e0a-8ec68d229f18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390431296 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.3390431296
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.631163850
Short name T5
Test name
Test status
Simulation time 11337988274 ps
CPU time 3.32 seconds
Started Oct 08 12:42:29 PM PDT 23
Finished Oct 08 12:42:32 PM PDT 23
Peak memory 162560 kb
Host smart-afc809a7-6a94-4f75-bf0e-2bfd5ff661d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631163850 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.631163850
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1033498454
Short name T4
Test name
Test status
Simulation time 9192478372 ps
CPU time 2.68 seconds
Started Oct 08 12:27:35 PM PDT 23
Finished Oct 08 12:27:37 PM PDT 23
Peak memory 162784 kb
Host smart-578b90e6-0b3c-4335-a034-19cca9e2d369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033498454 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1033498454
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.801777225
Short name T6
Test name
Test status
Simulation time 11203294359 ps
CPU time 3 seconds
Started Oct 08 12:41:09 PM PDT 23
Finished Oct 08 12:41:12 PM PDT 23
Peak memory 162792 kb
Host smart-10302d77-ddd1-4f42-b3ac-e3ddea68beb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801777225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.801777225
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.988783713
Short name T1
Test name
Test status
Simulation time 9969328243 ps
CPU time 2.83 seconds
Started Oct 08 12:23:26 PM PDT 23
Finished Oct 08 12:23:30 PM PDT 23
Peak memory 162856 kb
Host smart-eb3db206-21fa-433f-8172-0add43a54b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988783713 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.988783713
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2516606861
Short name T7
Test name
Test status
Simulation time 10492058166 ps
CPU time 2.92 seconds
Started Oct 08 12:41:02 PM PDT 23
Finished Oct 08 12:41:05 PM PDT 23
Peak memory 162512 kb
Host smart-e13245bc-3b9e-4fd5-86dc-d2b43c36ddb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516606861 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2516606861
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.1273704088
Short name T10
Test name
Test status
Simulation time 9683569907 ps
CPU time 2.83 seconds
Started Oct 08 12:24:17 PM PDT 23
Finished Oct 08 12:24:20 PM PDT 23
Peak memory 162808 kb
Host smart-81dac611-1004-47ee-89ce-f04c310fa703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273704088 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.1273704088
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.228012757
Short name T9
Test name
Test status
Simulation time 9526166330 ps
CPU time 2.8 seconds
Started Oct 08 12:40:59 PM PDT 23
Finished Oct 08 12:41:02 PM PDT 23
Peak memory 162652 kb
Host smart-cb301958-9dde-46d6-aba0-75a66a4c618b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228012757 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.228012757
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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