Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1507120123

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.2161194226
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.1497887883
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.1132282957
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.3279793993
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.1318699711
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.2321393981
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.2418120301
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.3803780357
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.3417804914



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3803780357 Oct 11 12:58:00 PM PDT 23 Oct 11 12:58:04 PM PDT 23 8990880051 ps
T2 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1318699711 Oct 11 12:58:00 PM PDT 23 Oct 11 12:58:04 PM PDT 23 10769843321 ps
T3 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2418120301 Oct 11 12:57:54 PM PDT 23 Oct 11 12:57:58 PM PDT 23 10492077967 ps
T4 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2321393981 Oct 11 12:57:27 PM PDT 23 Oct 11 12:57:30 PM PDT 23 10370227511 ps
T5 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2161194226 Oct 11 12:57:14 PM PDT 23 Oct 11 12:57:22 PM PDT 23 9329231574 ps
T6 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3417804914 Oct 11 12:57:52 PM PDT 23 Oct 11 12:58:01 PM PDT 23 11203294030 ps
T7 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1497887883 Oct 11 12:57:56 PM PDT 23 Oct 11 12:58:00 PM PDT 23 11337844752 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1132282957 Oct 11 12:57:59 PM PDT 23 Oct 11 12:58:04 PM PDT 23 9156475286 ps
T9 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.3279793993 Oct 11 12:57:25 PM PDT 23 Oct 11 12:57:28 PM PDT 23 10492107407 ps
T10 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1507120123 Oct 11 12:57:01 PM PDT 23 Oct 11 12:57:04 PM PDT 23 9015226516 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1507120123
Short name T10
Test name
Test status
Simulation time 9015226516 ps
CPU time 2.64 seconds
Started Oct 11 12:57:01 PM PDT 23
Finished Oct 11 12:57:04 PM PDT 23
Peak memory 162752 kb
Host smart-6e0b4ece-df4c-4874-a160-a5eb4f83eafc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507120123 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1507120123
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2161194226
Short name T5
Test name
Test status
Simulation time 9329231574 ps
CPU time 2.61 seconds
Started Oct 11 12:57:14 PM PDT 23
Finished Oct 11 12:57:22 PM PDT 23
Peak memory 162680 kb
Host smart-eaea5be3-52d2-4dc2-beaf-b612b1b61b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161194226 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.2161194226
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1497887883
Short name T7
Test name
Test status
Simulation time 11337844752 ps
CPU time 2.98 seconds
Started Oct 11 12:57:56 PM PDT 23
Finished Oct 11 12:58:00 PM PDT 23
Peak memory 162764 kb
Host smart-e33a127c-a18a-4773-8d26-7a6f523195f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497887883 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1497887883
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1132282957
Short name T8
Test name
Test status
Simulation time 9156475286 ps
CPU time 2.61 seconds
Started Oct 11 12:57:59 PM PDT 23
Finished Oct 11 12:58:04 PM PDT 23
Peak memory 162688 kb
Host smart-f7fb9565-ebc5-45a2-8e6c-3b350f319368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132282957 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1132282957
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.3279793993
Short name T9
Test name
Test status
Simulation time 10492107407 ps
CPU time 2.87 seconds
Started Oct 11 12:57:25 PM PDT 23
Finished Oct 11 12:57:28 PM PDT 23
Peak memory 162752 kb
Host smart-700722ad-683c-4fea-b3d9-756b815297a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279793993 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.3279793993
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1318699711
Short name T2
Test name
Test status
Simulation time 10769843321 ps
CPU time 2.88 seconds
Started Oct 11 12:58:00 PM PDT 23
Finished Oct 11 12:58:04 PM PDT 23
Peak memory 162652 kb
Host smart-e25deba4-e38d-4c24-a461-67a5f6e70e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318699711 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1318699711
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2321393981
Short name T4
Test name
Test status
Simulation time 10370227511 ps
CPU time 2.83 seconds
Started Oct 11 12:57:27 PM PDT 23
Finished Oct 11 12:57:30 PM PDT 23
Peak memory 162624 kb
Host smart-4594911c-28f2-4341-9444-fbff9a0db783
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321393981 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.2321393981
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2418120301
Short name T3
Test name
Test status
Simulation time 10492077967 ps
CPU time 2.86 seconds
Started Oct 11 12:57:54 PM PDT 23
Finished Oct 11 12:57:58 PM PDT 23
Peak memory 162724 kb
Host smart-fd91e7cb-fd01-41b9-9f43-efe6eabe8f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418120301 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2418120301
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3803780357
Short name T1
Test name
Test status
Simulation time 8990880051 ps
CPU time 2.67 seconds
Started Oct 11 12:58:00 PM PDT 23
Finished Oct 11 12:58:04 PM PDT 23
Peak memory 162688 kb
Host smart-d91aa37b-f11e-464f-815a-ddc329a8cff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803780357 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.3803780357
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3417804914
Short name T6
Test name
Test status
Simulation time 11203294030 ps
CPU time 2.98 seconds
Started Oct 11 12:57:52 PM PDT 23
Finished Oct 11 12:58:01 PM PDT 23
Peak memory 162708 kb
Host smart-7e445122-4e36-4008-90f7-9bf898a8349e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417804914 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.3417804914
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%