Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.890814973

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.3751273848
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.1229981335
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.2242818819
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2427980614
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.2064854393
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.3356178351
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.4234639910
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.2927003199
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.3363105898



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.890814973 Oct 15 12:34:20 PM PDT 23 Oct 15 12:34:23 PM PDT 23 9213697412 ps
T2 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2927003199 Oct 15 12:34:24 PM PDT 23 Oct 15 12:34:27 PM PDT 23 10114115118 ps
T3 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2064854393 Oct 15 12:34:15 PM PDT 23 Oct 15 12:34:19 PM PDT 23 10114117956 ps
T4 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2427980614 Oct 15 12:34:24 PM PDT 23 Oct 15 12:34:27 PM PDT 23 9429322733 ps
T5 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1229981335 Oct 15 12:35:08 PM PDT 23 Oct 15 12:35:11 PM PDT 23 9156841330 ps
T6 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.3356178351 Oct 15 12:34:12 PM PDT 23 Oct 15 12:34:16 PM PDT 23 9526166021 ps
T7 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3363105898 Oct 15 12:34:43 PM PDT 23 Oct 15 12:34:46 PM PDT 23 9114552726 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2242818819 Oct 15 12:35:00 PM PDT 23 Oct 15 12:35:04 PM PDT 23 10237400034 ps
T9 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3751273848 Oct 15 12:34:23 PM PDT 23 Oct 15 12:34:27 PM PDT 23 11070341854 ps
T10 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.4234639910 Oct 15 12:34:56 PM PDT 23 Oct 15 12:34:59 PM PDT 23 9684079962 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.890814973
Short name T1
Test name
Test status
Simulation time 9213697412 ps
CPU time 2.62 seconds
Started Oct 15 12:34:20 PM PDT 23
Finished Oct 15 12:34:23 PM PDT 23
Peak memory 162548 kb
Host smart-63e6cab7-d97c-4c34-a80e-d960fee97917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890814973 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.890814973
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3751273848
Short name T9
Test name
Test status
Simulation time 11070341854 ps
CPU time 2.9 seconds
Started Oct 15 12:34:23 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 162628 kb
Host smart-e9132398-21ee-45e7-82d6-2cb11a693050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751273848 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.3751273848
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1229981335
Short name T5
Test name
Test status
Simulation time 9156841330 ps
CPU time 2.58 seconds
Started Oct 15 12:35:08 PM PDT 23
Finished Oct 15 12:35:11 PM PDT 23
Peak memory 162628 kb
Host smart-8237384c-17b9-4efd-91f9-2c6cb81552e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229981335 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1229981335
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2242818819
Short name T8
Test name
Test status
Simulation time 10237400034 ps
CPU time 2.85 seconds
Started Oct 15 12:35:00 PM PDT 23
Finished Oct 15 12:35:04 PM PDT 23
Peak memory 162628 kb
Host smart-e329ded5-50b6-4807-88c8-8eb6701a8c12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242818819 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.2242818819
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2427980614
Short name T4
Test name
Test status
Simulation time 9429322733 ps
CPU time 2.67 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 162552 kb
Host smart-ad5ac569-18b4-479d-83f3-ff5acb2d2fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427980614 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2427980614
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2064854393
Short name T3
Test name
Test status
Simulation time 10114117956 ps
CPU time 2.78 seconds
Started Oct 15 12:34:15 PM PDT 23
Finished Oct 15 12:34:19 PM PDT 23
Peak memory 162612 kb
Host smart-88c8dd06-cfd1-4d83-90fb-e29c3316f98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2064854393 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.2064854393
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.3356178351
Short name T6
Test name
Test status
Simulation time 9526166021 ps
CPU time 2.7 seconds
Started Oct 15 12:34:12 PM PDT 23
Finished Oct 15 12:34:16 PM PDT 23
Peak memory 162552 kb
Host smart-6da7bcf0-3af1-40bf-9532-1f46376cdcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356178351 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.3356178351
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.4234639910
Short name T10
Test name
Test status
Simulation time 9684079962 ps
CPU time 2.77 seconds
Started Oct 15 12:34:56 PM PDT 23
Finished Oct 15 12:34:59 PM PDT 23
Peak memory 162760 kb
Host smart-6e1e3f58-e1f3-468c-b251-cd025d97f5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234639910 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.4234639910
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2927003199
Short name T2
Test name
Test status
Simulation time 10114115118 ps
CPU time 2.8 seconds
Started Oct 15 12:34:24 PM PDT 23
Finished Oct 15 12:34:27 PM PDT 23
Peak memory 162580 kb
Host smart-5d73f151-b894-471b-acec-a30c1ccd9366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927003199 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.2927003199
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3363105898
Short name T7
Test name
Test status
Simulation time 9114552726 ps
CPU time 2.64 seconds
Started Oct 15 12:34:43 PM PDT 23
Finished Oct 15 12:34:46 PM PDT 23
Peak memory 162564 kb
Host smart-ed6ff51e-5ca6-4086-9537-e35499324373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363105898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.3363105898
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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