Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.9574687506969394175167067997480132693493277135756942529902689858250114639248

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.104493220137308846449399100232508398745123569344080685876463953512274840476103
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.9366195121120729940873444085793601091052425673414717216338987383743502151687
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.104710124797414671363673996901268517710431503753905588628117788659966441107746
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.46863206606717528885289217545845593254412361710621052774871940622170612605440
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.59816517481687661946565937271848079225760844333024399086599321056810888611063
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.82359393290065233883337241650263253359404735599530771014470627293199108779392
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.72764282833753134025517506766281266167929251639763382443939542632102643305015
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.24230590060401079035875179528979696691277361722296210683914656905964957700975
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.50024391696636571932427847627331705612384293081078724534772783905783971320012



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.9366195121120729940873444085793601091052425673414717216338987383743502151687 Oct 18 12:26:21 PM PDT 23 Oct 18 12:26:25 PM PDT 23 9684159183 ps
T2 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.59816517481687661946565937271848079225760844333024399086599321056810888611063 Oct 18 12:26:03 PM PDT 23 Oct 18 12:26:06 PM PDT 23 9684159183 ps
T3 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.46863206606717528885289217545845593254412361710621052774871940622170612605440 Oct 18 12:23:31 PM PDT 23 Oct 18 12:23:34 PM PDT 23 9684159183 ps
T4 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.9574687506969394175167067997480132693493277135756942529902689858250114639248 Oct 18 12:26:32 PM PDT 23 Oct 18 12:26:35 PM PDT 23 9684159183 ps
T5 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.104493220137308846449399100232508398745123569344080685876463953512274840476103 Oct 18 12:26:31 PM PDT 23 Oct 18 12:26:34 PM PDT 23 9684159183 ps
T6 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.72764282833753134025517506766281266167929251639763382443939542632102643305015 Oct 18 12:26:23 PM PDT 23 Oct 18 12:26:26 PM PDT 23 9684159183 ps
T7 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.50024391696636571932427847627331705612384293081078724534772783905783971320012 Oct 18 12:26:00 PM PDT 23 Oct 18 12:26:04 PM PDT 23 9684159183 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.104710124797414671363673996901268517710431503753905588628117788659966441107746 Oct 18 12:26:00 PM PDT 23 Oct 18 12:26:04 PM PDT 23 9684159183 ps
T9 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.24230590060401079035875179528979696691277361722296210683914656905964957700975 Oct 18 12:21:25 PM PDT 23 Oct 18 12:21:28 PM PDT 23 9684159183 ps
T10 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.82359393290065233883337241650263253359404735599530771014470627293199108779392 Oct 18 12:27:31 PM PDT 23 Oct 18 12:27:34 PM PDT 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.9574687506969394175167067997480132693493277135756942529902689858250114639248
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.74 seconds
Started Oct 18 12:26:32 PM PDT 23
Finished Oct 18 12:26:35 PM PDT 23
Peak memory 162612 kb
Host smart-8c6efc4b-4bfe-41c8-a99d-e9928f49b594
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9574687506969394175167067997480132693493277135756942529902689858250114639248 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.957
4687506969394175167067997480132693493277135756942529902689858250114639248
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.104493220137308846449399100232508398745123569344080685876463953512274840476103
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.8 seconds
Started Oct 18 12:26:31 PM PDT 23
Finished Oct 18 12:26:34 PM PDT 23
Peak memory 162588 kb
Host smart-b22b89f5-3291-4726-8a0b-0d830e6d4447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104493220137308846449399100232508398745123569344080685876463953512274840476103 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.1
04493220137308846449399100232508398745123569344080685876463953512274840476103
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.9366195121120729940873444085793601091052425673414717216338987383743502151687
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 18 12:26:21 PM PDT 23
Finished Oct 18 12:26:25 PM PDT 23
Peak memory 162320 kb
Host smart-a26ff1cf-a502-4f22-b6ee-299be31865ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9366195121120729940873444085793601091052425673414717216338987383743502151687 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.936
6195121120729940873444085793601091052425673414717216338987383743502151687
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.104710124797414671363673996901268517710431503753905588628117788659966441107746
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.79 seconds
Started Oct 18 12:26:00 PM PDT 23
Finished Oct 18 12:26:04 PM PDT 23
Peak memory 162380 kb
Host smart-21817220-b14e-465c-9d9b-b049cb366419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104710124797414671363673996901268517710431503753905588628117788659966441107746 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1
04710124797414671363673996901268517710431503753905588628117788659966441107746
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.46863206606717528885289217545845593254412361710621052774871940622170612605440
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.8 seconds
Started Oct 18 12:23:31 PM PDT 23
Finished Oct 18 12:23:34 PM PDT 23
Peak memory 162568 kb
Host smart-7e6d1dfd-9a8f-4195-a6ac-70a9ea894192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46863206606717528885289217545845593254412361710621052774871940622170612605440 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.46
863206606717528885289217545845593254412361710621052774871940622170612605440
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.59816517481687661946565937271848079225760844333024399086599321056810888611063
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Oct 18 12:26:03 PM PDT 23
Finished Oct 18 12:26:06 PM PDT 23
Peak memory 162144 kb
Host smart-161a79e6-c4e5-4f3d-8689-35058a435496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59816517481687661946565937271848079225760844333024399086599321056810888611063 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.59
816517481687661946565937271848079225760844333024399086599321056810888611063
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.82359393290065233883337241650263253359404735599530771014470627293199108779392
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Oct 18 12:27:31 PM PDT 23
Finished Oct 18 12:27:34 PM PDT 23
Peak memory 162380 kb
Host smart-74cb6ee3-8e92-41f8-adac-b11d13966533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82359393290065233883337241650263253359404735599530771014470627293199108779392 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.82
359393290065233883337241650263253359404735599530771014470627293199108779392
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.72764282833753134025517506766281266167929251639763382443939542632102643305015
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Oct 18 12:26:23 PM PDT 23
Finished Oct 18 12:26:26 PM PDT 23
Peak memory 162580 kb
Host smart-05d61028-45db-444b-af96-748dab9de7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72764282833753134025517506766281266167929251639763382443939542632102643305015 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.72
764282833753134025517506766281266167929251639763382443939542632102643305015
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.24230590060401079035875179528979696691277361722296210683914656905964957700975
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.75 seconds
Started Oct 18 12:21:25 PM PDT 23
Finished Oct 18 12:21:28 PM PDT 23
Peak memory 162584 kb
Host smart-b47186c2-d833-4597-b2a4-d8146e1d5c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24230590060401079035875179528979696691277361722296210683914656905964957700975 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.24
230590060401079035875179528979696691277361722296210683914656905964957700975
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.50024391696636571932427847627331705612384293081078724534772783905783971320012
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.84 seconds
Started Oct 18 12:26:00 PM PDT 23
Finished Oct 18 12:26:04 PM PDT 23
Peak memory 161272 kb
Host smart-fcd36c2e-7bc0-4566-8c97-b13d4ea70970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50024391696636571932427847627331705612384293081078724534772783905783971320012 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.50
024391696636571932427847627331705612384293081078724534772783905783971320012
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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