Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.56028209361670600623209694672108556490255596715570895142307855414902525782265

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.773731203837099365029679329913386579910859276610525262818736937406997339033
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.48120191901600180886541362791369446263743055181023232856064787776149461077417
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.87710422747344244775608402375921638855152239279055964729179328760582460990753
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.53872342430721204389536476341894365833087359135155315848096671490633809091775
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.61967903515795556047746628900051660749568216842797321342812131939917253509649
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.9803310843611330210384690684517103729212904750308267038899509730128052486093
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.64011828948980590963947718151428334465210700483192688798148599668188791820338
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.532763723175297843809109240290923356101325254956879600788825170702185594695
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.2874640205141200735969126479491634819805535217390366820571807473543141376595



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.48120191901600180886541362791369446263743055181023232856064787776149461077417 Oct 22 12:21:32 PM PDT 23 Oct 22 12:21:35 PM PDT 23 9684159183 ps
T2 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.9803310843611330210384690684517103729212904750308267038899509730128052486093 Oct 22 12:21:02 PM PDT 23 Oct 22 12:21:05 PM PDT 23 9684159183 ps
T3 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.56028209361670600623209694672108556490255596715570895142307855414902525782265 Oct 22 12:25:18 PM PDT 23 Oct 22 12:25:23 PM PDT 23 9684159183 ps
T4 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.61967903515795556047746628900051660749568216842797321342812131939917253509649 Oct 22 12:20:48 PM PDT 23 Oct 22 12:20:51 PM PDT 23 9684159183 ps
T5 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.64011828948980590963947718151428334465210700483192688798148599668188791820338 Oct 22 12:25:18 PM PDT 23 Oct 22 12:25:23 PM PDT 23 9684159183 ps
T6 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.773731203837099365029679329913386579910859276610525262818736937406997339033 Oct 22 12:25:19 PM PDT 23 Oct 22 12:25:23 PM PDT 23 9684159183 ps
T7 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.87710422747344244775608402375921638855152239279055964729179328760582460990753 Oct 22 12:21:11 PM PDT 23 Oct 22 12:21:14 PM PDT 23 9684159183 ps
T8 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.53872342430721204389536476341894365833087359135155315848096671490633809091775 Oct 22 12:20:30 PM PDT 23 Oct 22 12:20:34 PM PDT 23 9684159183 ps
T9 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2874640205141200735969126479491634819805535217390366820571807473543141376595 Oct 22 12:27:38 PM PDT 23 Oct 22 12:27:41 PM PDT 23 9684159183 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.532763723175297843809109240290923356101325254956879600788825170702185594695 Oct 22 12:26:25 PM PDT 23 Oct 22 12:26:28 PM PDT 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.56028209361670600623209694672108556490255596715570895142307855414902525782265
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.75 seconds
Started Oct 22 12:25:18 PM PDT 23
Finished Oct 22 12:25:23 PM PDT 23
Peak memory 162144 kb
Host smart-3324caff-d6f7-444c-b60b-e96817ce06e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56028209361670600623209694672108556490255596715570895142307855414902525782265 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.56
028209361670600623209694672108556490255596715570895142307855414902525782265
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.773731203837099365029679329913386579910859276610525262818736937406997339033
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Oct 22 12:25:19 PM PDT 23
Finished Oct 22 12:25:23 PM PDT 23
Peak memory 162448 kb
Host smart-8e2c7383-bc18-4dbf-a078-b53c46b25057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773731203837099365029679329913386579910859276610525262818736937406997339033 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_
SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.7737
31203837099365029679329913386579910859276610525262818736937406997339033
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.48120191901600180886541362791369446263743055181023232856064787776149461077417
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.75 seconds
Started Oct 22 12:21:32 PM PDT 23
Finished Oct 22 12:21:35 PM PDT 23
Peak memory 162792 kb
Host smart-01f52989-e783-465c-b268-4089d0652b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48120191901600180886541362791369446263743055181023232856064787776149461077417 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.48
120191901600180886541362791369446263743055181023232856064787776149461077417
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.87710422747344244775608402375921638855152239279055964729179328760582460990753
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.88 seconds
Started Oct 22 12:21:11 PM PDT 23
Finished Oct 22 12:21:14 PM PDT 23
Peak memory 160564 kb
Host smart-b23fdda6-d8cf-43cc-a5a4-0ab7ed65227b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87710422747344244775608402375921638855152239279055964729179328760582460990753 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.87
710422747344244775608402375921638855152239279055964729179328760582460990753
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.53872342430721204389536476341894365833087359135155315848096671490633809091775
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.85 seconds
Started Oct 22 12:20:30 PM PDT 23
Finished Oct 22 12:20:34 PM PDT 23
Peak memory 162944 kb
Host smart-b2a603b8-0d21-48aa-b02c-17fd9c1ddf25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53872342430721204389536476341894365833087359135155315848096671490633809091775 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.53
872342430721204389536476341894365833087359135155315848096671490633809091775
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.61967903515795556047746628900051660749568216842797321342812131939917253509649
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.78 seconds
Started Oct 22 12:20:48 PM PDT 23
Finished Oct 22 12:20:51 PM PDT 23
Peak memory 162564 kb
Host smart-abf5a80e-dccb-4cca-9d72-e712dc454b07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61967903515795556047746628900051660749568216842797321342812131939917253509649 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.61
967903515795556047746628900051660749568216842797321342812131939917253509649
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.9803310843611330210384690684517103729212904750308267038899509730128052486093
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.8 seconds
Started Oct 22 12:21:02 PM PDT 23
Finished Oct 22 12:21:05 PM PDT 23
Peak memory 162508 kb
Host smart-9b52859f-d809-4d8c-b60c-a3b7baec74af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9803310843611330210384690684517103729212904750308267038899509730128052486093 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.980
3310843611330210384690684517103729212904750308267038899509730128052486093
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.64011828948980590963947718151428334465210700483192688798148599668188791820338
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.81 seconds
Started Oct 22 12:25:18 PM PDT 23
Finished Oct 22 12:25:23 PM PDT 23
Peak memory 160964 kb
Host smart-e79412d8-2b73-444a-9e71-87acc1ed70d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64011828948980590963947718151428334465210700483192688798148599668188791820338 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.64
011828948980590963947718151428334465210700483192688798148599668188791820338
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.532763723175297843809109240290923356101325254956879600788825170702185594695
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.72 seconds
Started Oct 22 12:26:25 PM PDT 23
Finished Oct 22 12:26:28 PM PDT 23
Peak memory 162484 kb
Host smart-99ce7980-da0c-4919-9d6d-aade67adb526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532763723175297843809109240290923356101325254956879600788825170702185594695 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_
SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.5327
63723175297843809109240290923356101325254956879600788825170702185594695
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2874640205141200735969126479491634819805535217390366820571807473543141376595
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Oct 22 12:27:38 PM PDT 23
Finished Oct 22 12:27:41 PM PDT 23
Peak memory 162556 kb
Host smart-69a3e505-bb59-4c98-9c97-6eeada4353fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874640205141200735969126479491634819805535217390366820571807473543141376595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.287
4640205141200735969126479491634819805535217390366820571807473543141376595
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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