Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.75776638986822791037948510106488249003142346615111755472954088535248598006010

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.48641084856164023578639163235807290500918300741342196208676726934270043936363
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.48711735324453486386641762059376937952258902994982293630297794594655976159183
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.93989074264877815437021815195694431985075764947539131960940305024989537490044
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.94918807860411977215785947386004268225537960704611737594230343499565186625255
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.112671388518932952809749091482246765386506831554089145068967334058434189211958
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.88322375568282147310707806946946567495437786753300996206577481080248207555554
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.72077043535239235938494711445496961755244590030109604867521477258535828984836
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.81658448637722686321839389086549501828909120312479168818598905871397222775232
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.56197186315248434686366898381665368203872867863924805811453049382164127564906



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.48711735324453486386641762059376937952258902994982293630297794594655976159183 Oct 25 01:15:40 PM PDT 23 Oct 25 01:15:43 PM PDT 23 9684159183 ps
T2 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.94918807860411977215785947386004268225537960704611737594230343499565186625255 Oct 25 01:15:55 PM PDT 23 Oct 25 01:15:59 PM PDT 23 9684159183 ps
T3 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.72077043535239235938494711445496961755244590030109604867521477258535828984836 Oct 25 01:15:41 PM PDT 23 Oct 25 01:15:44 PM PDT 23 9684159183 ps
T4 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.93989074264877815437021815195694431985075764947539131960940305024989537490044 Oct 25 01:15:54 PM PDT 23 Oct 25 01:15:57 PM PDT 23 9684159183 ps
T5 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.56197186315248434686366898381665368203872867863924805811453049382164127564906 Oct 25 01:15:53 PM PDT 23 Oct 25 01:15:56 PM PDT 23 9684159183 ps
T6 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.75776638986822791037948510106488249003142346615111755472954088535248598006010 Oct 25 01:15:50 PM PDT 23 Oct 25 01:15:54 PM PDT 23 9684159183 ps
T7 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.48641084856164023578639163235807290500918300741342196208676726934270043936363 Oct 25 01:15:47 PM PDT 23 Oct 25 01:15:50 PM PDT 23 9684159183 ps
T8 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.88322375568282147310707806946946567495437786753300996206577481080248207555554 Oct 25 01:15:41 PM PDT 23 Oct 25 01:15:44 PM PDT 23 9684159183 ps
T9 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.112671388518932952809749091482246765386506831554089145068967334058434189211958 Oct 25 01:15:52 PM PDT 23 Oct 25 01:15:55 PM PDT 23 9684159183 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.81658448637722686321839389086549501828909120312479168818598905871397222775232 Oct 25 01:15:51 PM PDT 23 Oct 25 01:15:55 PM PDT 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.75776638986822791037948510106488249003142346615111755472954088535248598006010
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 25 01:15:50 PM PDT 23
Finished Oct 25 01:15:54 PM PDT 23
Peak memory 162748 kb
Host smart-649e3001-8780-4797-a38f-4a379761863c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75776638986822791037948510106488249003142346615111755472954088535248598006010 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.75
776638986822791037948510106488249003142346615111755472954088535248598006010
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.48641084856164023578639163235807290500918300741342196208676726934270043936363
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 25 01:15:47 PM PDT 23
Finished Oct 25 01:15:50 PM PDT 23
Peak memory 162732 kb
Host smart-13675509-3409-45da-acfe-7e79aad4b16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48641084856164023578639163235807290500918300741342196208676726934270043936363 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.48
641084856164023578639163235807290500918300741342196208676726934270043936363
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.48711735324453486386641762059376937952258902994982293630297794594655976159183
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.75 seconds
Started Oct 25 01:15:40 PM PDT 23
Finished Oct 25 01:15:43 PM PDT 23
Peak memory 162632 kb
Host smart-a49ee872-272e-4153-8775-50f06e851266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48711735324453486386641762059376937952258902994982293630297794594655976159183 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.48
711735324453486386641762059376937952258902994982293630297794594655976159183
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.93989074264877815437021815195694431985075764947539131960940305024989537490044
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.76 seconds
Started Oct 25 01:15:54 PM PDT 23
Finished Oct 25 01:15:57 PM PDT 23
Peak memory 162632 kb
Host smart-d0294b94-3ff5-409e-bdd6-e0eaf80ae5f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93989074264877815437021815195694431985075764947539131960940305024989537490044 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.93
989074264877815437021815195694431985075764947539131960940305024989537490044
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.94918807860411977215785947386004268225537960704611737594230343499565186625255
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.72 seconds
Started Oct 25 01:15:55 PM PDT 23
Finished Oct 25 01:15:59 PM PDT 23
Peak memory 162780 kb
Host smart-203e1459-6946-420e-b066-5de1dce7aa18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94918807860411977215785947386004268225537960704611737594230343499565186625255 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.94
918807860411977215785947386004268225537960704611737594230343499565186625255
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.112671388518932952809749091482246765386506831554089145068967334058434189211958
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.77 seconds
Started Oct 25 01:15:52 PM PDT 23
Finished Oct 25 01:15:55 PM PDT 23
Peak memory 162764 kb
Host smart-cb5a0676-6b90-4641-a312-21f2fb8dc1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112671388518932952809749091482246765386506831554089145068967334058434189211958 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1
12671388518932952809749091482246765386506831554089145068967334058434189211958
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.88322375568282147310707806946946567495437786753300996206577481080248207555554
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.85 seconds
Started Oct 25 01:15:41 PM PDT 23
Finished Oct 25 01:15:44 PM PDT 23
Peak memory 162640 kb
Host smart-618a300b-5e3f-4daa-b15e-33d39abeebef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88322375568282147310707806946946567495437786753300996206577481080248207555554 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.88
322375568282147310707806946946567495437786753300996206577481080248207555554
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.72077043535239235938494711445496961755244590030109604867521477258535828984836
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.75 seconds
Started Oct 25 01:15:41 PM PDT 23
Finished Oct 25 01:15:44 PM PDT 23
Peak memory 162780 kb
Host smart-6925cc75-e551-4e8d-8db3-bba248e7a595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72077043535239235938494711445496961755244590030109604867521477258535828984836 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.72
077043535239235938494711445496961755244590030109604867521477258535828984836
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.81658448637722686321839389086549501828909120312479168818598905871397222775232
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.78 seconds
Started Oct 25 01:15:51 PM PDT 23
Finished Oct 25 01:15:55 PM PDT 23
Peak memory 162764 kb
Host smart-cd22e076-5988-40ed-98bf-c3e1749184e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81658448637722686321839389086549501828909120312479168818598905871397222775232 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.81
658448637722686321839389086549501828909120312479168818598905871397222775232
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.56197186315248434686366898381665368203872867863924805811453049382164127564906
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.74 seconds
Started Oct 25 01:15:53 PM PDT 23
Finished Oct 25 01:15:56 PM PDT 23
Peak memory 162632 kb
Host smart-e6e89d5f-c505-4e1e-b3f0-741c9fedd02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56197186315248434686366898381665368203872867863924805811453049382164127564906 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.56
197186315248434686366898381665368203872867863924805811453049382164127564906
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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