Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1986206321283152183077975696866325115365441979654336067635088304841164984062

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.8107783972483133916673902600755287243971628361208219357376454902551166942613
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.115783405023641684093123171628416904874444727501075483748871077561906447125306
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.53639236819659079141137290021103109897076902176914621366760393017793194028483
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.84422734194740597068493533638620014841641446948795594930710889668499622205327
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.1347774455684403269674518353303433732978338862834809133691633975999459950652
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.84857101154152494954518517537083531780158081033837942131574403011836145451813
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.25472672232683782110675649859631335040699692786906654786270459890346201086073
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.67687741073206355303599635778306401405992917753217084075707824695529408456331
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.97434844006373614835880634107366453808444328247031937168836169322530212239285



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.84857101154152494954518517537083531780158081033837942131574403011836145451813 Oct 29 12:50:40 PM PDT 23 Oct 29 12:50:43 PM PDT 23 9684159183 ps
T2 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.67687741073206355303599635778306401405992917753217084075707824695529408456331 Oct 29 12:50:21 PM PDT 23 Oct 29 12:50:24 PM PDT 23 9684159183 ps
T3 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.115783405023641684093123171628416904874444727501075483748871077561906447125306 Oct 29 12:49:53 PM PDT 23 Oct 29 12:49:56 PM PDT 23 9684159183 ps
T4 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1347774455684403269674518353303433732978338862834809133691633975999459950652 Oct 29 12:50:03 PM PDT 23 Oct 29 12:50:07 PM PDT 23 9684159183 ps
T5 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.97434844006373614835880634107366453808444328247031937168836169322530212239285 Oct 29 12:50:27 PM PDT 23 Oct 29 12:50:30 PM PDT 23 9684159183 ps
T6 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.8107783972483133916673902600755287243971628361208219357376454902551166942613 Oct 29 12:49:54 PM PDT 23 Oct 29 12:49:58 PM PDT 23 9684159183 ps
T7 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.84422734194740597068493533638620014841641446948795594930710889668499622205327 Oct 29 12:50:04 PM PDT 23 Oct 29 12:50:07 PM PDT 23 9684159183 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.53639236819659079141137290021103109897076902176914621366760393017793194028483 Oct 29 12:50:04 PM PDT 23 Oct 29 12:50:08 PM PDT 23 9684159183 ps
T9 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.25472672232683782110675649859631335040699692786906654786270459890346201086073 Oct 29 12:50:26 PM PDT 23 Oct 29 12:50:29 PM PDT 23 9684159183 ps
T10 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1986206321283152183077975696866325115365441979654336067635088304841164984062 Oct 29 12:49:52 PM PDT 23 Oct 29 12:49:55 PM PDT 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1986206321283152183077975696866325115365441979654336067635088304841164984062
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.68 seconds
Started Oct 29 12:49:52 PM PDT 23
Finished Oct 29 12:49:55 PM PDT 23
Peak memory 162604 kb
Host smart-dcfcf916-e31c-461b-aeae-3c00e0ee8e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986206321283152183077975696866325115365441979654336067635088304841164984062 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.198
6206321283152183077975696866325115365441979654336067635088304841164984062
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.8107783972483133916673902600755287243971628361208219357376454902551166942613
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 29 12:49:54 PM PDT 23
Finished Oct 29 12:49:58 PM PDT 23
Peak memory 162704 kb
Host smart-b07436a2-6ab7-4791-90d3-43318e284509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8107783972483133916673902600755287243971628361208219357376454902551166942613 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.810
7783972483133916673902600755287243971628361208219357376454902551166942613
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.115783405023641684093123171628416904874444727501075483748871077561906447125306
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 29 12:49:53 PM PDT 23
Finished Oct 29 12:49:56 PM PDT 23
Peak memory 162520 kb
Host smart-b8bca766-497f-4874-aea1-8dfbb1ad44e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115783405023641684093123171628416904874444727501075483748871077561906447125306 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1
15783405023641684093123171628416904874444727501075483748871077561906447125306
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.53639236819659079141137290021103109897076902176914621366760393017793194028483
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.77 seconds
Started Oct 29 12:50:04 PM PDT 23
Finished Oct 29 12:50:08 PM PDT 23
Peak memory 162520 kb
Host smart-62000b32-607d-4f12-ab89-175c8a01b3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53639236819659079141137290021103109897076902176914621366760393017793194028483 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.53
639236819659079141137290021103109897076902176914621366760393017793194028483
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.84422734194740597068493533638620014841641446948795594930710889668499622205327
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.73 seconds
Started Oct 29 12:50:04 PM PDT 23
Finished Oct 29 12:50:07 PM PDT 23
Peak memory 162552 kb
Host smart-7ae27b45-c386-4be1-b54f-b4e3612d6176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84422734194740597068493533638620014841641446948795594930710889668499622205327 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.84
422734194740597068493533638620014841641446948795594930710889668499622205327
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1347774455684403269674518353303433732978338862834809133691633975999459950652
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.76 seconds
Started Oct 29 12:50:03 PM PDT 23
Finished Oct 29 12:50:07 PM PDT 23
Peak memory 162592 kb
Host smart-a894cf53-a345-4911-9e2d-3e910554ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347774455684403269674518353303433732978338862834809133691633975999459950652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.134
7774455684403269674518353303433732978338862834809133691633975999459950652
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.84857101154152494954518517537083531780158081033837942131574403011836145451813
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.77 seconds
Started Oct 29 12:50:40 PM PDT 23
Finished Oct 29 12:50:43 PM PDT 23
Peak memory 162540 kb
Host smart-2fecce96-7f6d-42b5-a79d-bd33e6c34931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84857101154152494954518517537083531780158081033837942131574403011836145451813 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.84
857101154152494954518517537083531780158081033837942131574403011836145451813
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.25472672232683782110675649859631335040699692786906654786270459890346201086073
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Oct 29 12:50:26 PM PDT 23
Finished Oct 29 12:50:29 PM PDT 23
Peak memory 162576 kb
Host smart-9cb83a2e-07bb-47e6-b312-422371e792da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25472672232683782110675649859631335040699692786906654786270459890346201086073 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.25
472672232683782110675649859631335040699692786906654786270459890346201086073
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.67687741073206355303599635778306401405992917753217084075707824695529408456331
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.76 seconds
Started Oct 29 12:50:21 PM PDT 23
Finished Oct 29 12:50:24 PM PDT 23
Peak memory 162592 kb
Host smart-e2b7f72e-352f-4aa5-86d0-b41471d5495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67687741073206355303599635778306401405992917753217084075707824695529408456331 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.67
687741073206355303599635778306401405992917753217084075707824695529408456331
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.97434844006373614835880634107366453808444328247031937168836169322530212239285
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.72 seconds
Started Oct 29 12:50:27 PM PDT 23
Finished Oct 29 12:50:30 PM PDT 23
Peak memory 162564 kb
Host smart-cfff9eb4-d983-47bf-9ef2-aec3eacc1931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97434844006373614835880634107366453808444328247031937168836169322530212239285 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.97
434844006373614835880634107366453808444328247031937168836169322530212239285
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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