Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.80861758113526394530123997755414815509014991523770378033889856133220079749859

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.62974367672988355446747763410374241692425674115083864207004751642457150141122
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.112523624482793191608581424839475822833639544781608551167899469501890880835257
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.48161460334659597987525671200174073834519462625658409716920074652992133439816
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.69820846589330860660021799786775784036169673439513479883461686667409973090825
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.67558964208737591213433127344053505432954936919021317834745681486312949706766
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.53464679204713862915189674712116543574395140813907714100556196559749585525617
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.29675030473348019210942735869108324103515088529803791692083611995922924338891
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.50302388323185372018569716465076383815972669325287204290029709683336875680808
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.92804107661751083687099555803315331729440100173980367777932355299384922947886



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.48161460334659597987525671200174073834519462625658409716920074652992133439816 Nov 01 01:55:11 PM PDT 23 Nov 01 01:55:31 PM PDT 23 9684159183 ps
T2 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.29675030473348019210942735869108324103515088529803791692083611995922924338891 Nov 01 01:55:09 PM PDT 23 Nov 01 01:55:26 PM PDT 23 9684159183 ps
T3 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.62974367672988355446747763410374241692425674115083864207004751642457150141122 Nov 01 01:55:07 PM PDT 23 Nov 01 01:55:25 PM PDT 23 9684159183 ps
T4 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.69820846589330860660021799786775784036169673439513479883461686667409973090825 Nov 01 01:55:10 PM PDT 23 Nov 01 01:55:26 PM PDT 23 9684159183 ps
T5 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.67558964208737591213433127344053505432954936919021317834745681486312949706766 Nov 01 01:55:08 PM PDT 23 Nov 01 01:55:25 PM PDT 23 9684159183 ps
T6 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.112523624482793191608581424839475822833639544781608551167899469501890880835257 Nov 01 01:55:08 PM PDT 23 Nov 01 01:55:25 PM PDT 23 9684159183 ps
T7 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.53464679204713862915189674712116543574395140813907714100556196559749585525617 Nov 01 01:55:09 PM PDT 23 Nov 01 01:55:26 PM PDT 23 9684159183 ps
T8 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.80861758113526394530123997755414815509014991523770378033889856133220079749859 Nov 01 01:55:06 PM PDT 23 Nov 01 01:55:24 PM PDT 23 9684159183 ps
T9 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.92804107661751083687099555803315331729440100173980367777932355299384922947886 Nov 01 01:55:10 PM PDT 23 Nov 01 01:55:26 PM PDT 23 9684159183 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.50302388323185372018569716465076383815972669325287204290029709683336875680808 Nov 01 01:55:07 PM PDT 23 Nov 01 01:55:26 PM PDT 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.80861758113526394530123997755414815509014991523770378033889856133220079749859
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Nov 01 01:55:06 PM PDT 23
Finished Nov 01 01:55:24 PM PDT 23
Peak memory 162792 kb
Host smart-984090f6-4fdc-4287-a853-d5a47a3c7325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80861758113526394530123997755414815509014991523770378033889856133220079749859 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.80
861758113526394530123997755414815509014991523770378033889856133220079749859
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.62974367672988355446747763410374241692425674115083864207004751642457150141122
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Nov 01 01:55:07 PM PDT 23
Finished Nov 01 01:55:25 PM PDT 23
Peak memory 162792 kb
Host smart-eba1e2a5-3799-45c0-8632-8c9e55751707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62974367672988355446747763410374241692425674115083864207004751642457150141122 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.62
974367672988355446747763410374241692425674115083864207004751642457150141122
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.112523624482793191608581424839475822833639544781608551167899469501890880835257
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.7 seconds
Started Nov 01 01:55:08 PM PDT 23
Finished Nov 01 01:55:25 PM PDT 23
Peak memory 162764 kb
Host smart-cfc433c7-ce75-4362-b59c-0d8a0d36cf22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112523624482793191608581424839475822833639544781608551167899469501890880835257 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1
12523624482793191608581424839475822833639544781608551167899469501890880835257
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.48161460334659597987525671200174073834519462625658409716920074652992133439816
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Nov 01 01:55:11 PM PDT 23
Finished Nov 01 01:55:31 PM PDT 23
Peak memory 162780 kb
Host smart-5597578c-e136-4efc-9503-d8ee59239113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48161460334659597987525671200174073834519462625658409716920074652992133439816 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.48
161460334659597987525671200174073834519462625658409716920074652992133439816
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.69820846589330860660021799786775784036169673439513479883461686667409973090825
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.69 seconds
Started Nov 01 01:55:10 PM PDT 23
Finished Nov 01 01:55:26 PM PDT 23
Peak memory 162768 kb
Host smart-4cfce64d-abcb-4c60-97f4-4973835485e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69820846589330860660021799786775784036169673439513479883461686667409973090825 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.69
820846589330860660021799786775784036169673439513479883461686667409973090825
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.67558964208737591213433127344053505432954936919021317834745681486312949706766
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.7 seconds
Started Nov 01 01:55:08 PM PDT 23
Finished Nov 01 01:55:25 PM PDT 23
Peak memory 162764 kb
Host smart-c8174ddb-ab74-4e9a-9b34-b47686fc6093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67558964208737591213433127344053505432954936919021317834745681486312949706766 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.67
558964208737591213433127344053505432954936919021317834745681486312949706766
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.53464679204713862915189674712116543574395140813907714100556196559749585525617
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.7 seconds
Started Nov 01 01:55:09 PM PDT 23
Finished Nov 01 01:55:26 PM PDT 23
Peak memory 162768 kb
Host smart-c8170265-667f-4b31-86f3-6166e7d9437f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53464679204713862915189674712116543574395140813907714100556196559749585525617 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.53
464679204713862915189674712116543574395140813907714100556196559749585525617
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.29675030473348019210942735869108324103515088529803791692083611995922924338891
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.7 seconds
Started Nov 01 01:55:09 PM PDT 23
Finished Nov 01 01:55:26 PM PDT 23
Peak memory 162820 kb
Host smart-db424983-e129-4a3e-b590-80cb86563735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29675030473348019210942735869108324103515088529803791692083611995922924338891 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.29
675030473348019210942735869108324103515088529803791692083611995922924338891
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.50302388323185372018569716465076383815972669325287204290029709683336875680808
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.68 seconds
Started Nov 01 01:55:07 PM PDT 23
Finished Nov 01 01:55:26 PM PDT 23
Peak memory 162792 kb
Host smart-75128992-d695-4589-b3f0-d261e9d30808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50302388323185372018569716465076383815972669325287204290029709683336875680808 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.50
302388323185372018569716465076383815972669325287204290029709683336875680808
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.92804107661751083687099555803315331729440100173980367777932355299384922947886
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.66 seconds
Started Nov 01 01:55:10 PM PDT 23
Finished Nov 01 01:55:26 PM PDT 23
Peak memory 162768 kb
Host smart-931e8bd0-d67b-4a0d-b2bd-4145c5b085b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92804107661751083687099555803315331729440100173980367777932355299384922947886 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.92
804107661751083687099555803315331729440100173980367777932355299384922947886
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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