Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.18296167148833726662917913071803004911920652946484223917507884023597153273895

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.87254383451209409820576495396321116095967810149597054689192970282462579049062
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.77822889851177997834794278298802127334364560237835383522066056637265083110145
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.108887273931863224170897910918617299545293224472613424322973520358058539972238
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.11341208602981727431321389401100263326994599540184066102900189981133068777507
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.13790741638127570270675817599382837549970206460154820865797491756570820653608
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.92741995620878763650098728020818871350605425678516027591149448458183464024686
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.114535936402039702508802823035176509270340901596267000845362340182547600616543
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.2699763418358687757522728285169127060714454435817378050273855844765855936206
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.35075073508035324058477891758128547510269121051886751128737352388144677874267



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.18296167148833726662917913071803004911920652946484223917507884023597153273895 Nov 22 12:39:20 PM PST 23 Nov 22 12:39:26 PM PST 23 9684159183 ps
T2 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2699763418358687757522728285169127060714454435817378050273855844765855936206 Nov 22 12:39:24 PM PST 23 Nov 22 12:39:29 PM PST 23 9684159183 ps
T3 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.77822889851177997834794278298802127334364560237835383522066056637265083110145 Nov 22 12:39:29 PM PST 23 Nov 22 12:39:35 PM PST 23 9684159183 ps
T4 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.13790741638127570270675817599382837549970206460154820865797491756570820653608 Nov 22 12:39:28 PM PST 23 Nov 22 12:39:32 PM PST 23 9684159183 ps
T5 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.108887273931863224170897910918617299545293224472613424322973520358058539972238 Nov 22 12:39:32 PM PST 23 Nov 22 12:39:38 PM PST 23 9684159183 ps
T6 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.87254383451209409820576495396321116095967810149597054689192970282462579049062 Nov 22 12:39:29 PM PST 23 Nov 22 12:39:34 PM PST 23 9684159183 ps
T7 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.11341208602981727431321389401100263326994599540184066102900189981133068777507 Nov 22 12:39:17 PM PST 23 Nov 22 12:39:23 PM PST 23 9684159183 ps
T8 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.92741995620878763650098728020818871350605425678516027591149448458183464024686 Nov 22 12:39:25 PM PST 23 Nov 22 12:39:30 PM PST 23 9684159183 ps
T9 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.114535936402039702508802823035176509270340901596267000845362340182547600616543 Nov 22 12:39:17 PM PST 23 Nov 22 12:39:23 PM PST 23 9684159183 ps
T10 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.35075073508035324058477891758128547510269121051886751128737352388144677874267 Nov 22 12:39:16 PM PST 23 Nov 22 12:39:23 PM PST 23 9684159183 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.18296167148833726662917913071803004911920652946484223917507884023597153273895
Short name T1
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.78 seconds
Started Nov 22 12:39:20 PM PST 23
Finished Nov 22 12:39:26 PM PST 23
Peak memory 162728 kb
Host smart-05a18e2b-6441-452e-b646-d305aa6ab8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18296167148833726662917913071803004911920652946484223917507884023597153273895 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.18
296167148833726662917913071803004911920652946484223917507884023597153273895
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.87254383451209409820576495396321116095967810149597054689192970282462579049062
Short name T6
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.7 seconds
Started Nov 22 12:39:29 PM PST 23
Finished Nov 22 12:39:34 PM PST 23
Peak memory 162556 kb
Host smart-c1fe5013-8a8c-4d6b-a2a0-cdf33807e479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87254383451209409820576495396321116095967810149597054689192970282462579049062 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.87
254383451209409820576495396321116095967810149597054689192970282462579049062
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.77822889851177997834794278298802127334364560237835383522066056637265083110145
Short name T3
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.8 seconds
Started Nov 22 12:39:29 PM PST 23
Finished Nov 22 12:39:35 PM PST 23
Peak memory 162692 kb
Host smart-31b5dc50-8d41-4faf-abc8-58e65aaaa9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77822889851177997834794278298802127334364560237835383522066056637265083110145 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.77
822889851177997834794278298802127334364560237835383522066056637265083110145
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.108887273931863224170897910918617299545293224472613424322973520358058539972238
Short name T5
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.8 seconds
Started Nov 22 12:39:32 PM PST 23
Finished Nov 22 12:39:38 PM PST 23
Peak memory 162660 kb
Host smart-602ce9c7-e7ca-4ec5-a898-316c894cca76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108887273931863224170897910918617299545293224472613424322973520358058539972238 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1
08887273931863224170897910918617299545293224472613424322973520358058539972238
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.11341208602981727431321389401100263326994599540184066102900189981133068777507
Short name T7
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Nov 22 12:39:17 PM PST 23
Finished Nov 22 12:39:23 PM PST 23
Peak memory 162732 kb
Host smart-53e96db3-ce95-401c-978f-0873f6c3d0a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11341208602981727431321389401100263326994599540184066102900189981133068777507 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.11
341208602981727431321389401100263326994599540184066102900189981133068777507
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.13790741638127570270675817599382837549970206460154820865797491756570820653608
Short name T4
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Nov 22 12:39:28 PM PST 23
Finished Nov 22 12:39:32 PM PST 23
Peak memory 162668 kb
Host smart-caa40fa6-9802-4237-9443-5b89826c4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13790741638127570270675817599382837549970206460154820865797491756570820653608 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.13
790741638127570270675817599382837549970206460154820865797491756570820653608
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.92741995620878763650098728020818871350605425678516027591149448458183464024686
Short name T8
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.74 seconds
Started Nov 22 12:39:25 PM PST 23
Finished Nov 22 12:39:30 PM PST 23
Peak memory 162552 kb
Host smart-cbdae172-0b1b-4496-a0df-1f9d43c372d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92741995620878763650098728020818871350605425678516027591149448458183464024686 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.92
741995620878763650098728020818871350605425678516027591149448458183464024686
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.114535936402039702508802823035176509270340901596267000845362340182547600616543
Short name T9
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.74 seconds
Started Nov 22 12:39:17 PM PST 23
Finished Nov 22 12:39:23 PM PST 23
Peak memory 162588 kb
Host smart-1035de91-6168-49e2-b82e-edc858d24605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114535936402039702508802823035176509270340901596267000845362340182547600616543 -assert nopostproc +UVM_TESTNAME= +UVM_TE
ST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.1
14535936402039702508802823035176509270340901596267000845362340182547600616543
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2699763418358687757522728285169127060714454435817378050273855844765855936206
Short name T2
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.71 seconds
Started Nov 22 12:39:24 PM PST 23
Finished Nov 22 12:39:29 PM PST 23
Peak memory 162612 kb
Host smart-ce6dfc22-73f4-4fea-902d-a6575fea2548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699763418358687757522728285169127060714454435817378050273855844765855936206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST
_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.269
9763418358687757522728285169127060714454435817378050273855844765855936206
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.35075073508035324058477891758128547510269121051886751128737352388144677874267
Short name T10
Test name
Test status
Simulation time 9684159183 ps
CPU time 2.72 seconds
Started Nov 22 12:39:16 PM PST 23
Finished Nov 22 12:39:23 PM PST 23
Peak memory 162608 kb
Host smart-97b29056-d059-4ee3-94d0-7bea452ff7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35075073508035324058477891758128547510269121051886751128737352388144677874267 -assert nopostproc +UVM_TESTNAME= +UVM_TES
T_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.35
075073508035324058477891758128547510269121051886751128737352388144677874267
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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