Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1597351272

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.1601004462
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.3362100659
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.2224134844
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1548671760
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.2845756084
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1934151812
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.3926299366
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.2850305455
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.939384584



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1934151812 Dec 20 12:19:00 PM PST 23 Dec 20 12:19:06 PM PST 23 9290622121 ps
T2 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3362100659 Dec 20 12:18:48 PM PST 23 Dec 20 12:18:56 PM PST 23 9271476370 ps
T3 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1597351272 Dec 20 12:18:51 PM PST 23 Dec 20 12:19:00 PM PST 23 9271510024 ps
T4 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3926299366 Dec 20 12:18:50 PM PST 23 Dec 20 12:18:58 PM PST 23 10114217726 ps
T5 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2845756084 Dec 20 12:18:49 PM PST 23 Dec 20 12:18:58 PM PST 23 10237401443 ps
T6 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2224134844 Dec 20 12:18:53 PM PST 23 Dec 20 12:19:02 PM PST 23 8725720508 ps
T7 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1548671760 Dec 20 12:18:49 PM PST 23 Dec 20 12:18:58 PM PST 23 9429353442 ps
T8 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2850305455 Dec 20 12:18:54 PM PST 23 Dec 20 12:19:04 PM PST 23 9812294071 ps
T9 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.939384584 Dec 20 12:18:51 PM PST 23 Dec 20 12:19:01 PM PST 23 10932401135 ps
T10 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.1601004462 Dec 20 12:18:52 PM PST 23 Dec 20 12:19:01 PM PST 23 9271511224 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1597351272
Short name T3
Test name
Test status
Simulation time 9271510024 ps
CPU time 2.72 seconds
Started Dec 20 12:18:51 PM PST 23
Finished Dec 20 12:19:00 PM PST 23
Peak memory 162752 kb
Host smart-7bbb52ca-19e2-4b88-9e7f-77fcc6b443e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597351272 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1597351272
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.1601004462
Short name T10
Test name
Test status
Simulation time 9271511224 ps
CPU time 2.7 seconds
Started Dec 20 12:18:52 PM PST 23
Finished Dec 20 12:19:01 PM PST 23
Peak memory 162740 kb
Host smart-9116d46e-d3b5-4cb4-854a-6ddc931b73ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601004462 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.1601004462
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3362100659
Short name T2
Test name
Test status
Simulation time 9271476370 ps
CPU time 2.64 seconds
Started Dec 20 12:18:48 PM PST 23
Finished Dec 20 12:18:56 PM PST 23
Peak memory 162732 kb
Host smart-0cf80624-69a3-484c-8126-13086febdeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362100659 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.3362100659
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2224134844
Short name T6
Test name
Test status
Simulation time 8725720508 ps
CPU time 2.54 seconds
Started Dec 20 12:18:53 PM PST 23
Finished Dec 20 12:19:02 PM PST 23
Peak memory 162736 kb
Host smart-e75e1563-07b5-41ab-8bfc-8f643775d2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224134844 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.2224134844
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1548671760
Short name T7
Test name
Test status
Simulation time 9429353442 ps
CPU time 2.68 seconds
Started Dec 20 12:18:49 PM PST 23
Finished Dec 20 12:18:58 PM PST 23
Peak memory 162608 kb
Host smart-a0f05dd3-79f3-45a2-997e-14a71a52ae10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548671760 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1548671760
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.2845756084
Short name T5
Test name
Test status
Simulation time 10237401443 ps
CPU time 2.79 seconds
Started Dec 20 12:18:49 PM PST 23
Finished Dec 20 12:18:58 PM PST 23
Peak memory 162608 kb
Host smart-13740669-1658-4ccc-9618-35ec000c0661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2845756084 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.2845756084
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1934151812
Short name T1
Test name
Test status
Simulation time 9290622121 ps
CPU time 2.67 seconds
Started Dec 20 12:19:00 PM PST 23
Finished Dec 20 12:19:06 PM PST 23
Peak memory 162732 kb
Host smart-8e254f1e-4955-48e9-a501-87cd1e1c259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934151812 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1934151812
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3926299366
Short name T4
Test name
Test status
Simulation time 10114217726 ps
CPU time 2.76 seconds
Started Dec 20 12:18:50 PM PST 23
Finished Dec 20 12:18:58 PM PST 23
Peak memory 162608 kb
Host smart-613ab8b2-22de-4465-9b99-790f0a27ce2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926299366 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.3926299366
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2850305455
Short name T8
Test name
Test status
Simulation time 9812294071 ps
CPU time 2.73 seconds
Started Dec 20 12:18:54 PM PST 23
Finished Dec 20 12:19:04 PM PST 23
Peak memory 162732 kb
Host smart-dd2a13a2-ecd8-4b0d-83ed-40d794b5583e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850305455 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.2850305455
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.939384584
Short name T9
Test name
Test status
Simulation time 10932401135 ps
CPU time 2.91 seconds
Started Dec 20 12:18:51 PM PST 23
Finished Dec 20 12:19:01 PM PST 23
Peak memory 162756 kb
Host smart-b21d9994-837e-41b9-92a9-ac46dcdc509b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939384584 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.939384584
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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