Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1168118528

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.3645711889
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.2283863440
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.525850225
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2578487411
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.3095753794
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1262190742
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.2358294203
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.3896868686
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.1101492624



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1168118528 Dec 24 12:25:50 PM PST 23 Dec 24 12:25:54 PM PST 23 8938437274 ps
T2 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.1101492624 Dec 24 12:27:09 PM PST 23 Dec 24 12:27:15 PM PST 23 10114065793 ps
T3 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2358294203 Dec 24 12:26:26 PM PST 23 Dec 24 12:26:31 PM PST 23 10769837035 ps
T4 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1262190742 Dec 24 12:27:29 PM PST 23 Dec 24 12:27:34 PM PST 23 8976953994 ps
T5 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3095753794 Dec 24 12:27:47 PM PST 23 Dec 24 12:28:00 PM PST 23 9156474867 ps
T6 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2283863440 Dec 24 12:27:21 PM PST 23 Dec 24 12:27:27 PM PST 23 9271463947 ps
T7 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3645711889 Dec 24 12:27:53 PM PST 23 Dec 24 12:28:02 PM PST 23 10237531289 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.525850225 Dec 24 12:28:10 PM PST 23 Dec 24 12:28:28 PM PST 23 11338024533 ps
T9 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2578487411 Dec 24 12:28:49 PM PST 23 Dec 24 12:29:02 PM PST 23 8894383393 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3896868686 Dec 24 12:25:53 PM PST 23 Dec 24 12:25:57 PM PST 23 11203344735 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1168118528
Short name T1
Test name
Test status
Simulation time 8938437274 ps
CPU time 2.7 seconds
Started Dec 24 12:25:50 PM PST 23
Finished Dec 24 12:25:54 PM PST 23
Peak memory 162680 kb
Host smart-c6148925-38ee-4da6-a6ae-5b730b8bab8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168118528 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1168118528
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3645711889
Short name T7
Test name
Test status
Simulation time 10237531289 ps
CPU time 2.87 seconds
Started Dec 24 12:27:53 PM PST 23
Finished Dec 24 12:28:02 PM PST 23
Peak memory 162436 kb
Host smart-841759ca-0879-4153-b547-8ac30a7c8ac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645711889 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.3645711889
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2283863440
Short name T6
Test name
Test status
Simulation time 9271463947 ps
CPU time 2.71 seconds
Started Dec 24 12:27:21 PM PST 23
Finished Dec 24 12:27:27 PM PST 23
Peak memory 162520 kb
Host smart-57bd63c4-b2ab-4887-af6b-598f547d31a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283863440 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.2283863440
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.525850225
Short name T8
Test name
Test status
Simulation time 11338024533 ps
CPU time 3.05 seconds
Started Dec 24 12:28:10 PM PST 23
Finished Dec 24 12:28:28 PM PST 23
Peak memory 162588 kb
Host smart-02cd9119-5c12-4fab-a98b-945e6bab714f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525850225 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.525850225
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2578487411
Short name T9
Test name
Test status
Simulation time 8894383393 ps
CPU time 2.68 seconds
Started Dec 24 12:28:49 PM PST 23
Finished Dec 24 12:29:02 PM PST 23
Peak memory 161520 kb
Host smart-66d0f31a-51ed-4ccb-a937-43269e2667ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578487411 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2578487411
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3095753794
Short name T5
Test name
Test status
Simulation time 9156474867 ps
CPU time 2.79 seconds
Started Dec 24 12:27:47 PM PST 23
Finished Dec 24 12:28:00 PM PST 23
Peak memory 162480 kb
Host smart-1db20841-b4e2-466b-98ba-04a5c1bd380b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095753794 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.3095753794
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1262190742
Short name T4
Test name
Test status
Simulation time 8976953994 ps
CPU time 2.6 seconds
Started Dec 24 12:27:29 PM PST 23
Finished Dec 24 12:27:34 PM PST 23
Peak memory 162532 kb
Host smart-9aa21640-517e-4165-b13f-a9b327340130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262190742 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1262190742
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2358294203
Short name T3
Test name
Test status
Simulation time 10769837035 ps
CPU time 2.93 seconds
Started Dec 24 12:26:26 PM PST 23
Finished Dec 24 12:26:31 PM PST 23
Peak memory 162436 kb
Host smart-8cbaac94-a5f5-4a92-8b5d-da36b9834bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358294203 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2358294203
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3896868686
Short name T10
Test name
Test status
Simulation time 11203344735 ps
CPU time 3.09 seconds
Started Dec 24 12:25:53 PM PST 23
Finished Dec 24 12:25:57 PM PST 23
Peak memory 162516 kb
Host smart-525f14c6-d78b-4277-a44a-5a3c2dfc0229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896868686 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.3896868686
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.1101492624
Short name T2
Test name
Test status
Simulation time 10114065793 ps
CPU time 2.79 seconds
Started Dec 24 12:27:09 PM PST 23
Finished Dec 24 12:27:15 PM PST 23
Peak memory 162384 kb
Host smart-4294fc28-6897-4106-bc60-487cb6fb2029
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101492624 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.1101492624
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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