Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3549618787

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.961906241
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.795991205
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.1527579797
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2593795571
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.3866883619
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.2338920035
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.1216834675
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.1341269681
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.3553367836



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1216834675 Dec 27 12:48:51 PM PST 23 Dec 27 12:48:56 PM PST 23 9812185540 ps
T2 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3553367836 Dec 27 12:48:54 PM PST 23 Dec 27 12:49:00 PM PST 23 9289981073 ps
T3 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2338920035 Dec 27 12:48:56 PM PST 23 Dec 27 12:49:01 PM PST 23 9812266769 ps
T4 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3866883619 Dec 27 12:48:47 PM PST 23 Dec 27 12:48:53 PM PST 23 9969281425 ps
T5 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.961906241 Dec 27 12:48:33 PM PST 23 Dec 27 12:48:40 PM PST 23 10619417588 ps
T6 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2593795571 Dec 27 12:49:15 PM PST 23 Dec 27 12:49:26 PM PST 23 11070325734 ps
T7 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3549618787 Dec 27 12:49:00 PM PST 23 Dec 27 12:49:06 PM PST 23 11203187650 ps
T8 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1527579797 Dec 27 12:48:41 PM PST 23 Dec 27 12:48:45 PM PST 23 8641498241 ps
T9 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.795991205 Dec 27 12:48:47 PM PST 23 Dec 27 12:48:52 PM PST 23 9328774676 ps
T10 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.1341269681 Dec 27 12:48:54 PM PST 23 Dec 27 12:49:00 PM PST 23 10932504451 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3549618787
Short name T7
Test name
Test status
Simulation time 11203187650 ps
CPU time 2.98 seconds
Started Dec 27 12:49:00 PM PST 23
Finished Dec 27 12:49:06 PM PST 23
Peak memory 162536 kb
Host smart-139394b2-42f0-402c-9f71-e8a312104948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549618787 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.3549618787
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.961906241
Short name T5
Test name
Test status
Simulation time 10619417588 ps
CPU time 2.92 seconds
Started Dec 27 12:48:33 PM PST 23
Finished Dec 27 12:48:40 PM PST 23
Peak memory 162512 kb
Host smart-0eed82b6-dcaa-4fd7-b280-572d7b1baa33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961906241 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.961906241
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.795991205
Short name T9
Test name
Test status
Simulation time 9328774676 ps
CPU time 2.62 seconds
Started Dec 27 12:48:47 PM PST 23
Finished Dec 27 12:48:52 PM PST 23
Peak memory 162648 kb
Host smart-5cd1a882-f92b-4897-8ad4-3c19c0809fb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795991205 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.795991205
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1527579797
Short name T8
Test name
Test status
Simulation time 8641498241 ps
CPU time 2.57 seconds
Started Dec 27 12:48:41 PM PST 23
Finished Dec 27 12:48:45 PM PST 23
Peak memory 162600 kb
Host smart-16a18890-6479-4e99-beba-9ab0c81a4da1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527579797 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1527579797
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2593795571
Short name T6
Test name
Test status
Simulation time 11070325734 ps
CPU time 2.93 seconds
Started Dec 27 12:49:15 PM PST 23
Finished Dec 27 12:49:26 PM PST 23
Peak memory 162612 kb
Host smart-0e432930-7a62-40d4-9bd6-940372a99d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593795571 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2593795571
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3866883619
Short name T4
Test name
Test status
Simulation time 9969281425 ps
CPU time 2.86 seconds
Started Dec 27 12:48:47 PM PST 23
Finished Dec 27 12:48:53 PM PST 23
Peak memory 162628 kb
Host smart-e99d249e-8397-43c2-bde5-dc74ed11a53e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866883619 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.3866883619
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2338920035
Short name T3
Test name
Test status
Simulation time 9812266769 ps
CPU time 2.76 seconds
Started Dec 27 12:48:56 PM PST 23
Finished Dec 27 12:49:01 PM PST 23
Peak memory 162516 kb
Host smart-30b44633-4499-40ad-bb75-487044636056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338920035 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.2338920035
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1216834675
Short name T1
Test name
Test status
Simulation time 9812185540 ps
CPU time 2.79 seconds
Started Dec 27 12:48:51 PM PST 23
Finished Dec 27 12:48:56 PM PST 23
Peak memory 162532 kb
Host smart-364e9968-d10b-4c07-9d72-867879e1c727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216834675 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.1216834675
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.1341269681
Short name T10
Test name
Test status
Simulation time 10932504451 ps
CPU time 2.92 seconds
Started Dec 27 12:48:54 PM PST 23
Finished Dec 27 12:49:00 PM PST 23
Peak memory 162520 kb
Host smart-df314239-9017-4060-ab67-9024446a2fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341269681 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.1341269681
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.3553367836
Short name T2
Test name
Test status
Simulation time 9289981073 ps
CPU time 2.77 seconds
Started Dec 27 12:48:54 PM PST 23
Finished Dec 27 12:49:00 PM PST 23
Peak memory 162600 kb
Host smart-97f64c81-effa-41b8-9d9c-11281d2296f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553367836 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.3553367836
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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