Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2541217967

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.4065329652
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.1714208073
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.3363063866
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.2662572604
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.3223479628
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.351302549
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.1362289865
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.3951904323
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.2455243830



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1362289865 Dec 31 12:46:16 PM PST 23 Dec 31 12:46:20 PM PST 23 10237397592 ps
T2 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2455243830 Dec 31 12:46:06 PM PST 23 Dec 31 12:46:10 PM PST 23 11203189874 ps
T3 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2541217967 Dec 31 12:46:43 PM PST 23 Dec 31 12:46:48 PM PST 23 11337756258 ps
T4 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1714208073 Dec 31 12:46:33 PM PST 23 Dec 31 12:46:39 PM PST 23 11203342137 ps
T5 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3951904323 Dec 31 12:46:27 PM PST 23 Dec 31 12:46:32 PM PST 23 9969307328 ps
T6 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3363063866 Dec 31 12:46:44 PM PST 23 Dec 31 12:46:48 PM PST 23 9812188070 ps
T7 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.351302549 Dec 31 12:46:02 PM PST 23 Dec 31 12:46:05 PM PST 23 9969463518 ps
T8 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3223479628 Dec 31 12:46:09 PM PST 23 Dec 31 12:46:14 PM PST 23 10932533194 ps
T9 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.4065329652 Dec 31 12:46:01 PM PST 23 Dec 31 12:46:05 PM PST 23 11337840333 ps
T10 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2662572604 Dec 31 12:46:26 PM PST 23 Dec 31 12:46:30 PM PST 23 11337889551 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2541217967
Short name T3
Test name
Test status
Simulation time 11337756258 ps
CPU time 2.97 seconds
Started Dec 31 12:46:43 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 162588 kb
Host smart-ee7e72dd-2682-4ded-b423-40220b28533a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541217967 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.2541217967
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.4065329652
Short name T9
Test name
Test status
Simulation time 11337840333 ps
CPU time 3.01 seconds
Started Dec 31 12:46:01 PM PST 23
Finished Dec 31 12:46:05 PM PST 23
Peak memory 162468 kb
Host smart-130c4b30-e68e-4141-aff6-a89786f12f64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065329652 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.4065329652
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1714208073
Short name T4
Test name
Test status
Simulation time 11203342137 ps
CPU time 3.01 seconds
Started Dec 31 12:46:33 PM PST 23
Finished Dec 31 12:46:39 PM PST 23
Peak memory 162656 kb
Host smart-2143f7e1-55d9-4c55-9798-d5391028bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714208073 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1714208073
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3363063866
Short name T6
Test name
Test status
Simulation time 9812188070 ps
CPU time 2.73 seconds
Started Dec 31 12:46:44 PM PST 23
Finished Dec 31 12:46:48 PM PST 23
Peak memory 162564 kb
Host smart-377d9269-b954-41ab-8278-953d7ae7221b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363063866 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.3363063866
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2662572604
Short name T10
Test name
Test status
Simulation time 11337889551 ps
CPU time 3.02 seconds
Started Dec 31 12:46:26 PM PST 23
Finished Dec 31 12:46:30 PM PST 23
Peak memory 162476 kb
Host smart-fdf333b5-af1a-4b0e-a3b1-6d41017c49fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662572604 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2662572604
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.3223479628
Short name T8
Test name
Test status
Simulation time 10932533194 ps
CPU time 2.92 seconds
Started Dec 31 12:46:09 PM PST 23
Finished Dec 31 12:46:14 PM PST 23
Peak memory 162560 kb
Host smart-34ccb50f-d81a-4730-8534-434103b4593c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223479628 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.3223479628
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.351302549
Short name T7
Test name
Test status
Simulation time 9969463518 ps
CPU time 2.75 seconds
Started Dec 31 12:46:02 PM PST 23
Finished Dec 31 12:46:05 PM PST 23
Peak memory 162540 kb
Host smart-e98f87f5-7e85-4382-a097-dab8c33f651c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351302549 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.351302549
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1362289865
Short name T1
Test name
Test status
Simulation time 10237397592 ps
CPU time 2.78 seconds
Started Dec 31 12:46:16 PM PST 23
Finished Dec 31 12:46:20 PM PST 23
Peak memory 162644 kb
Host smart-1c17c011-0c16-470d-9426-a79e6cfc1e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362289865 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.1362289865
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3951904323
Short name T5
Test name
Test status
Simulation time 9969307328 ps
CPU time 2.74 seconds
Started Dec 31 12:46:27 PM PST 23
Finished Dec 31 12:46:32 PM PST 23
Peak memory 162536 kb
Host smart-b7dfdcaf-c6a5-457d-b01e-892114050e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951904323 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.3951904323
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2455243830
Short name T2
Test name
Test status
Simulation time 11203189874 ps
CPU time 2.94 seconds
Started Dec 31 12:46:06 PM PST 23
Finished Dec 31 12:46:10 PM PST 23
Peak memory 162644 kb
Host smart-829afbe6-cf93-4576-b672-e4ebb4f92b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455243830 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2455243830
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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