| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 91.71 | 91.71 | 98.41 | 98.41 | 86.21 | 86.21 | 100.00 | 100.00 | 92.31 | 92.31 | 98.31 | 98.31 | 75.00 | 75.00 | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3412722798 |
| Name |
|---|
| /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2469232730 |
| /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1808966860 |
| /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3405157413 |
| /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2029451006 |
| /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1482936457 |
| /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1066545405 |
| /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1704931482 |
| /workspace/coverage/default/8.rstmgr_cnsty_chk_test.812478471 |
| /workspace/coverage/default/9.rstmgr_cnsty_chk_test.253340825 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2029451006 | Jan 03 12:21:17 PM PST 24 | Jan 03 12:21:40 PM PST 24 | 10114168166 ps | ||
| T2 | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1808966860 | Jan 03 12:21:16 PM PST 24 | Jan 03 12:21:40 PM PST 24 | 8955005749 ps | ||
| T3 | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.812478471 | Jan 03 12:21:18 PM PST 24 | Jan 03 12:21:37 PM PST 24 | 10114168436 ps | ||
| T4 | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2469232730 | Jan 03 12:21:09 PM PST 24 | Jan 03 12:21:33 PM PST 24 | 8752421563 ps | ||
| T5 | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.253340825 | Jan 03 12:21:16 PM PST 24 | Jan 03 12:21:40 PM PST 24 | 11337891686 ps | ||
| T6 | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1482936457 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:21:33 PM PST 24 | 8991137688 ps | ||
| T7 | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3412722798 | Jan 03 12:21:08 PM PST 24 | Jan 03 12:21:33 PM PST 24 | 10370354284 ps | ||
| T8 | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1704931482 | Jan 03 12:21:17 PM PST 24 | Jan 03 12:21:40 PM PST 24 | 9156660354 ps | ||
| T9 | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3405157413 | Jan 03 12:21:16 PM PST 24 | Jan 03 12:21:40 PM PST 24 | 9271461133 ps | ||
| T10 | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1066545405 | Jan 03 12:21:18 PM PST 24 | Jan 03 12:21:37 PM PST 24 | 11338122065 ps |
| Test location | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.3412722798 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 10370354284 ps |
| CPU time | 2.97 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:21:33 PM PST 24 |
| Peak memory | 160596 kb |
| Host | smart-b8f28321-9060-4ad5-a15b-0f3c4cf426fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3412722798 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.3412722798 |
| Directory | /workspace/1.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2469232730 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 8752421563 ps |
| CPU time | 2.6 seconds |
| Started | Jan 03 12:21:09 PM PST 24 |
| Finished | Jan 03 12:21:33 PM PST 24 |
| Peak memory | 162180 kb |
| Host | smart-2ddc2ecf-08eb-41c1-b700-e8dc2ce0bcb5 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2469232730 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.2469232730 |
| Directory | /workspace/0.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1808966860 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 8955005749 ps |
| CPU time | 2.6 seconds |
| Started | Jan 03 12:21:16 PM PST 24 |
| Finished | Jan 03 12:21:40 PM PST 24 |
| Peak memory | 162516 kb |
| Host | smart-79a979a3-fad7-4f8d-b718-f9ce96de66a6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1808966860 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1808966860 |
| Directory | /workspace/2.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3405157413 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9271461133 ps |
| CPU time | 2.72 seconds |
| Started | Jan 03 12:21:16 PM PST 24 |
| Finished | Jan 03 12:21:40 PM PST 24 |
| Peak memory | 162516 kb |
| Host | smart-af8ce0ab-e455-4e93-8821-82a8cd3f91ad |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3405157413 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.3405157413 |
| Directory | /workspace/3.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.2029451006 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 10114168166 ps |
| CPU time | 2.83 seconds |
| Started | Jan 03 12:21:17 PM PST 24 |
| Finished | Jan 03 12:21:40 PM PST 24 |
| Peak memory | 162516 kb |
| Host | smart-ee7c063e-df7b-4830-9065-45a7144bbdc2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2029451006 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.2029451006 |
| Directory | /workspace/4.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1482936457 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 8991137688 ps |
| CPU time | 2.8 seconds |
| Started | Jan 03 12:21:08 PM PST 24 |
| Finished | Jan 03 12:21:33 PM PST 24 |
| Peak memory | 160872 kb |
| Host | smart-46bd34f9-418f-43e2-900e-434f51e3b2f1 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1482936457 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1482936457 |
| Directory | /workspace/5.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1066545405 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 11338122065 ps |
| CPU time | 2.96 seconds |
| Started | Jan 03 12:21:18 PM PST 24 |
| Finished | Jan 03 12:21:37 PM PST 24 |
| Peak memory | 162412 kb |
| Host | smart-ecf24f31-71de-4b1f-b45b-57bf850ed1a0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1066545405 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1066545405 |
| Directory | /workspace/6.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.1704931482 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9156660354 ps |
| CPU time | 2.62 seconds |
| Started | Jan 03 12:21:17 PM PST 24 |
| Finished | Jan 03 12:21:40 PM PST 24 |
| Peak memory | 162516 kb |
| Host | smart-4c3b3e1a-9946-4588-850e-35e934114377 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1704931482 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.1704931482 |
| Directory | /workspace/7.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.812478471 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 10114168436 ps |
| CPU time | 2.81 seconds |
| Started | Jan 03 12:21:18 PM PST 24 |
| Finished | Jan 03 12:21:37 PM PST 24 |
| Peak memory | 162360 kb |
| Host | smart-840e6c73-8668-4835-9be6-b3817cb1430b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=812478471 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.812478471 |
| Directory | /workspace/8.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.253340825 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 11337891686 ps |
| CPU time | 3.05 seconds |
| Started | Jan 03 12:21:16 PM PST 24 |
| Finished | Jan 03 12:21:40 PM PST 24 |
| Peak memory | 162528 kb |
| Host | smart-f936b346-74a0-4fc5-a23c-0ccefaf2cdd6 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=253340825 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.253340825 |
| Directory | /workspace/9.rstmgr_cnsty_chk_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |