Total Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.87	98.41	86.21	100.00	92.31	98.31	100.00

Total tests in report: 5

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Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
91.71	91.71	98.41	98.41	86.21	86.21	100.00	100.00	92.31	92.31	98.31	98.31	75.00	75.00	/workspace/coverage/default/0.rstmgr_cnsty_chk_test.1608206424

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Tests that do not contribute to grading

Name
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.118128015
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1774233936
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.4233128666
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1453234934

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Total test records in report: 5

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TEST NO	TEST LOCATION	TEST NAME	STATUS	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1453234934			Jan 07 12:33:57 PM PST 24	Jan 07 12:35:42 PM PST 24	8917270265 ps
T2	/workspace/coverage/default/2.rstmgr_cnsty_chk_test.118128015			Jan 07 12:33:50 PM PST 24	Jan 07 12:34:58 PM PST 24	11070312785 ps
T3	/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1774233936			Jan 07 12:34:42 PM PST 24	Jan 07 12:36:06 PM PST 24	11203186440 ps
T4	/workspace/coverage/default/5.rstmgr_cnsty_chk_test.4233128666			Jan 07 12:34:19 PM PST 24	Jan 07 12:35:41 PM PST 24	9526171621 ps
T5	/workspace/coverage/default/0.rstmgr_cnsty_chk_test.1608206424			Jan 07 12:34:25 PM PST 24	Jan 07 12:36:15 PM PST 24	10237366853 ps

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Test location	/workspace/coverage/default/0.rstmgr_cnsty_chk_test.1608206424
Short name	T5
Test name
Test status
Simulation time	10237366853 ps
CPU time	2.78 seconds
Started	Jan 07 12:34:25 PM PST 24
Finished	Jan 07 12:36:15 PM PST 24
Peak memory	162504 kb
Host	smart-16c9901f-319e-4079-b980-3650fb16af8b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1608206424 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1608206424
Directory	/workspace/0.rstmgr_cnsty_chk_test/latest

---

Test location	/workspace/coverage/default/2.rstmgr_cnsty_chk_test.118128015
Short name	T2
Test name
Test status
Simulation time	11070312785 ps
CPU time	2.93 seconds
Started	Jan 07 12:33:50 PM PST 24
Finished	Jan 07 12:34:58 PM PST 24
Peak memory	162572 kb
Host	smart-7227af7d-9b25-44e5-b0e6-d2f0138eddf0
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=118128015 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.118128015
Directory	/workspace/2.rstmgr_cnsty_chk_test/latest

---

Test location	/workspace/coverage/default/4.rstmgr_cnsty_chk_test.1774233936
Short name	T3
Test name
Test status
Simulation time	11203186440 ps
CPU time	2.96 seconds
Started	Jan 07 12:34:42 PM PST 24
Finished	Jan 07 12:36:06 PM PST 24
Peak memory	162628 kb
Host	smart-312d8362-5de4-43d5-b10a-ef8bc06a710c
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1774233936 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1774233936
Directory	/workspace/4.rstmgr_cnsty_chk_test/latest

---

Test location	/workspace/coverage/default/5.rstmgr_cnsty_chk_test.4233128666
Short name	T4
Test name
Test status
Simulation time	9526171621 ps
CPU time	2.65 seconds
Started	Jan 07 12:34:19 PM PST 24
Finished	Jan 07 12:35:41 PM PST 24
Peak memory	162532 kb
Host	smart-2cfaf491-fd38-4af1-9dd0-84cfe8636c64
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=4233128666 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.4233128666
Directory	/workspace/5.rstmgr_cnsty_chk_test/latest

---

Test location	/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1453234934
Short name	T1
Test name
Test status
Simulation time	8917270265 ps
CPU time	2.55 seconds
Started	Jan 07 12:33:57 PM PST 24
Finished	Jan 07 12:35:42 PM PST 24
Peak memory	162472 kb
Host	smart-c4622d81-74fb-4d39-b81a-889a36f8425b
User	root
Command	/workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1453234934 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1453234934
Directory	/workspace/6.rstmgr_cnsty_chk_test/latest