042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | TOTAL | 0 | 0 | -- | |||
| V2 | TOTAL | 0 | 0 | -- | |||
| V2S | unexpected_child_reset_activity | rstmgr_cnsty_chk_smoke | 0 | 0 | -- | ||
| V2S | child_reset_asserts_late | child_reset_asserts_late | 0 | 0 | -- | ||
| V2S | child_reset_releases_late | child_reset_releases_late | 0 | 0 | -- | ||
| V2S | parent_reset_asserts_late | parent_reset_asserts_late | 0 | 0 | -- | ||
| V2S | parent_reset_releases_late | parent_reset_releases_late | 0 | 0 | -- | ||
| V2S | TOTAL | 0 | 0 | -- | |||
| V3 | TOTAL | 0 | 0 | -- | |||
| Unmapped tests | rstmgr_cnsty_chk_test | 2.960s | 11.203ms | 5 | 10 | 50.00 | |
| TOTAL | 5 | 10 | 50.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| N.A. | 1 | 1 | 0 | 0.00 |
| V2S | 5 | 0 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
|---|---|---|---|---|---|---|
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
Exit reason: Error: User command failed Job returned non-zero exit code has 5 failures:
1.rstmgr_cnsty_chk_test.21002932308547952988991848444805921292939993050054311406194678162835529174387
Log /container/opentitan-public/scratch/os_regression/rstmgr_cnsty_chk-sim-vcs/1.rstmgr_cnsty_chk_test/latest/run.log
[make]: simulate
cd /workspace/1.rstmgr_cnsty_chk_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914604915 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.1914604915
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
3.rstmgr_cnsty_chk_test.107814820404952024033449065027676012735948010110014576823663806041037389705675
Log /container/opentitan-public/scratch/os_regression/rstmgr_cnsty_chk-sim-vcs/3.rstmgr_cnsty_chk_test/latest/run.log
[make]: simulate
cd /workspace/3.rstmgr_cnsty_chk_test/latest && /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878457291 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.878457291
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:34 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 3 more failures.