| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 91.71 | 91.71 | 98.41 | 98.41 | 86.21 | 86.21 | 100.00 | 100.00 | 92.31 | 92.31 | 98.31 | 98.31 | 75.00 | 75.00 | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.167160281 |
| Name |
|---|
| /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3290585359 |
| /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3969320228 |
| /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2144241206 |
| /workspace/coverage/default/4.rstmgr_cnsty_chk_test.3797510447 |
| /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1759822898 |
| /workspace/coverage/default/6.rstmgr_cnsty_chk_test.980663029 |
| /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2776470622 |
| /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3651757216 |
| /workspace/coverage/default/9.rstmgr_cnsty_chk_test.267553014 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.167160281 | Jan 10 12:23:25 PM PST 24 | Jan 10 12:23:31 PM PST 24 | 11070535712 ps | ||
| T2 | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.267553014 | Jan 10 12:22:18 PM PST 24 | Jan 10 12:22:21 PM PST 24 | 9684081636 ps | ||
| T3 | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.980663029 | Jan 10 12:31:25 PM PST 24 | Jan 10 12:32:15 PM PST 24 | 8990991979 ps | ||
| T4 | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1759822898 | Jan 10 12:29:05 PM PST 24 | Jan 10 12:29:28 PM PST 24 | 9271482337 ps | ||
| T5 | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3290585359 | Jan 10 12:27:44 PM PST 24 | Jan 10 12:27:59 PM PST 24 | 9113265631 ps | ||
| T6 | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.3797510447 | Jan 10 12:27:53 PM PST 24 | Jan 10 12:28:09 PM PST 24 | 9429372253 ps | ||
| T7 | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2144241206 | Jan 10 12:23:59 PM PST 24 | Jan 10 12:24:08 PM PST 24 | 9129844756 ps | ||
| T8 | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2776470622 | Jan 10 12:31:26 PM PST 24 | Jan 10 12:32:17 PM PST 24 | 9969251669 ps | ||
| T9 | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3651757216 | Jan 10 12:26:48 PM PST 24 | Jan 10 12:26:56 PM PST 24 | 9812294574 ps | ||
| T10 | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3969320228 | Jan 10 12:22:18 PM PST 24 | Jan 10 12:22:21 PM PST 24 | 9684362224 ps |
| Test location | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.167160281 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 11070535712 ps |
| CPU time | 3.01 seconds |
| Started | Jan 10 12:23:25 PM PST 24 |
| Finished | Jan 10 12:23:31 PM PST 24 |
| Peak memory | 162516 kb |
| Host | smart-fc4f88d3-eead-45de-b345-d388d4fe848e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=167160281 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.167160281 |
| Directory | /workspace/1.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.3290585359 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 9113265631 ps |
| CPU time | 2.62 seconds |
| Started | Jan 10 12:27:44 PM PST 24 |
| Finished | Jan 10 12:27:59 PM PST 24 |
| Peak memory | 162528 kb |
| Host | smart-2220488c-4484-4977-82f1-f3cff1e245e0 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3290585359 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.3290585359 |
| Directory | /workspace/0.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3969320228 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 9684362224 ps |
| CPU time | 2.82 seconds |
| Started | Jan 10 12:22:18 PM PST 24 |
| Finished | Jan 10 12:22:21 PM PST 24 |
| Peak memory | 162424 kb |
| Host | smart-7ad930f6-be33-4ee4-ad8d-914e039b5134 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3969320228 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.3969320228 |
| Directory | /workspace/2.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.2144241206 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9129844756 ps |
| CPU time | 2.64 seconds |
| Started | Jan 10 12:23:59 PM PST 24 |
| Finished | Jan 10 12:24:08 PM PST 24 |
| Peak memory | 162772 kb |
| Host | smart-596b57d1-6fc6-4b55-98b8-93a3b613b87f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2144241206 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.2144241206 |
| Directory | /workspace/3.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.3797510447 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 9429372253 ps |
| CPU time | 2.73 seconds |
| Started | Jan 10 12:27:53 PM PST 24 |
| Finished | Jan 10 12:28:09 PM PST 24 |
| Peak memory | 162748 kb |
| Host | smart-73a40981-e332-464e-828a-339d0cf7cdf2 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3797510447 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.3797510447 |
| Directory | /workspace/4.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1759822898 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9271482337 ps |
| CPU time | 2.65 seconds |
| Started | Jan 10 12:29:05 PM PST 24 |
| Finished | Jan 10 12:29:28 PM PST 24 |
| Peak memory | 162324 kb |
| Host | smart-3f7d916e-b146-44e0-81dd-0f6cc309c084 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1759822898 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1759822898 |
| Directory | /workspace/5.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.980663029 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 8990991979 ps |
| CPU time | 2.61 seconds |
| Started | Jan 10 12:31:25 PM PST 24 |
| Finished | Jan 10 12:32:15 PM PST 24 |
| Peak memory | 161908 kb |
| Host | smart-b3ab5ecf-1a08-423e-9fa1-b2a837479a6f |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=980663029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.980663029 |
| Directory | /workspace/6.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.2776470622 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9969251669 ps |
| CPU time | 2.72 seconds |
| Started | Jan 10 12:31:26 PM PST 24 |
| Finished | Jan 10 12:32:17 PM PST 24 |
| Peak memory | 162236 kb |
| Host | smart-f5a02bcb-5d7f-4cc5-916f-fa964191d35e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2776470622 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.2776470622 |
| Directory | /workspace/7.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.3651757216 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 9812294574 ps |
| CPU time | 2.83 seconds |
| Started | Jan 10 12:26:48 PM PST 24 |
| Finished | Jan 10 12:26:56 PM PST 24 |
| Peak memory | 162536 kb |
| Host | smart-fe62b27a-2d31-47e1-b19e-8e00b5f0b038 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3651757216 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.3651757216 |
| Directory | /workspace/8.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.267553014 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9684081636 ps |
| CPU time | 2.93 seconds |
| Started | Jan 10 12:22:18 PM PST 24 |
| Finished | Jan 10 12:22:21 PM PST 24 |
| Peak memory | 162180 kb |
| Host | smart-d8c6000d-a571-40be-8db8-dfb50be5d664 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=267553014 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.267553014 |
| Directory | /workspace/9.rstmgr_cnsty_chk_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |