Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2298927828

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.2745463403
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.3919807435
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.3417997640
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.994253233
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.4253852421
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.2522376029
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.3485098775
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.198171229
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.2631282517



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.994253233 Jan 14 12:18:07 PM PST 24 Jan 14 12:18:10 PM PST 24 8560207786 ps
T2 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2745463403 Jan 14 12:18:08 PM PST 24 Jan 14 12:18:11 PM PST 24 9526219245 ps
T3 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.4253852421 Jan 14 12:18:08 PM PST 24 Jan 14 12:18:11 PM PST 24 11070082132 ps
T4 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3919807435 Jan 14 12:18:08 PM PST 24 Jan 14 12:18:11 PM PST 24 9053594538 ps
T5 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3417997640 Jan 14 12:16:28 PM PST 24 Jan 14 12:16:31 PM PST 24 10237400181 ps
T6 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2631282517 Jan 14 12:16:28 PM PST 24 Jan 14 12:16:31 PM PST 24 9328718069 ps
T7 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.198171229 Jan 14 12:16:28 PM PST 24 Jan 14 12:16:31 PM PST 24 8675505587 ps
T8 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2298927828 Jan 14 12:18:08 PM PST 24 Jan 14 12:18:11 PM PST 24 10237398415 ps
T9 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3485098775 Jan 14 12:16:27 PM PST 24 Jan 14 12:16:30 PM PST 24 9230138808 ps
T10 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2522376029 Jan 14 12:16:43 PM PST 24 Jan 14 12:16:47 PM PST 24 9271461161 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.2298927828
Short name T8
Test name
Test status
Simulation time 10237398415 ps
CPU time 2.84 seconds
Started Jan 14 12:18:08 PM PST 24
Finished Jan 14 12:18:11 PM PST 24
Peak memory 162368 kb
Host smart-c7ef546a-67de-4357-a81f-b464560f7782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298927828 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.2298927828
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2745463403
Short name T2
Test name
Test status
Simulation time 9526219245 ps
CPU time 2.76 seconds
Started Jan 14 12:18:08 PM PST 24
Finished Jan 14 12:18:11 PM PST 24
Peak memory 162368 kb
Host smart-dbd3f911-0d75-4c47-877c-d238a6bf876c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745463403 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.2745463403
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.3919807435
Short name T4
Test name
Test status
Simulation time 9053594538 ps
CPU time 2.64 seconds
Started Jan 14 12:18:08 PM PST 24
Finished Jan 14 12:18:11 PM PST 24
Peak memory 162340 kb
Host smart-a3cbdf16-e0fa-4c73-ac37-28a9f1440761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919807435 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.3919807435
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.3417997640
Short name T5
Test name
Test status
Simulation time 10237400181 ps
CPU time 2.9 seconds
Started Jan 14 12:16:28 PM PST 24
Finished Jan 14 12:16:31 PM PST 24
Peak memory 162680 kb
Host smart-62bba0bb-4dca-43eb-a629-cb0c542471f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417997640 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.3417997640
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.994253233
Short name T1
Test name
Test status
Simulation time 8560207786 ps
CPU time 2.64 seconds
Started Jan 14 12:18:07 PM PST 24
Finished Jan 14 12:18:10 PM PST 24
Peak memory 162284 kb
Host smart-3522ff43-4761-4230-93de-82a34e190b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994253233 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.994253233
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.4253852421
Short name T3
Test name
Test status
Simulation time 11070082132 ps
CPU time 3.05 seconds
Started Jan 14 12:18:08 PM PST 24
Finished Jan 14 12:18:11 PM PST 24
Peak memory 162340 kb
Host smart-5e50184a-4294-40fd-aa64-478e30fe6f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4253852421 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.4253852421
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.2522376029
Short name T10
Test name
Test status
Simulation time 9271461161 ps
CPU time 2.68 seconds
Started Jan 14 12:16:43 PM PST 24
Finished Jan 14 12:16:47 PM PST 24
Peak memory 162896 kb
Host smart-18074a6d-5c9e-42c7-80f8-eaa6eaf37c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522376029 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.2522376029
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3485098775
Short name T9
Test name
Test status
Simulation time 9230138808 ps
CPU time 2.68 seconds
Started Jan 14 12:16:27 PM PST 24
Finished Jan 14 12:16:30 PM PST 24
Peak memory 162680 kb
Host smart-38a7aac7-a206-42a8-b468-0ab28982cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485098775 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.3485098775
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.198171229
Short name T7
Test name
Test status
Simulation time 8675505587 ps
CPU time 2.58 seconds
Started Jan 14 12:16:28 PM PST 24
Finished Jan 14 12:16:31 PM PST 24
Peak memory 162680 kb
Host smart-2cf9992d-c0c6-458a-a3bc-ddd6268a9d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198171229 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.198171229
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2631282517
Short name T6
Test name
Test status
Simulation time 9328718069 ps
CPU time 2.75 seconds
Started Jan 14 12:16:28 PM PST 24
Finished Jan 14 12:16:31 PM PST 24
Peak memory 162680 kb
Host smart-07463da9-bd26-4413-8955-4a1a1d8b776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631282517 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2631282517
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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