Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.87 98.41 86.21 100.00 92.31 98.31 100.00


Total tests in report: 10
Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE LINE COND TOGGLE FSM BRANCH ASSERT  
TOTAL INCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRTOTALINCRNAME
91.71 91.71 98.41 98.41 86.21 86.21 100.00 100.00 92.31 92.31 98.31 98.31 75.00 75.00 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.81698748

Tests that do not contribute to grading

Name
/workspace/coverage/default/1.rstmgr_cnsty_chk_test.2742122968
/workspace/coverage/default/2.rstmgr_cnsty_chk_test.1615986644
/workspace/coverage/default/3.rstmgr_cnsty_chk_test.274422395
/workspace/coverage/default/4.rstmgr_cnsty_chk_test.355305962
/workspace/coverage/default/5.rstmgr_cnsty_chk_test.228401567
/workspace/coverage/default/6.rstmgr_cnsty_chk_test.1014869979
/workspace/coverage/default/7.rstmgr_cnsty_chk_test.3145188048
/workspace/coverage/default/8.rstmgr_cnsty_chk_test.2706124231
/workspace/coverage/default/9.rstmgr_cnsty_chk_test.897451244



Total test records in report: 10
TEST NOTEST LOCATIONTEST NAMESTATUSSTARTEDFINISHEDSIMULATION TIME
T1 /workspace/coverage/default/9.rstmgr_cnsty_chk_test.897451244 Jan 21 12:49:57 PM PST 24 Jan 21 12:50:01 PM PST 24 9684109721 ps
T2 /workspace/coverage/default/5.rstmgr_cnsty_chk_test.228401567 Jan 21 12:19:11 PM PST 24 Jan 21 12:19:16 PM PST 24 9156856810 ps
T3 /workspace/coverage/default/3.rstmgr_cnsty_chk_test.274422395 Jan 21 12:31:34 PM PST 24 Jan 21 12:31:37 PM PST 24 9526216361 ps
T4 /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3145188048 Jan 21 12:49:59 PM PST 24 Jan 21 12:50:04 PM PST 24 9252134207 ps
T5 /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1014869979 Jan 21 12:29:56 PM PST 24 Jan 21 12:29:59 PM PST 24 9156890927 ps
T6 /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2742122968 Jan 21 12:18:20 PM PST 24 Jan 21 12:18:24 PM PST 24 10769832985 ps
T7 /workspace/coverage/default/0.rstmgr_cnsty_chk_test.81698748 Jan 21 01:35:30 PM PST 24 Jan 21 01:35:33 PM PST 24 9156713045 ps
T8 /workspace/coverage/default/4.rstmgr_cnsty_chk_test.355305962 Jan 21 12:18:37 PM PST 24 Jan 21 12:18:41 PM PST 24 11337708204 ps
T9 /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2706124231 Jan 21 12:19:52 PM PST 24 Jan 21 12:19:55 PM PST 24 8854719222 ps
T10 /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1615986644 Jan 21 12:18:38 PM PST 24 Jan 21 12:18:42 PM PST 24 10237452902 ps

Test location /workspace/coverage/default/0.rstmgr_cnsty_chk_test.81698748
Short name T7
Test name
Test status
Simulation time 9156713045 ps
CPU time 2.59 seconds
Started Jan 21 01:35:30 PM PST 24
Finished Jan 21 01:35:33 PM PST 24
Peak memory 162080 kb
Host smart-03cb053b-3ddd-46bd-a46d-f09ae57e65b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81698748 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.81698748
Directory /workspace/0.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2742122968
Short name T6
Test name
Test status
Simulation time 10769832985 ps
CPU time 2.91 seconds
Started Jan 21 12:18:20 PM PST 24
Finished Jan 21 12:18:24 PM PST 24
Peak memory 162188 kb
Host smart-c0d67acb-feee-48fc-8076-8abaaf78a460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742122968 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.2742122968
Directory /workspace/1.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/2.rstmgr_cnsty_chk_test.1615986644
Short name T10
Test name
Test status
Simulation time 10237452902 ps
CPU time 2.77 seconds
Started Jan 21 12:18:38 PM PST 24
Finished Jan 21 12:18:42 PM PST 24
Peak memory 161896 kb
Host smart-70525d53-3bba-477c-94b4-4ee4cc850f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615986644 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.1615986644
Directory /workspace/2.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/3.rstmgr_cnsty_chk_test.274422395
Short name T3
Test name
Test status
Simulation time 9526216361 ps
CPU time 2.66 seconds
Started Jan 21 12:31:34 PM PST 24
Finished Jan 21 12:31:37 PM PST 24
Peak memory 161908 kb
Host smart-2c87ea69-2b3c-41c4-ae7f-9fec01a1e973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274422395 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.274422395
Directory /workspace/3.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/4.rstmgr_cnsty_chk_test.355305962
Short name T8
Test name
Test status
Simulation time 11337708204 ps
CPU time 3.07 seconds
Started Jan 21 12:18:37 PM PST 24
Finished Jan 21 12:18:41 PM PST 24
Peak memory 161820 kb
Host smart-82c2c4b9-3625-428e-af6d-49cea27e235e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355305962 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.355305962
Directory /workspace/4.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/5.rstmgr_cnsty_chk_test.228401567
Short name T2
Test name
Test status
Simulation time 9156856810 ps
CPU time 2.69 seconds
Started Jan 21 12:19:11 PM PST 24
Finished Jan 21 12:19:16 PM PST 24
Peak memory 162180 kb
Host smart-d0659297-7e04-4fe7-aee9-e18c33a5bf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228401567 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.228401567
Directory /workspace/5.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1014869979
Short name T5
Test name
Test status
Simulation time 9156890927 ps
CPU time 2.63 seconds
Started Jan 21 12:29:56 PM PST 24
Finished Jan 21 12:29:59 PM PST 24
Peak memory 161892 kb
Host smart-d5597f82-d90b-4673-b67e-cab6ecaf6409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014869979 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1014869979
Directory /workspace/6.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/7.rstmgr_cnsty_chk_test.3145188048
Short name T4
Test name
Test status
Simulation time 9252134207 ps
CPU time 2.61 seconds
Started Jan 21 12:49:59 PM PST 24
Finished Jan 21 12:50:04 PM PST 24
Peak memory 161848 kb
Host smart-d83aad08-6315-4381-b522-5c2e144ba66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145188048 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.3145188048
Directory /workspace/7.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/8.rstmgr_cnsty_chk_test.2706124231
Short name T9
Test name
Test status
Simulation time 8854719222 ps
CPU time 2.65 seconds
Started Jan 21 12:19:52 PM PST 24
Finished Jan 21 12:19:55 PM PST 24
Peak memory 162188 kb
Host smart-433cb029-f794-4c9f-bdb5-231db734b4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706124231 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
pace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.2706124231
Directory /workspace/8.rstmgr_cnsty_chk_test/latest

Test location /workspace/coverage/default/9.rstmgr_cnsty_chk_test.897451244
Short name T1
Test name
Test status
Simulation time 9684109721 ps
CPU time 2.77 seconds
Started Jan 21 12:49:57 PM PST 24
Finished Jan 21 12:50:01 PM PST 24
Peak memory 161704 kb
Host smart-7a3a1a39-de73-4f91-bde4-4b20072d194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897451244 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
ace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.897451244
Directory /workspace/9.rstmgr_cnsty_chk_test/latest
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