| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 95.87 | 98.41 | 86.21 | 100.00 | 92.31 | 98.31 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | ||||||||
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 91.71 | 91.71 | 98.41 | 98.41 | 86.21 | 86.21 | 100.00 | 100.00 | 92.31 | 92.31 | 98.31 | 98.31 | 75.00 | 75.00 | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1132539499 |
| Name |
|---|
| /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2554369761 |
| /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2857391595 |
| /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1130577510 |
| /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1709374075 |
| /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1590445839 |
| /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1110499409 |
| /workspace/coverage/default/7.rstmgr_cnsty_chk_test.532650196 |
| /workspace/coverage/default/8.rstmgr_cnsty_chk_test.320047801 |
| /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2677299753 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
|---|---|---|---|---|---|---|
| T1 | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1110499409 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:43:52 PM PST 24 | 9429354000 ps | ||
| T2 | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1590445839 | Jan 24 12:43:07 PM PST 24 | Jan 24 12:43:56 PM PST 24 | 9429239283 ps | ||
| T3 | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.532650196 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:43:53 PM PST 24 | 9429368142 ps | ||
| T4 | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.320047801 | Jan 24 12:43:11 PM PST 24 | Jan 24 12:44:01 PM PST 24 | 9526218814 ps | ||
| T5 | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1132539499 | Jan 24 12:55:13 PM PST 24 | Jan 24 12:55:45 PM PST 24 | 8854747012 ps | ||
| T6 | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2554369761 | Jan 24 12:43:02 PM PST 24 | Jan 24 12:43:49 PM PST 24 | 11338024593 ps | ||
| T7 | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2677299753 | Jan 24 12:43:05 PM PST 24 | Jan 24 12:43:52 PM PST 24 | 9429322064 ps | ||
| T8 | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2857391595 | Jan 24 12:43:02 PM PST 24 | Jan 24 12:43:48 PM PST 24 | 9683799141 ps | ||
| T9 | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1709374075 | Jan 24 12:43:13 PM PST 24 | Jan 24 12:44:03 PM PST 24 | 10370458113 ps | ||
| T10 | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1130577510 | Jan 24 12:43:04 PM PST 24 | Jan 24 12:43:51 PM PST 24 | 8970213335 ps |
| Test location | /workspace/coverage/default/0.rstmgr_cnsty_chk_test.1132539499 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 8854747012 ps |
| CPU time | 2.56 seconds |
| Started | Jan 24 12:55:13 PM PST 24 |
| Finished | Jan 24 12:55:45 PM PST 24 |
| Peak memory | 161912 kb |
| Host | smart-3986547c-dd6c-4fbd-9d49-06f78c60a82a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1132539499 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_cnsty_chk_test.1132539499 |
| Directory | /workspace/0.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/1.rstmgr_cnsty_chk_test.2554369761 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 11338024593 ps |
| CPU time | 3.01 seconds |
| Started | Jan 24 12:43:02 PM PST 24 |
| Finished | Jan 24 12:43:49 PM PST 24 |
| Peak memory | 161504 kb |
| Host | smart-e647df3c-05ca-473f-9e2e-74aeea32727e |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2554369761 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_cnsty_chk_test.2554369761 |
| Directory | /workspace/1.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/2.rstmgr_cnsty_chk_test.2857391595 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 9683799141 ps |
| CPU time | 2.74 seconds |
| Started | Jan 24 12:43:02 PM PST 24 |
| Finished | Jan 24 12:43:48 PM PST 24 |
| Peak memory | 161476 kb |
| Host | smart-48cb4578-e4af-474d-870a-7954a52fd261 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2857391595 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_cnsty_chk_test.2857391595 |
| Directory | /workspace/2.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/3.rstmgr_cnsty_chk_test.1130577510 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 8970213335 ps |
| CPU time | 2.75 seconds |
| Started | Jan 24 12:43:04 PM PST 24 |
| Finished | Jan 24 12:43:51 PM PST 24 |
| Peak memory | 161908 kb |
| Host | smart-4a7bd28c-e6f5-4a41-a062-464eb3cbd86b |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1130577510 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_cnsty_chk_test.1130577510 |
| Directory | /workspace/3.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/4.rstmgr_cnsty_chk_test.1709374075 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 10370458113 ps |
| CPU time | 2.83 seconds |
| Started | Jan 24 12:43:13 PM PST 24 |
| Finished | Jan 24 12:44:03 PM PST 24 |
| Peak memory | 161500 kb |
| Host | smart-23f09cbd-5c5a-497a-bc6f-9eced0110840 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1709374075 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_cnsty_chk_test.1709374075 |
| Directory | /workspace/4.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/5.rstmgr_cnsty_chk_test.1590445839 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 9429239283 ps |
| CPU time | 2.66 seconds |
| Started | Jan 24 12:43:07 PM PST 24 |
| Finished | Jan 24 12:43:56 PM PST 24 |
| Peak memory | 161504 kb |
| Host | smart-4986a3b8-1e21-41ce-969c-d4389797c976 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1590445839 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_cnsty_chk_test.1590445839 |
| Directory | /workspace/5.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/6.rstmgr_cnsty_chk_test.1110499409 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 9429354000 ps |
| CPU time | 2.69 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:43:52 PM PST 24 |
| Peak memory | 161776 kb |
| Host | smart-545cc605-b0d7-41c4-8ee5-cba9177022fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1110499409 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_cnsty_chk_test.1110499409 |
| Directory | /workspace/6.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/7.rstmgr_cnsty_chk_test.532650196 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 9429368142 ps |
| CPU time | 2.67 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:43:53 PM PST 24 |
| Peak memory | 161520 kb |
| Host | smart-e136838a-0d0d-4505-9c70-4278c0cba8fb |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=532650196 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_cnsty_chk_test.532650196 |
| Directory | /workspace/7.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/8.rstmgr_cnsty_chk_test.320047801 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 9526218814 ps |
| CPU time | 2.7 seconds |
| Started | Jan 24 12:43:11 PM PST 24 |
| Finished | Jan 24 12:44:01 PM PST 24 |
| Peak memory | 161880 kb |
| Host | smart-41976478-10af-465f-97f9-c0e5ab305945 |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=320047801 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_cnsty_chk_test.320047801 |
| Directory | /workspace/8.rstmgr_cnsty_chk_test/latest |
| Test location | /workspace/coverage/default/9.rstmgr_cnsty_chk_test.2677299753 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 9429322064 ps |
| CPU time | 2.7 seconds |
| Started | Jan 24 12:43:05 PM PST 24 |
| Finished | Jan 24 12:43:52 PM PST 24 |
| Peak memory | 161896 kb |
| Host | smart-fdb1c3f7-b138-4f14-8cf0-3d814898367a |
| User | root |
| Command | /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2677299753 -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_cnsty_chk_test.2677299753 |
| Directory | /workspace/9.rstmgr_cnsty_chk_test/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |