Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.86 92.67 78.11 89.36 79.49 82.30 97.75 95.34


Total test records in report: 357
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T142 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1927099135 Jan 24 01:16:07 PM PST 24 Jan 24 01:16:50 PM PST 24 81539047 ps
T272 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.366831492 Jan 24 01:17:41 PM PST 24 Jan 24 01:18:22 PM PST 24 735839236 ps
T273 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3290701231 Jan 24 01:17:50 PM PST 24 Jan 24 01:18:37 PM PST 24 812057396 ps
T274 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2483761712 Jan 24 01:16:25 PM PST 24 Jan 24 01:17:31 PM PST 24 5627202315 ps
T275 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.761771616 Jan 24 01:16:52 PM PST 24 Jan 24 01:17:31 PM PST 24 4153889010 ps
T276 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2333458548 Jan 24 01:17:00 PM PST 24 Jan 24 01:17:37 PM PST 24 223206047 ps
T277 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1983797336 Jan 24 01:16:07 PM PST 24 Jan 24 01:17:21 PM PST 24 15110616248 ps
T82 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2872332019 Jan 24 01:16:25 PM PST 24 Jan 24 01:17:11 PM PST 24 206884170 ps
T80 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1367619608 Jan 24 01:17:29 PM PST 24 Jan 24 01:18:09 PM PST 24 417606188 ps
T138 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2478845719 Jan 24 01:17:05 PM PST 24 Jan 24 01:17:44 PM PST 24 139705181 ps
T81 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2859033611 Jan 24 01:17:46 PM PST 24 Jan 24 01:18:32 PM PST 24 1999590505 ps
T125 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3210848627 Jan 24 01:17:50 PM PST 24 Jan 24 01:18:39 PM PST 24 490924241 ps
T107 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1337834260 Jan 24 01:16:03 PM PST 24 Jan 24 01:16:45 PM PST 24 2168839810 ps
T126 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2531956952 Jan 24 01:17:40 PM PST 24 Jan 24 01:18:24 PM PST 24 261622283 ps
T127 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4261198680 Jan 24 01:17:50 PM PST 24 Jan 24 01:18:36 PM PST 24 2476489163 ps
T128 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4237480430 Jan 24 01:15:53 PM PST 24 Jan 24 01:17:29 PM PST 24 21252416826 ps
T278 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3945805518 Jan 24 01:17:03 PM PST 24 Jan 24 01:17:38 PM PST 24 39198785 ps
T279 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.151642800 Jan 24 01:17:34 PM PST 24 Jan 24 01:18:12 PM PST 24 48240671 ps
T280 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1279466651 Jan 24 01:16:01 PM PST 24 Jan 24 01:17:04 PM PST 24 6300729020 ps
T281 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.249395268 Jan 24 01:16:52 PM PST 24 Jan 24 01:18:19 PM PST 24 1414000917 ps
T282 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1869783674 Jan 24 01:16:07 PM PST 24 Jan 24 01:16:52 PM PST 24 3130523593 ps
T283 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4241671707 Jan 24 01:16:17 PM PST 24 Jan 24 01:17:00 PM PST 24 16985428 ps
T143 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3051428164 Jan 24 01:17:06 PM PST 24 Jan 24 01:17:50 PM PST 24 819266299 ps
T139 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4239432253 Jan 24 01:16:45 PM PST 24 Jan 24 01:18:17 PM PST 24 2846139527 ps
T284 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.193792876 Jan 24 01:17:41 PM PST 24 Jan 24 01:18:21 PM PST 24 59597380 ps
T285 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.824366466 Jan 24 01:16:25 PM PST 24 Jan 24 01:17:09 PM PST 24 23651822 ps
T130 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.137434170 Jan 24 01:17:46 PM PST 24 Jan 24 01:18:29 PM PST 24 1244008033 ps
T286 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3478147129 Jan 24 01:16:00 PM PST 24 Jan 24 01:16:41 PM PST 24 522914762 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2614646206 Jan 24 01:16:11 PM PST 24 Jan 24 01:17:02 PM PST 24 21337846886 ps
T288 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3443661504 Jan 24 01:16:08 PM PST 24 Jan 24 01:16:49 PM PST 24 40583545 ps
T140 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4187871509 Jan 24 01:16:54 PM PST 24 Jan 24 01:17:31 PM PST 24 82936476 ps
T289 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.689113073 Jan 24 01:17:08 PM PST 24 Jan 24 01:17:47 PM PST 24 458485644 ps
T144 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1958075949 Jan 24 01:17:13 PM PST 24 Jan 24 01:17:54 PM PST 24 1271969174 ps
T290 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2107016325 Jan 24 01:15:58 PM PST 24 Jan 24 01:16:41 PM PST 24 165389917 ps
T291 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1425715232 Jan 24 01:16:00 PM PST 24 Jan 24 01:16:41 PM PST 24 185186022 ps
T292 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3467730531 Jan 24 01:15:55 PM PST 24 Jan 24 01:16:37 PM PST 24 36311030 ps
T293 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.881654260 Jan 24 01:17:18 PM PST 24 Jan 24 01:17:57 PM PST 24 147862325 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3258601581 Jan 24 01:16:57 PM PST 24 Jan 24 01:17:36 PM PST 24 2224014578 ps
T295 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.6792758 Jan 24 01:16:04 PM PST 24 Jan 24 01:16:47 PM PST 24 749815138 ps
T296 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.306043923 Jan 24 01:17:32 PM PST 24 Jan 24 01:18:28 PM PST 24 21143570928 ps
T131 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2914372850 Jan 24 01:15:54 PM PST 24 Jan 24 01:16:43 PM PST 24 142350394 ps
T132 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2321468672 Jan 24 01:17:30 PM PST 24 Jan 24 01:18:14 PM PST 24 2723323446 ps
T297 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1390583684 Jan 24 01:17:00 PM PST 24 Jan 24 01:17:36 PM PST 24 129460872 ps
T298 /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.3213504104 Jan 24 01:17:51 PM PST 24 Jan 24 01:18:45 PM PST 24 10664958989 ps
T299 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1865095002 Jan 24 01:17:31 PM PST 24 Jan 24 01:18:18 PM PST 24 1463797273 ps
T300 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3176882682 Jan 24 01:16:53 PM PST 24 Jan 24 01:17:31 PM PST 24 186429640 ps
T301 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3577606135 Jan 24 01:16:53 PM PST 24 Jan 24 01:17:31 PM PST 24 217010522 ps
T302 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.127832837 Jan 24 01:17:29 PM PST 24 Jan 24 01:18:08 PM PST 24 62853665 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.245618435 Jan 24 01:16:10 PM PST 24 Jan 24 01:16:52 PM PST 24 127563478 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2595967679 Jan 24 01:16:06 PM PST 24 Jan 24 01:16:49 PM PST 24 802989172 ps
T304 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2355263279 Jan 24 01:57:13 PM PST 24 Jan 24 01:57:19 PM PST 24 1163434479 ps
T305 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.64929353 Jan 24 01:16:08 PM PST 24 Jan 24 01:16:50 PM PST 24 911616454 ps
T306 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3498324606 Jan 24 01:15:58 PM PST 24 Jan 24 01:16:45 PM PST 24 6406561918 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.58665527 Jan 24 01:16:03 PM PST 24 Jan 24 01:16:42 PM PST 24 31566078 ps
T308 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3647534061 Jan 24 01:17:19 PM PST 24 Jan 24 01:18:02 PM PST 24 270346770 ps
T309 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3028758250 Jan 24 01:15:53 PM PST 24 Jan 24 01:16:36 PM PST 24 682741499 ps
T133 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1328183151 Jan 24 01:16:59 PM PST 24 Jan 24 01:17:39 PM PST 24 272269924 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3551699139 Jan 24 01:17:46 PM PST 24 Jan 24 01:18:27 PM PST 24 32670334 ps
T311 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1787817455 Jan 24 01:16:51 PM PST 24 Jan 24 01:17:26 PM PST 24 57685733 ps
T312 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.142438310 Jan 24 01:17:41 PM PST 24 Jan 24 01:18:26 PM PST 24 779218011 ps
T313 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.805830994 Jan 24 01:16:05 PM PST 24 Jan 24 01:16:44 PM PST 24 471522520 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2521061218 Jan 24 01:39:25 PM PST 24 Jan 24 01:39:44 PM PST 24 32761241 ps
T109 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.246865593 Jan 24 01:16:52 PM PST 24 Jan 24 01:17:30 PM PST 24 1028433302 ps
T315 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2150023638 Jan 24 01:16:54 PM PST 24 Jan 24 01:17:30 PM PST 24 202381291 ps
T316 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4155473863 Jan 24 01:17:31 PM PST 24 Jan 24 01:18:10 PM PST 24 89717593 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4149042118 Jan 24 01:15:59 PM PST 24 Jan 24 01:16:40 PM PST 24 53265126 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3762239246 Jan 24 01:16:27 PM PST 24 Jan 24 01:17:11 PM PST 24 81195219 ps
T319 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2645038969 Jan 24 01:17:29 PM PST 24 Jan 24 01:18:08 PM PST 24 60698611 ps
T320 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1968908174 Jan 24 01:17:46 PM PST 24 Jan 24 01:18:34 PM PST 24 652233579 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3429582220 Jan 24 01:16:47 PM PST 24 Jan 24 01:17:31 PM PST 24 1061656574 ps
T322 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2760138558 Jan 24 01:17:32 PM PST 24 Jan 24 01:18:11 PM PST 24 184933120 ps
T323 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.205957739 Jan 24 01:17:32 PM PST 24 Jan 24 01:18:11 PM PST 24 45980645 ps
T324 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2636383576 Jan 24 01:16:52 PM PST 24 Jan 24 01:17:29 PM PST 24 60603635 ps
T325 /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.500381129 Jan 24 01:16:51 PM PST 24 Jan 24 01:17:42 PM PST 24 4966402811 ps
T326 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1455136845 Jan 24 01:16:57 PM PST 24 Jan 24 01:17:42 PM PST 24 769426057 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2180700925 Jan 24 01:56:01 PM PST 24 Jan 24 01:56:11 PM PST 24 2431499256 ps
T328 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2150092254 Jan 24 02:30:26 PM PST 24 Jan 24 02:31:04 PM PST 24 47351504063 ps
T329 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3530737745 Jan 24 01:16:51 PM PST 24 Jan 24 01:17:47 PM PST 24 3868952786 ps
T330 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2874256021 Jan 24 01:17:54 PM PST 24 Jan 24 01:18:45 PM PST 24 1933583001 ps
T331 /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.792307512 Jan 24 01:17:40 PM PST 24 Jan 24 01:18:23 PM PST 24 374538115 ps
T332 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4035455568 Jan 24 01:25:26 PM PST 24 Jan 24 01:26:21 PM PST 24 79655395 ps
T333 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1095828293 Jan 24 01:17:19 PM PST 24 Jan 24 01:18:00 PM PST 24 80397714 ps
T334 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2136382551 Jan 24 01:16:53 PM PST 24 Jan 24 01:17:29 PM PST 24 114327642 ps
T335 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.816319024 Jan 24 01:16:12 PM PST 24 Jan 24 01:16:54 PM PST 24 215369486 ps
T336 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1073572888 Jan 24 01:17:01 PM PST 24 Jan 24 01:17:38 PM PST 24 192312129 ps
T337 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3469191591 Jan 24 01:15:59 PM PST 24 Jan 24 01:16:40 PM PST 24 124124529 ps
T338 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3726113822 Jan 24 01:16:54 PM PST 24 Jan 24 01:17:30 PM PST 24 66141357 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3647112065 Jan 24 01:16:00 PM PST 24 Jan 24 01:16:41 PM PST 24 191583116 ps
T340 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3483774285 Jan 24 01:16:08 PM PST 24 Jan 24 01:17:24 PM PST 24 2493404756 ps
T341 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1110501734 Jan 24 01:17:19 PM PST 24 Jan 24 01:17:59 PM PST 24 60847988 ps
T342 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1149170423 Jan 24 01:16:49 PM PST 24 Jan 24 01:17:25 PM PST 24 60195357 ps
T343 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2148755188 Jan 24 01:17:10 PM PST 24 Jan 24 01:17:49 PM PST 24 362911944 ps
T344 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1783240529 Jan 24 01:16:52 PM PST 24 Jan 24 01:17:28 PM PST 24 29582243 ps
T345 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.794597218 Jan 24 03:02:12 PM PST 24 Jan 24 03:02:19 PM PST 24 144219809 ps
T346 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1020850419 Jan 24 01:16:27 PM PST 24 Jan 24 01:17:10 PM PST 24 399337367 ps
T347 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.639258966 Jan 24 01:16:04 PM PST 24 Jan 24 01:17:02 PM PST 24 8082446388 ps
T348 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2577660662 Jan 24 01:17:31 PM PST 24 Jan 24 01:18:14 PM PST 24 399232708 ps
T349 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3619520876 Jan 24 01:16:53 PM PST 24 Jan 24 01:18:09 PM PST 24 12206775937 ps
T149 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.333995313 Jan 24 01:17:15 PM PST 24 Jan 24 01:18:08 PM PST 24 3732595724 ps
T350 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1839492440 Jan 24 01:17:41 PM PST 24 Jan 24 01:18:25 PM PST 24 538922965 ps
T351 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3616705512 Jan 24 01:15:59 PM PST 24 Jan 24 01:16:45 PM PST 24 3233311435 ps
T352 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3435217564 Jan 24 01:17:32 PM PST 24 Jan 24 01:18:10 PM PST 24 236489940 ps
T353 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2526988735 Jan 24 01:17:34 PM PST 24 Jan 24 01:18:17 PM PST 24 277889741 ps
T354 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2887668101 Jan 24 01:22:48 PM PST 24 Jan 24 01:23:45 PM PST 24 19625389 ps
T355 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3936651100 Jan 24 01:17:29 PM PST 24 Jan 24 01:18:09 PM PST 24 1527760297 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2418395310 Jan 24 01:16:07 PM PST 24 Jan 24 01:16:49 PM PST 24 54453802 ps
T357 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3901173787 Jan 24 01:16:52 PM PST 24 Jan 24 01:17:39 PM PST 24 4825738824 ps

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.2853873666
Short name T29
Test name
Test status
Simulation time 3737811691 ps
CPU time 12.45 seconds
Started Jan 24 01:19:02 PM PST 24
Finished Jan 24 01:20:10 PM PST 24
Peak memory 202960 kb
Host smart-0dd4a0be-a598-4ff3-b99c-b52790ac9865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853873666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.2853873666
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_stress_all.2099155140
Short name T5
Test name
Test status
Simulation time 2396594323 ps
CPU time 6.72 seconds
Started Jan 24 01:19:51 PM PST 24
Finished Jan 24 01:20:59 PM PST 24
Peak memory 203856 kb
Host smart-eb1aa9af-8de2-4dc4-881d-e3405a7cbd53
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099155140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_stress_all.2099155140
Directory /workspace/18.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.801463136
Short name T46
Test name
Test status
Simulation time 4034450865 ps
CPU time 4.58 seconds
Started Jan 24 01:16:54 PM PST 24
Finished Jan 24 01:17:34 PM PST 24
Peak memory 219912 kb
Host smart-4491fbbe-93df-48d7-acc2-9b205437fd10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801463136 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.801463136
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/29.rv_dm_tap_fsm_rand_reset.3067795313
Short name T90
Test name
Test status
Simulation time 5979332617 ps
CPU time 14.3 seconds
Started Jan 24 01:18:08 PM PST 24
Finished Jan 24 01:19:13 PM PST 24
Peak memory 211972 kb
Host smart-7df4548e-53f7-473d-bcde-bb5381dd84de
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067795313 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 29.rv_dm_tap_fsm_rand_reset.3067795313
Directory /workspace/29.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3780738659
Short name T48
Test name
Test status
Simulation time 19207060 ps
CPU time 0.67 seconds
Started Jan 24 03:35:49 PM PST 24
Finished Jan 24 03:35:53 PM PST 24
Peak memory 203632 kb
Host smart-3fc76c04-2b64-4b73-b933-462875b7affa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780738659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3780738659
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.2584938692
Short name T4
Test name
Test status
Simulation time 1537180131 ps
CPU time 3.6 seconds
Started Jan 24 01:18:27 PM PST 24
Finished Jan 24 01:19:11 PM PST 24
Peak memory 203808 kb
Host smart-15a2ec7d-e2ea-4715-ab53-90e5b0a7aa7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584938692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.2584938692
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2190572693
Short name T39
Test name
Test status
Simulation time 5920313059 ps
CPU time 19.28 seconds
Started Jan 24 01:59:18 PM PST 24
Finished Jan 24 01:59:39 PM PST 24
Peak memory 215888 kb
Host smart-464f05c7-6620-4e6f-8233-47c622e07872
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190572693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2190572693
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.394138255
Short name T105
Test name
Test status
Simulation time 243817309 ps
CPU time 5.18 seconds
Started Jan 24 01:16:23 PM PST 24
Finished Jan 24 01:17:11 PM PST 24
Peak memory 211948 kb
Host smart-903feafe-0dff-41d1-a141-3c963ae27378
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394138255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.394138255
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.2141467796
Short name T31
Test name
Test status
Simulation time 329757428 ps
CPU time 0.96 seconds
Started Jan 24 01:18:27 PM PST 24
Finished Jan 24 01:19:08 PM PST 24
Peak memory 203244 kb
Host smart-22251291-2493-4b0b-b467-ac9ee992dc12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141467796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.2141467796
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.2712111357
Short name T15
Test name
Test status
Simulation time 7772039702 ps
CPU time 13.75 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:54 PM PST 24
Peak memory 204056 kb
Host smart-3c2b2df6-2b7b-4bf1-9f20-66686497ad55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712111357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.2712111357
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2847066830
Short name T45
Test name
Test status
Simulation time 18125227509 ps
CPU time 30.38 seconds
Started Jan 24 02:08:46 PM PST 24
Finished Jan 24 02:09:34 PM PST 24
Peak memory 203672 kb
Host smart-c20a751b-1064-45a1-9076-6692170d4a13
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847066830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2847066830
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2098535470
Short name T30
Test name
Test status
Simulation time 1520592062 ps
CPU time 3.36 seconds
Started Jan 24 01:18:13 PM PST 24
Finished Jan 24 01:19:04 PM PST 24
Peak memory 203712 kb
Host smart-36da6753-8998-4535-93da-60a37c8cf3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098535470 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2098535470
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1367619608
Short name T80
Test name
Test status
Simulation time 417606188 ps
CPU time 2.67 seconds
Started Jan 24 01:17:29 PM PST 24
Finished Jan 24 01:18:09 PM PST 24
Peak memory 219396 kb
Host smart-a973fea8-9374-47b9-a935-21731de41c3f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367619608 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1367619608
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.2859033611
Short name T81
Test name
Test status
Simulation time 1999590505 ps
CPU time 6.33 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:32 PM PST 24
Peak memory 213620 kb
Host smart-d8aebe6d-6a35-40c4-a90f-45b81d18fcf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859033611 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.2859033611
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.2872332019
Short name T82
Test name
Test status
Simulation time 206884170 ps
CPU time 2.81 seconds
Started Jan 24 01:16:25 PM PST 24
Finished Jan 24 01:17:11 PM PST 24
Peak memory 219164 kb
Host smart-66100f5f-7ce4-4411-bd28-bfa08dc06b0f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872332019 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.2872332019
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.3424692054
Short name T116
Test name
Test status
Simulation time 2085011323 ps
CPU time 9.48 seconds
Started Jan 24 01:17:10 PM PST 24
Finished Jan 24 01:17:56 PM PST 24
Peak memory 212020 kb
Host smart-df108c5f-4371-445e-9b83-633e42a95648
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424692054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.3
424692054
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.561395368
Short name T13
Test name
Test status
Simulation time 319551250 ps
CPU time 1.28 seconds
Started Jan 24 02:32:37 PM PST 24
Finished Jan 24 02:33:09 PM PST 24
Peak memory 203632 kb
Host smart-83661f3d-069c-49fe-94a8-e8b09190d49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561395368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.561395368
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2988390771
Short name T72
Test name
Test status
Simulation time 217970695 ps
CPU time 1.24 seconds
Started Jan 24 01:18:31 PM PST 24
Finished Jan 24 01:19:11 PM PST 24
Peak memory 219864 kb
Host smart-49827f4f-1ed4-48f7-824e-8c53ec0b6ffa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988390771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2988390771
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3512326128
Short name T64
Test name
Test status
Simulation time 49519033 ps
CPU time 0.75 seconds
Started Jan 24 01:15:55 PM PST 24
Finished Jan 24 01:16:37 PM PST 24
Peak memory 203516 kb
Host smart-bf9da852-ec42-433a-b00f-640e27b5ff69
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512326128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3512326128
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3533117901
Short name T104
Test name
Test status
Simulation time 1915711858 ps
CPU time 18.71 seconds
Started Jan 24 01:17:30 PM PST 24
Finished Jan 24 01:18:26 PM PST 24
Peak memory 215096 kb
Host smart-de6237df-bb45-4b4a-b2ac-ff573e919c33
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533117901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
533117901
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1000920810
Short name T85
Test name
Test status
Simulation time 21356155 ps
CPU time 0.7 seconds
Started Jan 24 01:38:27 PM PST 24
Finished Jan 24 01:38:51 PM PST 24
Peak memory 203616 kb
Host smart-fbb5efbc-65af-474a-82d1-9bdd29bd6ac7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000920810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1000920810
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1810930884
Short name T258
Test name
Test status
Simulation time 3854961315 ps
CPU time 5.24 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:24 PM PST 24
Peak memory 215924 kb
Host smart-08d20da8-e5e9-4ee7-894b-8fb40f21afce
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810930884 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1810930884
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3210848627
Short name T125
Test name
Test status
Simulation time 490924241 ps
CPU time 3.98 seconds
Started Jan 24 01:17:50 PM PST 24
Finished Jan 24 01:18:39 PM PST 24
Peak memory 203684 kb
Host smart-0e39c8ef-dc58-4c00-b151-26d187178c11
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210848627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3210848627
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3125849751
Short name T67
Test name
Test status
Simulation time 219921673 ps
CPU time 0.63 seconds
Started Jan 24 01:21:04 PM PST 24
Finished Jan 24 01:22:12 PM PST 24
Peak memory 203360 kb
Host smart-3c909e7e-adc5-482e-9962-ec2855dd5b5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125849751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3125849751
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.323078754
Short name T1
Test name
Test status
Simulation time 301732977 ps
CPU time 0.92 seconds
Started Jan 24 01:18:29 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 203612 kb
Host smart-3f619e82-0163-4cb1-8a64-ca67affbafba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323078754 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.323078754
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2937875839
Short name T40
Test name
Test status
Simulation time 477568332 ps
CPU time 7.91 seconds
Started Jan 24 01:17:06 PM PST 24
Finished Jan 24 01:17:51 PM PST 24
Peak memory 211876 kb
Host smart-0e64c383-55cb-4746-8597-0a09ec386a8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937875839 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2937875839
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1337834260
Short name T107
Test name
Test status
Simulation time 2168839810 ps
CPU time 4.09 seconds
Started Jan 24 01:16:03 PM PST 24
Finished Jan 24 01:16:45 PM PST 24
Peak memory 203552 kb
Host smart-cf9c1b08-962e-470c-aaaa-ebdea6dfc930
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337834260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1337834260
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.2942206992
Short name T26
Test name
Test status
Simulation time 343772144 ps
CPU time 1.15 seconds
Started Jan 24 01:36:08 PM PST 24
Finished Jan 24 01:36:42 PM PST 24
Peak memory 203192 kb
Host smart-305afc7e-ca32-4a09-a4b6-0fcf79a44972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942206992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.2942206992
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.217604507
Short name T136
Test name
Test status
Simulation time 4312777683 ps
CPU time 68.32 seconds
Started Jan 24 01:15:58 PM PST 24
Finished Jan 24 01:17:47 PM PST 24
Peak memory 203752 kb
Host smart-ba0420ad-eedb-4bc0-8f8d-eaa2532add46
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217604507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 1.rv_dm_csr_aliasing.217604507
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.413272620
Short name T252
Test name
Test status
Simulation time 1173028215 ps
CPU time 28.05 seconds
Started Jan 24 01:15:57 PM PST 24
Finished Jan 24 01:17:06 PM PST 24
Peak memory 203708 kb
Host smart-21e107cf-628f-4c22-95fe-ba619285c827
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413272620 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 0.rv_dm_csr_aliasing.413272620
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2790997458
Short name T166
Test name
Test status
Simulation time 2811375721 ps
CPU time 27.73 seconds
Started Jan 24 01:32:34 PM PST 24
Finished Jan 24 01:33:38 PM PST 24
Peak memory 203744 kb
Host smart-6fcca98b-a62c-4b21-ac1a-5c0fae40a097
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790997458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2790997458
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3647112065
Short name T339
Test name
Test status
Simulation time 191583116 ps
CPU time 1.51 seconds
Started Jan 24 01:16:00 PM PST 24
Finished Jan 24 01:16:41 PM PST 24
Peak memory 203556 kb
Host smart-9467b0ad-c148-4be5-9919-dade170d1b0c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647112065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3647112065
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2107016325
Short name T290
Test name
Test status
Simulation time 165389917 ps
CPU time 2.26 seconds
Started Jan 24 01:15:58 PM PST 24
Finished Jan 24 01:16:41 PM PST 24
Peak memory 203520 kb
Host smart-106062d5-5266-4162-a104-168dd13de531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107016325 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2107016325
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3498324606
Short name T306
Test name
Test status
Simulation time 6406561918 ps
CPU time 6.66 seconds
Started Jan 24 01:15:58 PM PST 24
Finished Jan 24 01:16:45 PM PST 24
Peak memory 203520 kb
Host smart-f85b09c5-2ff0-4d30-8172-20c597105419
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498324606 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3498324606
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4237480430
Short name T128
Test name
Test status
Simulation time 21252416826 ps
CPU time 53.2 seconds
Started Jan 24 01:15:53 PM PST 24
Finished Jan 24 01:17:29 PM PST 24
Peak memory 203684 kb
Host smart-0257042d-62f4-434d-8596-2d1f739760b8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237480430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.4237480430
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.762098959
Short name T239
Test name
Test status
Simulation time 967337733 ps
CPU time 1.37 seconds
Started Jan 24 01:15:54 PM PST 24
Finished Jan 24 01:16:37 PM PST 24
Peak memory 203624 kb
Host smart-05097597-e577-4479-ac02-bcae44854bdb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762098959 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.762098959
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3028758250
Short name T309
Test name
Test status
Simulation time 682741499 ps
CPU time 1.5 seconds
Started Jan 24 01:15:53 PM PST 24
Finished Jan 24 01:16:36 PM PST 24
Peak memory 203576 kb
Host smart-767978ab-592f-4e4b-9ca8-a58f10c3d5dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028758250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
028758250
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.2071209079
Short name T248
Test name
Test status
Simulation time 154243342 ps
CPU time 1.07 seconds
Started Jan 24 01:16:00 PM PST 24
Finished Jan 24 01:16:41 PM PST 24
Peak memory 203328 kb
Host smart-4b869da7-2d29-425a-8e08-372497a6b101
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071209079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.2071209079
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3478147129
Short name T286
Test name
Test status
Simulation time 522914762 ps
CPU time 1.39 seconds
Started Jan 24 01:16:00 PM PST 24
Finished Jan 24 01:16:41 PM PST 24
Peak memory 203412 kb
Host smart-e0b45bd5-b451-4d34-8014-b1c6cf007fa0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478147129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3478147129
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.822063311
Short name T243
Test name
Test status
Simulation time 153845214 ps
CPU time 0.79 seconds
Started Jan 24 01:15:54 PM PST 24
Finished Jan 24 01:16:37 PM PST 24
Peak memory 203484 kb
Host smart-752d6412-e7b1-45c7-a142-2025c0d2f0f7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822063311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.822063311
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2028200716
Short name T118
Test name
Test status
Simulation time 24924261 ps
CPU time 0.63 seconds
Started Jan 24 02:56:40 PM PST 24
Finished Jan 24 02:56:42 PM PST 24
Peak memory 203480 kb
Host smart-ff026f24-5f53-4ad8-839b-b8cffecf6674
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028200716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2028200716
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3467730531
Short name T292
Test name
Test status
Simulation time 36311030 ps
CPU time 0.63 seconds
Started Jan 24 01:15:55 PM PST 24
Finished Jan 24 01:16:37 PM PST 24
Peak memory 203516 kb
Host smart-921fda33-8f70-4b9c-9061-26e941fdeda0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467730531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3467730531
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2914372850
Short name T131
Test name
Test status
Simulation time 142350394 ps
CPU time 6.32 seconds
Started Jan 24 01:15:54 PM PST 24
Finished Jan 24 01:16:43 PM PST 24
Peak memory 203688 kb
Host smart-b566320c-c4ba-464e-abed-0a0448e8509f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914372850 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2914372850
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2521061218
Short name T314
Test name
Test status
Simulation time 32761241 ps
CPU time 2.05 seconds
Started Jan 24 01:39:25 PM PST 24
Finished Jan 24 01:39:44 PM PST 24
Peak memory 211968 kb
Host smart-50a49848-951e-433a-83ed-8c0bf042aa58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521061218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2521061218
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.714787720
Short name T151
Test name
Test status
Simulation time 664906543 ps
CPU time 16.77 seconds
Started Jan 24 01:15:55 PM PST 24
Finished Jan 24 01:16:53 PM PST 24
Peak memory 211952 kb
Host smart-c4224e68-a0af-48eb-b021-92adda0eac72
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=714787720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.714787720
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3483774285
Short name T340
Test name
Test status
Simulation time 2493404756 ps
CPU time 34.44 seconds
Started Jan 24 01:16:08 PM PST 24
Finished Jan 24 01:17:24 PM PST 24
Peak memory 203708 kb
Host smart-d1b07e57-c583-4b07-a5fe-fd08da33ee42
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483774285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3483774285
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2881954849
Short name T241
Test name
Test status
Simulation time 67443024 ps
CPU time 1.55 seconds
Started Jan 24 01:16:04 PM PST 24
Finished Jan 24 01:16:44 PM PST 24
Peak memory 203580 kb
Host smart-bc1e9855-eaa7-41e9-9f9d-812374d26431
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881954849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2881954849
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.64929353
Short name T305
Test name
Test status
Simulation time 911616454 ps
CPU time 2.38 seconds
Started Jan 24 01:16:08 PM PST 24
Finished Jan 24 01:16:50 PM PST 24
Peak memory 212088 kb
Host smart-bb954b33-3e5e-4878-9559-600a4a98535e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64929353 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.64929353
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2418395310
Short name T356
Test name
Test status
Simulation time 54453802 ps
CPU time 1.42 seconds
Started Jan 24 01:16:07 PM PST 24
Finished Jan 24 01:16:49 PM PST 24
Peak memory 203636 kb
Host smart-f3ad18f7-330d-4575-8095-f391f312bbe6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418395310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2418395310
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.3616705512
Short name T351
Test name
Test status
Simulation time 3233311435 ps
CPU time 6.31 seconds
Started Jan 24 01:15:59 PM PST 24
Finished Jan 24 01:16:45 PM PST 24
Peak memory 203392 kb
Host smart-a2e5a963-6c01-4240-a739-2f0056445042
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616705512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.3616705512
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.1279466651
Short name T280
Test name
Test status
Simulation time 6300729020 ps
CPU time 24.29 seconds
Started Jan 24 01:16:01 PM PST 24
Finished Jan 24 01:17:04 PM PST 24
Peak memory 203520 kb
Host smart-76b46c66-62f9-4423-99dc-ec897626f508
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279466651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.1279466651
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3469191591
Short name T337
Test name
Test status
Simulation time 124124529 ps
CPU time 0.91 seconds
Started Jan 24 01:15:59 PM PST 24
Finished Jan 24 01:16:40 PM PST 24
Peak memory 203340 kb
Host smart-38888673-bf89-454c-9d55-d9e4b7670903
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469191591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
469191591
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1425715232
Short name T291
Test name
Test status
Simulation time 185186022 ps
CPU time 0.83 seconds
Started Jan 24 01:16:00 PM PST 24
Finished Jan 24 01:16:41 PM PST 24
Peak memory 203320 kb
Host smart-21d991ca-2aff-453f-8ea0-35922f1727e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425715232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1425715232
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2180700925
Short name T327
Test name
Test status
Simulation time 2431499256 ps
CPU time 6.39 seconds
Started Jan 24 01:56:01 PM PST 24
Finished Jan 24 01:56:11 PM PST 24
Peak memory 203656 kb
Host smart-9fab06ec-513b-4d81-bbdb-144e57d14e41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180700925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2180700925
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4149042118
Short name T317
Test name
Test status
Simulation time 53265126 ps
CPU time 0.68 seconds
Started Jan 24 01:15:59 PM PST 24
Finished Jan 24 01:16:40 PM PST 24
Peak memory 203320 kb
Host smart-4a43e308-4a23-4ebf-8a9c-50e9222ec677
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149042118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4149042118
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4097362234
Short name T110
Test name
Test status
Simulation time 140479197 ps
CPU time 0.79 seconds
Started Jan 24 01:15:55 PM PST 24
Finished Jan 24 01:16:37 PM PST 24
Peak memory 203536 kb
Host smart-5ed7bd3c-d672-4ce8-83f5-36534de5cceb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097362234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
097362234
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.58665527
Short name T307
Test name
Test status
Simulation time 31566078 ps
CPU time 0.63 seconds
Started Jan 24 01:16:03 PM PST 24
Finished Jan 24 01:16:42 PM PST 24
Peak memory 203408 kb
Host smart-cfb8da6e-1988-4fa3-af36-7bc1edf648ff
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58665527 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_parti
al_access.58665527
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4241671707
Short name T283
Test name
Test status
Simulation time 16985428 ps
CPU time 0.62 seconds
Started Jan 24 01:16:17 PM PST 24
Finished Jan 24 01:17:00 PM PST 24
Peak memory 203500 kb
Host smart-1e13ddf3-3285-4d1a-9bba-51ff153664a7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241671707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4241671707
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1927099135
Short name T142
Test name
Test status
Simulation time 81539047 ps
CPU time 3.4 seconds
Started Jan 24 01:16:07 PM PST 24
Finished Jan 24 01:16:50 PM PST 24
Peak memory 203644 kb
Host smart-4e3ba67f-c805-48ec-9862-14137a58d2ca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927099135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1927099135
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.6792758
Short name T295
Test name
Test status
Simulation time 749815138 ps
CPU time 4.83 seconds
Started Jan 24 01:16:04 PM PST 24
Finished Jan 24 01:16:47 PM PST 24
Peak memory 211920 kb
Host smart-49b52c0e-66f2-4560-a4ef-cf1d7b7be007
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6792758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.6792758
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.615829654
Short name T92
Test name
Test status
Simulation time 948574180 ps
CPU time 16.06 seconds
Started Jan 24 01:16:09 PM PST 24
Finished Jan 24 01:17:05 PM PST 24
Peak memory 211840 kb
Host smart-abd07863-6ec9-476f-b79b-81718d61615a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615829654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.615829654
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.181405716
Short name T262
Test name
Test status
Simulation time 1869327274 ps
CPU time 3.26 seconds
Started Jan 24 01:17:19 PM PST 24
Finished Jan 24 01:18:00 PM PST 24
Peak memory 214184 kb
Host smart-48fa1067-4fcb-4836-84bf-23e17e831510
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181405716 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.181405716
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.657610854
Short name T135
Test name
Test status
Simulation time 117412778 ps
CPU time 2.43 seconds
Started Jan 24 01:17:09 PM PST 24
Finished Jan 24 01:17:49 PM PST 24
Peak memory 203624 kb
Host smart-3139bc20-ea26-4cca-943e-bd721395b0db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657610854 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.657610854
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.689113073
Short name T289
Test name
Test status
Simulation time 458485644 ps
CPU time 2.27 seconds
Started Jan 24 01:17:08 PM PST 24
Finished Jan 24 01:17:47 PM PST 24
Peak memory 203560 kb
Host smart-e802c503-15af-4676-803f-886bb786fd1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689113073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.689113073
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3945805518
Short name T278
Test name
Test status
Simulation time 39198785 ps
CPU time 0.66 seconds
Started Jan 24 01:17:03 PM PST 24
Finished Jan 24 01:17:38 PM PST 24
Peak memory 203508 kb
Host smart-7a12fd34-4c56-464a-81d4-3a84795b0988
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945805518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3945805518
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.3647534061
Short name T308
Test name
Test status
Simulation time 270346770 ps
CPU time 4.15 seconds
Started Jan 24 01:17:19 PM PST 24
Finished Jan 24 01:18:02 PM PST 24
Peak memory 203644 kb
Host smart-1cd433dc-20e5-4acd-82a3-fce07b93e8f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647534061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.3647534061
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1110501734
Short name T341
Test name
Test status
Simulation time 60847988 ps
CPU time 1.85 seconds
Started Jan 24 01:17:19 PM PST 24
Finished Jan 24 01:17:59 PM PST 24
Peak memory 203660 kb
Host smart-4fc127f9-e748-4ad2-b7e9-4e3b71b7c807
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110501734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1110501734
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.333995313
Short name T149
Test name
Test status
Simulation time 3732595724 ps
CPU time 17.37 seconds
Started Jan 24 01:17:15 PM PST 24
Finished Jan 24 01:18:08 PM PST 24
Peak memory 213728 kb
Host smart-e113e056-7a7a-456b-9b67-495057135107
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333995313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.333995313
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.1455598416
Short name T261
Test name
Test status
Simulation time 1412072009 ps
CPU time 3.14 seconds
Started Jan 24 01:17:26 PM PST 24
Finished Jan 24 01:18:07 PM PST 24
Peak memory 213284 kb
Host smart-de436dce-0bf3-4a04-bbae-b7b63ec10ed7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455598416 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.1455598416
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2148755188
Short name T343
Test name
Test status
Simulation time 362911944 ps
CPU time 2.28 seconds
Started Jan 24 01:17:10 PM PST 24
Finished Jan 24 01:17:49 PM PST 24
Peak memory 203584 kb
Host smart-bf658852-01a7-490a-afbb-f528e97cd98e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148755188 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2148755188
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4193841903
Short name T62
Test name
Test status
Simulation time 283775527 ps
CPU time 1.17 seconds
Started Jan 24 01:17:18 PM PST 24
Finished Jan 24 01:17:58 PM PST 24
Peak memory 203356 kb
Host smart-be17791e-f4a9-47b2-9685-09fd69311524
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193841903 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4193841903
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.881654260
Short name T293
Test name
Test status
Simulation time 147862325 ps
CPU time 0.99 seconds
Started Jan 24 01:17:18 PM PST 24
Finished Jan 24 01:17:57 PM PST 24
Peak memory 203276 kb
Host smart-f2a64a16-ce42-4241-8d6f-bf237f772677
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881654260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.881654260
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.1958075949
Short name T144
Test name
Test status
Simulation time 1271969174 ps
CPU time 4.34 seconds
Started Jan 24 01:17:13 PM PST 24
Finished Jan 24 01:17:54 PM PST 24
Peak memory 203684 kb
Host smart-cb159263-efdb-4656-86d2-c0825131cd18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958075949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.1958075949
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.1095828293
Short name T333
Test name
Test status
Simulation time 80397714 ps
CPU time 2.43 seconds
Started Jan 24 01:17:19 PM PST 24
Finished Jan 24 01:18:00 PM PST 24
Peak memory 204044 kb
Host smart-eef2a6b3-b874-4db8-9eab-e0a9ad83474c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095828293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.1095828293
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.2760138558
Short name T322
Test name
Test status
Simulation time 184933120 ps
CPU time 1.53 seconds
Started Jan 24 01:17:32 PM PST 24
Finished Jan 24 01:18:11 PM PST 24
Peak memory 203624 kb
Host smart-d8622ab1-1bf9-4ae5-9b04-bf97315b64b9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760138558 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.2760138558
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.3936651100
Short name T355
Test name
Test status
Simulation time 1527760297 ps
CPU time 2.22 seconds
Started Jan 24 01:17:29 PM PST 24
Finished Jan 24 01:18:09 PM PST 24
Peak memory 203496 kb
Host smart-b2dca268-9770-44e8-876b-eb6c3bc6d902
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936651100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
3936651100
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.2645038969
Short name T319
Test name
Test status
Simulation time 60698611 ps
CPU time 0.75 seconds
Started Jan 24 01:17:29 PM PST 24
Finished Jan 24 01:18:08 PM PST 24
Peak memory 203420 kb
Host smart-93abd8ab-1d6f-4b48-9873-b5370015a43e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645038969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
2645038969
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3404864304
Short name T101
Test name
Test status
Simulation time 764261448 ps
CPU time 3.84 seconds
Started Jan 24 01:17:26 PM PST 24
Finished Jan 24 01:18:08 PM PST 24
Peak memory 203568 kb
Host smart-5bac9fc5-8a3f-4178-9875-6f63c4604962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404864304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3404864304
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2577660662
Short name T348
Test name
Test status
Simulation time 399232708 ps
CPU time 5.6 seconds
Started Jan 24 01:17:31 PM PST 24
Finished Jan 24 01:18:14 PM PST 24
Peak memory 211904 kb
Host smart-d75d84c7-d790-4f62-a00b-b1469bf9e4c2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577660662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2577660662
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1865095002
Short name T299
Test name
Test status
Simulation time 1463797273 ps
CPU time 9.39 seconds
Started Jan 24 01:17:31 PM PST 24
Finished Jan 24 01:18:18 PM PST 24
Peak memory 212052 kb
Host smart-75705e24-c943-4415-9813-ed4447ce5d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865095002 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
865095002
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4155473863
Short name T316
Test name
Test status
Simulation time 89717593 ps
CPU time 1.91 seconds
Started Jan 24 01:17:31 PM PST 24
Finished Jan 24 01:18:10 PM PST 24
Peak memory 214104 kb
Host smart-9524a609-98e7-4f1f-b2b6-42fa57ed2eb2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155473863 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4155473863
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.127832837
Short name T302
Test name
Test status
Simulation time 62853665 ps
CPU time 1.35 seconds
Started Jan 24 01:17:29 PM PST 24
Finished Jan 24 01:18:08 PM PST 24
Peak memory 203544 kb
Host smart-a48abf4e-9c98-4d2a-90b2-9cfb0e002bac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127832837 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.127832837
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3435217564
Short name T352
Test name
Test status
Simulation time 236489940 ps
CPU time 1.26 seconds
Started Jan 24 01:17:32 PM PST 24
Finished Jan 24 01:18:10 PM PST 24
Peak memory 203592 kb
Host smart-9adb922f-eaae-4e25-8652-dc9d8dbb7a6b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435217564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3435217564
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.151642800
Short name T279
Test name
Test status
Simulation time 48240671 ps
CPU time 0.76 seconds
Started Jan 24 01:17:34 PM PST 24
Finished Jan 24 01:18:12 PM PST 24
Peak memory 203508 kb
Host smart-d4c765d4-7513-46f1-9e3a-6c29b6a5af58
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151642800 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.151642800
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2321468672
Short name T132
Test name
Test status
Simulation time 2723323446 ps
CPU time 6.26 seconds
Started Jan 24 01:17:30 PM PST 24
Finished Jan 24 01:18:14 PM PST 24
Peak memory 203804 kb
Host smart-5ccd8ed8-b445-4d2f-9b82-8d154ad3b94c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321468672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2321468672
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3598872186
Short name T115
Test name
Test status
Simulation time 10824059838 ps
CPU time 20.08 seconds
Started Jan 24 01:17:26 PM PST 24
Finished Jan 24 01:18:25 PM PST 24
Peak memory 220148 kb
Host smart-c7871605-a495-4d94-986a-1fb5b96d524b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598872186 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3598872186
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.321883897
Short name T246
Test name
Test status
Simulation time 55713382 ps
CPU time 3.41 seconds
Started Jan 24 01:17:30 PM PST 24
Finished Jan 24 01:18:11 PM PST 24
Peak memory 211924 kb
Host smart-63f64260-c32e-4785-a4cc-c07552e8a732
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=321883897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.321883897
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.205957739
Short name T323
Test name
Test status
Simulation time 45980645 ps
CPU time 1.43 seconds
Started Jan 24 01:17:32 PM PST 24
Finished Jan 24 01:18:11 PM PST 24
Peak memory 211836 kb
Host smart-d28f117c-1f04-4e6d-8190-9818323cc245
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205957739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.205957739
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.4209430857
Short name T247
Test name
Test status
Simulation time 262969386 ps
CPU time 1.18 seconds
Started Jan 24 01:17:34 PM PST 24
Finished Jan 24 01:18:12 PM PST 24
Peak memory 203640 kb
Host smart-0a43e0bf-3448-4aeb-9413-637a35392e3e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209430857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
4209430857
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.1942903591
Short name T238
Test name
Test status
Simulation time 40496377 ps
CPU time 0.65 seconds
Started Jan 24 01:17:27 PM PST 24
Finished Jan 24 01:18:06 PM PST 24
Peak memory 203520 kb
Host smart-5028860f-75c5-4a2c-a731-f024bab3e12f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942903591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
1942903591
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.142438310
Short name T312
Test name
Test status
Simulation time 779218011 ps
CPU time 6.81 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:26 PM PST 24
Peak memory 203540 kb
Host smart-55f7f050-dc76-4239-bafc-7cef1d2b88eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142438310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.142438310
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.306043923
Short name T296
Test name
Test status
Simulation time 21143570928 ps
CPU time 19.14 seconds
Started Jan 24 01:17:32 PM PST 24
Finished Jan 24 01:18:28 PM PST 24
Peak memory 220048 kb
Host smart-50405e98-8d83-44f2-8fb1-7579d4f9fb5c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306043923 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.306043923
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.792307512
Short name T331
Test name
Test status
Simulation time 374538115 ps
CPU time 4.41 seconds
Started Jan 24 01:17:40 PM PST 24
Finished Jan 24 01:18:23 PM PST 24
Peak memory 211740 kb
Host smart-ceb5fccb-c2a8-4b53-93f7-7cdddecaf672
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792307512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.792307512
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.925824990
Short name T38
Test name
Test status
Simulation time 1981132632 ps
CPU time 10.1 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:29 PM PST 24
Peak memory 211892 kb
Host smart-b9934da3-38c7-41a4-a18c-1ed12adfbd9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925824990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.925824990
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2371449848
Short name T102
Test name
Test status
Simulation time 82656283 ps
CPU time 1.35 seconds
Started Jan 24 01:17:32 PM PST 24
Finished Jan 24 01:18:10 PM PST 24
Peak memory 203596 kb
Host smart-16d4c459-586d-40b9-bd94-7bafc37e765b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371449848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2371449848
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3841146825
Short name T263
Test name
Test status
Simulation time 149487553 ps
CPU time 1.17 seconds
Started Jan 24 01:17:33 PM PST 24
Finished Jan 24 01:18:11 PM PST 24
Peak memory 203572 kb
Host smart-ed186492-ad8e-4135-af2f-ede4ed22620b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841146825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3841146825
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.1852262107
Short name T117
Test name
Test status
Simulation time 48438812 ps
CPU time 0.68 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:20 PM PST 24
Peak memory 203472 kb
Host smart-ab7b89c4-79f7-4b51-9f87-368e11748b54
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852262107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
1852262107
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.3359002064
Short name T141
Test name
Test status
Simulation time 85164510 ps
CPU time 3.55 seconds
Started Jan 24 01:17:39 PM PST 24
Finished Jan 24 01:18:21 PM PST 24
Peak memory 203592 kb
Host smart-17a4d7eb-5d71-4b57-938e-81f556ed5246
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359002064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.3359002064
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2526988735
Short name T353
Test name
Test status
Simulation time 277889741 ps
CPU time 5.3 seconds
Started Jan 24 01:17:34 PM PST 24
Finished Jan 24 01:18:17 PM PST 24
Peak memory 203716 kb
Host smart-4dcc3b1f-44d5-4a9e-a775-5eff4d06c2d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526988735 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2526988735
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.3646121803
Short name T91
Test name
Test status
Simulation time 4316485051 ps
CPU time 15.83 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:42 PM PST 24
Peak memory 212400 kb
Host smart-b3e73a96-2b25-4781-8218-fd1fb240b604
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646121803 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.3
646121803
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.1913159386
Short name T55
Test name
Test status
Simulation time 5991681575 ps
CPU time 5.28 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:24 PM PST 24
Peak memory 220048 kb
Host smart-cd59600a-f07c-4507-bde2-8efbaff912d2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913159386 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.1913159386
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.4050566111
Short name T134
Test name
Test status
Simulation time 60185405 ps
CPU time 1.49 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:21 PM PST 24
Peak memory 211608 kb
Host smart-91f1c8b4-316e-416d-8901-4b7f892320a4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050566111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.4050566111
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.366831492
Short name T272
Test name
Test status
Simulation time 735839236 ps
CPU time 2.97 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:22 PM PST 24
Peak memory 203612 kb
Host smart-0589f38d-d16b-413b-9466-3d44c4c186b4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366831492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.366831492
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.4090554599
Short name T84
Test name
Test status
Simulation time 52214838 ps
CPU time 0.69 seconds
Started Jan 24 01:17:35 PM PST 24
Finished Jan 24 01:18:13 PM PST 24
Peak memory 203532 kb
Host smart-064b60b3-1113-47e1-bc8b-ec2af0cfa4b9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090554599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
4090554599
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.1839492440
Short name T350
Test name
Test status
Simulation time 538922965 ps
CPU time 5.97 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:25 PM PST 24
Peak memory 203704 kb
Host smart-02b68487-bdf0-4ac5-b2cb-633c7f4191b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839492440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.1839492440
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.193792876
Short name T284
Test name
Test status
Simulation time 59597380 ps
CPU time 1.78 seconds
Started Jan 24 01:17:41 PM PST 24
Finished Jan 24 01:18:21 PM PST 24
Peak memory 203532 kb
Host smart-81292ba8-e61b-449b-8270-90a288a5d2f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193792876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.193792876
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1968908174
Short name T320
Test name
Test status
Simulation time 652233579 ps
CPU time 8.03 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:34 PM PST 24
Peak memory 211900 kb
Host smart-f924f7bf-8f4b-4bc5-889e-f7c83b777694
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968908174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
968908174
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4261198680
Short name T127
Test name
Test status
Simulation time 2476489163 ps
CPU time 3.79 seconds
Started Jan 24 01:17:50 PM PST 24
Finished Jan 24 01:18:36 PM PST 24
Peak memory 213760 kb
Host smart-d18c841e-3974-4a5d-8965-fb98ac5465da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261198680 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4261198680
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.760605591
Short name T100
Test name
Test status
Simulation time 94258307 ps
CPU time 2.29 seconds
Started Jan 24 01:17:51 PM PST 24
Finished Jan 24 01:18:38 PM PST 24
Peak memory 211944 kb
Host smart-90c0f231-2a03-4ca6-9e6b-a2d3152f4b59
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760605591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.760605591
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.69924132
Short name T253
Test name
Test status
Simulation time 732998757 ps
CPU time 2.03 seconds
Started Jan 24 01:17:38 PM PST 24
Finished Jan 24 01:18:19 PM PST 24
Peak memory 203532 kb
Host smart-1184ec5c-7213-4575-9703-ecb5a22e91c2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69924132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.69924132
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.3551699139
Short name T310
Test name
Test status
Simulation time 32670334 ps
CPU time 0.68 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:27 PM PST 24
Peak memory 203488 kb
Host smart-431fbfdd-addf-4ec8-974c-6865619984ae
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551699139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
3551699139
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.212764973
Short name T58
Test name
Test status
Simulation time 270066828 ps
CPU time 3.98 seconds
Started Jan 24 01:17:54 PM PST 24
Finished Jan 24 01:18:45 PM PST 24
Peak memory 203688 kb
Host smart-98965ae3-b007-44ca-a4b0-42f05f56e727
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212764973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.212764973
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2531956952
Short name T126
Test name
Test status
Simulation time 261622283 ps
CPU time 4.79 seconds
Started Jan 24 01:17:40 PM PST 24
Finished Jan 24 01:18:24 PM PST 24
Peak memory 203548 kb
Host smart-f620ce0f-77da-44cc-afed-31b5d2da720d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531956952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2531956952
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.3217446770
Short name T255
Test name
Test status
Simulation time 1037379338 ps
CPU time 18.13 seconds
Started Jan 24 01:17:54 PM PST 24
Finished Jan 24 01:18:58 PM PST 24
Peak memory 212956 kb
Host smart-4ab17309-30d4-41d0-bbe6-946032559603
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217446770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.3
217446770
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.2874256021
Short name T330
Test name
Test status
Simulation time 1933583001 ps
CPU time 5.01 seconds
Started Jan 24 01:17:54 PM PST 24
Finished Jan 24 01:18:45 PM PST 24
Peak memory 211816 kb
Host smart-90a9b557-8aee-464b-8438-a819e32aa240
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874256021 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.2874256021
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.464872623
Short name T122
Test name
Test status
Simulation time 108760650 ps
CPU time 2.36 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:28 PM PST 24
Peak memory 211884 kb
Host smart-f9f0b341-093e-495d-9fdc-1cf9a581ca7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464872623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.464872623
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.3290701231
Short name T273
Test name
Test status
Simulation time 812057396 ps
CPU time 1.19 seconds
Started Jan 24 01:17:50 PM PST 24
Finished Jan 24 01:18:37 PM PST 24
Peak memory 203572 kb
Host smart-bc83cf67-05dc-4321-92e2-a7107ed4e3fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290701231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
3290701231
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.820166048
Short name T119
Test name
Test status
Simulation time 25654286 ps
CPU time 0.67 seconds
Started Jan 24 01:17:54 PM PST 24
Finished Jan 24 01:18:42 PM PST 24
Peak memory 203328 kb
Host smart-5f12eb5f-148f-4584-a259-4ded123f3f1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820166048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.820166048
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.137434170
Short name T130
Test name
Test status
Simulation time 1244008033 ps
CPU time 3.82 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:29 PM PST 24
Peak memory 203652 kb
Host smart-31e7410d-dac3-4fc0-a57c-06cc66fc7be1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137434170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.137434170
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2261097099
Short name T264
Test name
Test status
Simulation time 468096335 ps
CPU time 4.1 seconds
Started Jan 24 01:17:54 PM PST 24
Finished Jan 24 01:18:45 PM PST 24
Peak memory 203516 kb
Host smart-1036ceb1-febf-4bdb-962a-1c3bf48fe322
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261097099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2261097099
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1568730646
Short name T87
Test name
Test status
Simulation time 4694349732 ps
CPU time 18.69 seconds
Started Jan 24 01:17:50 PM PST 24
Finished Jan 24 01:18:54 PM PST 24
Peak memory 216032 kb
Host smart-a58fc798-8205-49a5-a8be-5808a268e7b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568730646 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
568730646
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1263932920
Short name T254
Test name
Test status
Simulation time 93637234 ps
CPU time 1.82 seconds
Started Jan 24 01:17:46 PM PST 24
Finished Jan 24 01:18:28 PM PST 24
Peak memory 212760 kb
Host smart-787ccd45-4a91-418d-98ef-5c471f5c608f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263932920 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1263932920
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3371356945
Short name T59
Test name
Test status
Simulation time 402644574 ps
CPU time 2.18 seconds
Started Jan 24 01:17:47 PM PST 24
Finished Jan 24 01:18:29 PM PST 24
Peak memory 211860 kb
Host smart-c5f94522-d6bd-4151-95e4-c90fce0a3e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371356945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3371356945
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.548267476
Short name T237
Test name
Test status
Simulation time 596555228 ps
CPU time 0.89 seconds
Started Jan 24 01:17:53 PM PST 24
Finished Jan 24 01:18:41 PM PST 24
Peak memory 203628 kb
Host smart-41ab0947-3aa1-4593-926e-e69a6f019537
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548267476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.548267476
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.3565137432
Short name T266
Test name
Test status
Simulation time 45731956 ps
CPU time 0.7 seconds
Started Jan 24 01:17:53 PM PST 24
Finished Jan 24 01:18:41 PM PST 24
Peak memory 203484 kb
Host smart-e6a2e269-2725-4d9f-8dc7-8e9e3ac7df89
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565137432 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
3565137432
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.1819855763
Short name T249
Test name
Test status
Simulation time 13111290502 ps
CPU time 10.21 seconds
Started Jan 24 01:17:50 PM PST 24
Finished Jan 24 01:18:45 PM PST 24
Peak memory 212116 kb
Host smart-7132a83e-1855-4e7f-8e25-fb8d3ff2de32
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819855763 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.1819855763
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3154961821
Short name T43
Test name
Test status
Simulation time 517518117 ps
CPU time 2.98 seconds
Started Jan 24 01:17:45 PM PST 24
Finished Jan 24 01:18:27 PM PST 24
Peak memory 211836 kb
Host smart-86b28e40-7539-4317-8334-48541911fd4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154961821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3154961821
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3388494931
Short name T150
Test name
Test status
Simulation time 696080652 ps
CPU time 16.74 seconds
Started Jan 24 01:17:48 PM PST 24
Finished Jan 24 01:18:46 PM PST 24
Peak memory 211924 kb
Host smart-ab136274-8645-4648-b092-8285edc76e96
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388494931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
388494931
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1185398399
Short name T114
Test name
Test status
Simulation time 2120897574 ps
CPU time 26.54 seconds
Started Jan 24 01:16:06 PM PST 24
Finished Jan 24 01:17:12 PM PST 24
Peak memory 203632 kb
Host smart-8de2b2bc-8b3d-45cd-a9f2-a9c1446e21c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185398399 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1185398399
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3962126995
Short name T60
Test name
Test status
Simulation time 5577581664 ps
CPU time 54.48 seconds
Started Jan 24 01:16:15 PM PST 24
Finished Jan 24 01:17:51 PM PST 24
Peak memory 203632 kb
Host smart-8423ced4-6755-4eeb-8740-1b017c42f8ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962126995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3962126995
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.732738702
Short name T123
Test name
Test status
Simulation time 99152251 ps
CPU time 1.43 seconds
Started Jan 24 01:16:14 PM PST 24
Finished Jan 24 01:16:56 PM PST 24
Peak memory 203692 kb
Host smart-c93a24b3-ba62-4453-acfb-fa6c25a74e4a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732738702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.732738702
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.4031268655
Short name T56
Test name
Test status
Simulation time 378044678 ps
CPU time 1.52 seconds
Started Jan 24 01:16:25 PM PST 24
Finished Jan 24 01:17:10 PM PST 24
Peak memory 203656 kb
Host smart-a43d8f15-31f6-4449-8d26-906482c904f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031268655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.4031268655
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.639258966
Short name T347
Test name
Test status
Simulation time 8082446388 ps
CPU time 20.17 seconds
Started Jan 24 01:16:04 PM PST 24
Finished Jan 24 01:17:02 PM PST 24
Peak memory 203212 kb
Host smart-08d8bbb1-bd75-4c57-a266-c7adef36de3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639258966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.639258966
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1983797336
Short name T277
Test name
Test status
Simulation time 15110616248 ps
CPU time 34.06 seconds
Started Jan 24 01:16:07 PM PST 24
Finished Jan 24 01:17:21 PM PST 24
Peak memory 203652 kb
Host smart-9ab26e7b-97a1-4efb-aac3-40bb72147b04
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983797336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1983797336
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.2595967679
Short name T108
Test name
Test status
Simulation time 802989172 ps
CPU time 3.42 seconds
Started Jan 24 01:16:06 PM PST 24
Finished Jan 24 01:16:49 PM PST 24
Peak memory 203576 kb
Host smart-c6eec88b-4099-4776-86f7-33cee7ae6faa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595967679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.2595967679
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.805830994
Short name T313
Test name
Test status
Simulation time 471522520 ps
CPU time 1.3 seconds
Started Jan 24 01:16:05 PM PST 24
Finished Jan 24 01:16:44 PM PST 24
Peak memory 203568 kb
Host smart-e71587e4-9ab9-4f6e-a108-b0b0382e9e06
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805830994 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.805830994
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.245618435
Short name T303
Test name
Test status
Simulation time 127563478 ps
CPU time 0.71 seconds
Started Jan 24 01:16:10 PM PST 24
Finished Jan 24 01:16:52 PM PST 24
Peak memory 203432 kb
Host smart-6409b801-4716-4acd-812d-3bb3ef7cc76c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245618435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.245618435
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1869783674
Short name T282
Test name
Test status
Simulation time 3130523593 ps
CPU time 4.17 seconds
Started Jan 24 01:16:07 PM PST 24
Finished Jan 24 01:16:52 PM PST 24
Peak memory 203640 kb
Host smart-2e003ff0-d9f4-4c1c-b647-b72b5edd9579
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869783674 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1869783674
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3443661504
Short name T288
Test name
Test status
Simulation time 40583545 ps
CPU time 0.72 seconds
Started Jan 24 01:16:08 PM PST 24
Finished Jan 24 01:16:49 PM PST 24
Peak memory 203480 kb
Host smart-128b47b5-f111-4c9c-ba4e-b7d9f5f259f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443661504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3443661504
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1316273460
Short name T69
Test name
Test status
Simulation time 147914143 ps
CPU time 0.65 seconds
Started Jan 24 01:16:03 PM PST 24
Finished Jan 24 01:16:42 PM PST 24
Peak memory 203508 kb
Host smart-0dd4d515-eab5-4103-ab5b-5197b5505c03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316273460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
316273460
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3080217456
Short name T251
Test name
Test status
Simulation time 42158793 ps
CPU time 0.64 seconds
Started Jan 24 01:16:24 PM PST 24
Finished Jan 24 01:17:08 PM PST 24
Peak memory 203456 kb
Host smart-b055c096-d154-45c8-8b4c-67f0e8314684
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080217456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3080217456
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.2887668101
Short name T354
Test name
Test status
Simulation time 19625389 ps
CPU time 0.65 seconds
Started Jan 24 01:22:48 PM PST 24
Finished Jan 24 01:23:45 PM PST 24
Peak memory 203484 kb
Host smart-d6ed2b10-b6ac-4ba4-ba2f-ad6e90db0dcf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887668101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.2887668101
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1252742856
Short name T44
Test name
Test status
Simulation time 164059721 ps
CPU time 6.78 seconds
Started Jan 24 01:16:16 PM PST 24
Finished Jan 24 01:17:04 PM PST 24
Peak memory 203568 kb
Host smart-cac42265-08bc-44be-a545-b5244a7a12ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252742856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1252742856
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.2614646206
Short name T287
Test name
Test status
Simulation time 21337846886 ps
CPU time 10.63 seconds
Started Jan 24 01:16:11 PM PST 24
Finished Jan 24 01:17:02 PM PST 24
Peak memory 212148 kb
Host smart-7b28d34f-8976-41bb-8d39-29e62f4a44c4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614646206 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.2614646206
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.4035455568
Short name T332
Test name
Test status
Simulation time 79655395 ps
CPU time 4.14 seconds
Started Jan 24 01:25:26 PM PST 24
Finished Jan 24 01:26:21 PM PST 24
Peak memory 211912 kb
Host smart-43b60904-6839-4dfc-b90f-42161d11be2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035455568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.4035455568
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2704880143
Short name T259
Test name
Test status
Simulation time 449537775 ps
CPU time 8.35 seconds
Started Jan 24 01:16:04 PM PST 24
Finished Jan 24 01:16:50 PM PST 24
Peak memory 211552 kb
Host smart-f49466b9-e2e2-47f1-800b-c6a95ee2c5cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704880143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2704880143
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.2150092254
Short name T328
Test name
Test status
Simulation time 47351504063 ps
CPU time 26.58 seconds
Started Jan 24 02:30:26 PM PST 24
Finished Jan 24 02:31:04 PM PST 24
Peak memory 220016 kb
Host smart-d5b6e592-35b3-4919-9d3e-587d9e84d95a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150092254 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.2150092254
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/24.rv_dm_tap_fsm_rand_reset.3213504104
Short name T298
Test name
Test status
Simulation time 10664958989 ps
CPU time 10 seconds
Started Jan 24 01:17:51 PM PST 24
Finished Jan 24 01:18:45 PM PST 24
Peak memory 211900 kb
Host smart-44ac897a-62a1-44c3-a404-e0cfe150fe5f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3213504104 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 24.rv_dm_tap_fsm_rand_reset.3213504104
Directory /workspace/24.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.951942325
Short name T244
Test name
Test status
Simulation time 10192024746 ps
CPU time 10.54 seconds
Started Jan 24 01:18:08 PM PST 24
Finished Jan 24 01:19:09 PM PST 24
Peak memory 211920 kb
Host smart-6f53c0c1-6b98-433f-bd6b-5ad5e3748230
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951942325 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.951942325
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.3513338043
Short name T250
Test name
Test status
Simulation time 4563614460 ps
CPU time 16.26 seconds
Started Jan 24 01:18:07 PM PST 24
Finished Jan 24 01:19:14 PM PST 24
Peak memory 211936 kb
Host smart-2d30e730-7761-40ca-9cc5-55659c7f2a9a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513338043 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.3513338043
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.4239432253
Short name T139
Test name
Test status
Simulation time 2846139527 ps
CPU time 53.84 seconds
Started Jan 24 01:16:45 PM PST 24
Finished Jan 24 01:18:17 PM PST 24
Peak memory 203588 kb
Host smart-18d476b8-31d6-43e4-a2f1-5e4217a1be10
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239432253 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.4239432253
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3762239246
Short name T318
Test name
Test status
Simulation time 81195219 ps
CPU time 1.42 seconds
Started Jan 24 01:16:27 PM PST 24
Finished Jan 24 01:17:11 PM PST 24
Peak memory 203664 kb
Host smart-ab9f3f5b-fac2-40f5-8b8e-0efb72985e04
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762239246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3762239246
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.761771616
Short name T275
Test name
Test status
Simulation time 4153889010 ps
CPU time 4.11 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 214700 kb
Host smart-abb9e782-9a0e-4dfb-96ac-b876bf187ba5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761771616 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.761771616
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4187871509
Short name T140
Test name
Test status
Simulation time 82936476 ps
CPU time 2.07 seconds
Started Jan 24 01:16:54 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 211920 kb
Host smart-468f9ec5-f75e-4ad5-a0a2-0e4781840dcf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187871509 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4187871509
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2729245811
Short name T235
Test name
Test status
Simulation time 9457705466 ps
CPU time 13.11 seconds
Started Jan 24 01:16:21 PM PST 24
Finished Jan 24 01:17:17 PM PST 24
Peak memory 203680 kb
Host smart-98a8e34f-0ff7-401c-b7b2-d420c154ea39
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729245811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2729245811
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.2483761712
Short name T274
Test name
Test status
Simulation time 5627202315 ps
CPU time 23.17 seconds
Started Jan 24 01:16:25 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 203628 kb
Host smart-d06afae7-9bfd-4612-bf6a-feac6e4e9610
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483761712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.2483761712
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3702348377
Short name T106
Test name
Test status
Simulation time 707342215 ps
CPU time 1.51 seconds
Started Jan 24 01:16:27 PM PST 24
Finished Jan 24 01:17:12 PM PST 24
Peak memory 203504 kb
Host smart-826e4e6c-f875-4d63-b82b-eaa17831a73a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702348377 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3702348377
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.1020850419
Short name T346
Test name
Test status
Simulation time 399337367 ps
CPU time 0.91 seconds
Started Jan 24 01:16:27 PM PST 24
Finished Jan 24 01:17:10 PM PST 24
Peak memory 203660 kb
Host smart-baaea9f8-b609-49ae-a75e-181d27295347
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1020850419 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.1
020850419
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.816319024
Short name T335
Test name
Test status
Simulation time 215369486 ps
CPU time 0.8 seconds
Started Jan 24 01:16:12 PM PST 24
Finished Jan 24 01:16:54 PM PST 24
Peak memory 203464 kb
Host smart-383738e9-7d79-44ad-9025-76fbf4b16736
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816319024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.816319024
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.2355263279
Short name T304
Test name
Test status
Simulation time 1163434479 ps
CPU time 4.27 seconds
Started Jan 24 01:57:13 PM PST 24
Finished Jan 24 01:57:19 PM PST 24
Peak memory 203600 kb
Host smart-3c6118b0-35d3-4e45-a7dc-cf887d820b82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355263279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.2355263279
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.794597218
Short name T345
Test name
Test status
Simulation time 144219809 ps
CPU time 0.65 seconds
Started Jan 24 03:02:12 PM PST 24
Finished Jan 24 03:02:19 PM PST 24
Peak memory 203528 kb
Host smart-14401177-00b8-4cb9-8ef2-5f717c7dc2df
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794597218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_hw_reset.794597218
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.248118536
Short name T267
Test name
Test status
Simulation time 78452440 ps
CPU time 0.79 seconds
Started Jan 24 01:16:16 PM PST 24
Finished Jan 24 01:16:59 PM PST 24
Peak memory 203532 kb
Host smart-d01286d6-06e2-495c-94ac-d576e84828a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=248118536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.248118536
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.824366466
Short name T285
Test name
Test status
Simulation time 23651822 ps
CPU time 0.61 seconds
Started Jan 24 01:16:25 PM PST 24
Finished Jan 24 01:17:09 PM PST 24
Peak memory 203380 kb
Host smart-c0b41c13-ac87-49e4-9de7-2097863ed8ba
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824366466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_part
ial_access.824366466
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1287589121
Short name T137
Test name
Test status
Simulation time 102414488 ps
CPU time 0.62 seconds
Started Jan 24 01:16:24 PM PST 24
Finished Jan 24 01:17:08 PM PST 24
Peak memory 203428 kb
Host smart-1850ee71-ef8b-4b09-810a-56ce9f211fc0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287589121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1287589121
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.3429582220
Short name T321
Test name
Test status
Simulation time 1061656574 ps
CPU time 7.42 seconds
Started Jan 24 01:16:47 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 203680 kb
Host smart-dfc7502c-f480-405e-bd9d-9d57892ca9bb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429582220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_
csr_outstanding.3429582220
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.2332704061
Short name T265
Test name
Test status
Simulation time 1416722491 ps
CPU time 15.53 seconds
Started Jan 24 01:16:27 PM PST 24
Finished Jan 24 01:17:26 PM PST 24
Peak memory 211860 kb
Host smart-691398f3-1095-4d8b-82bc-33d8568cc7b8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332704061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.2332704061
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.4232731221
Short name T89
Test name
Test status
Simulation time 19726453015 ps
CPU time 17.72 seconds
Started Jan 24 01:18:09 PM PST 24
Finished Jan 24 01:19:17 PM PST 24
Peak memory 220084 kb
Host smart-93ad7dac-f181-40e2-bd94-e1be189dccc7
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232731221 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.4232731221
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.3669065392
Short name T65
Test name
Test status
Simulation time 7176458862 ps
CPU time 9.57 seconds
Started Jan 24 01:18:11 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 211912 kb
Host smart-10bcf124-ffdc-4667-8d2d-df00d499f6fe
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669065392 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.3669065392
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.1114881895
Short name T256
Test name
Test status
Simulation time 7708992354 ps
CPU time 12.48 seconds
Started Jan 24 01:18:06 PM PST 24
Finished Jan 24 01:19:09 PM PST 24
Peak memory 219820 kb
Host smart-fb00e05d-6e30-436c-9ce7-b836e297c341
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114881895 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.1114881895
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.311308660
Short name T42
Test name
Test status
Simulation time 17143785882 ps
CPU time 21.03 seconds
Started Jan 24 01:28:44 PM PST 24
Finished Jan 24 01:29:27 PM PST 24
Peak memory 211960 kb
Host smart-0f19910b-b47b-4cbf-ad92-5502da838068
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311308660 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.311308660
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2711502368
Short name T172
Test name
Test status
Simulation time 6366788146 ps
CPU time 63.96 seconds
Started Jan 24 01:16:48 PM PST 24
Finished Jan 24 01:18:28 PM PST 24
Peak memory 203688 kb
Host smart-16a79b3f-d2d5-4df7-8fb8-b79f32e78b65
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711502368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2711502368
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.249395268
Short name T281
Test name
Test status
Simulation time 1414000917 ps
CPU time 51.77 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:18:19 PM PST 24
Peak memory 203632 kb
Host smart-c5b01527-9bc6-4e54-9162-3f5f040a1c92
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249395268 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.249395268
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2636383576
Short name T324
Test name
Test status
Simulation time 60603635 ps
CPU time 2.12 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:29 PM PST 24
Peak memory 203716 kb
Host smart-cc6ff9fb-d538-4627-8353-4dfe409a3d1f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636383576 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2636383576
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.960451585
Short name T124
Test name
Test status
Simulation time 109315579 ps
CPU time 2.11 seconds
Started Jan 24 01:16:49 PM PST 24
Finished Jan 24 01:17:27 PM PST 24
Peak memory 203476 kb
Host smart-a450730c-edca-4459-8fc2-b2ecde833543
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960451585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.960451585
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.3901173787
Short name T357
Test name
Test status
Simulation time 4825738824 ps
CPU time 11.85 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:39 PM PST 24
Peak memory 203628 kb
Host smart-0e0b8006-48f4-4492-945c-0a3e99a7a719
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901173787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.3901173787
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3619520876
Short name T349
Test name
Test status
Simulation time 12206775937 ps
CPU time 41.18 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:18:09 PM PST 24
Peak memory 203732 kb
Host smart-73ac4fb8-7f57-4c00-902f-25ae7c62b7d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619520876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3619520876
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.246865593
Short name T109
Test name
Test status
Simulation time 1028433302 ps
CPU time 3.17 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:30 PM PST 24
Peak memory 203576 kb
Host smart-e61a9662-b42b-418d-a447-88128ddf0274
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246865593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.246865593
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.1568131206
Short name T112
Test name
Test status
Simulation time 537474500 ps
CPU time 1.4 seconds
Started Jan 24 01:16:51 PM PST 24
Finished Jan 24 01:17:27 PM PST 24
Peak memory 203624 kb
Host smart-7b5b431f-70b0-47f6-9da5-4c30bb3ec29e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568131206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.1
568131206
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.3726113822
Short name T338
Test name
Test status
Simulation time 66141357 ps
CPU time 0.81 seconds
Started Jan 24 01:16:54 PM PST 24
Finished Jan 24 01:17:30 PM PST 24
Peak memory 203488 kb
Host smart-8306ed67-15dc-4a7c-beb1-73435a536d7b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726113822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.3726113822
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2762413115
Short name T271
Test name
Test status
Simulation time 521174071 ps
CPU time 1.92 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:29 PM PST 24
Peak memory 203652 kb
Host smart-590e6f03-6a36-46be-a909-08c021c5cf6c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762413115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2762413115
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.1149170423
Short name T342
Test name
Test status
Simulation time 60195357 ps
CPU time 0.66 seconds
Started Jan 24 01:16:49 PM PST 24
Finished Jan 24 01:17:25 PM PST 24
Peak memory 203488 kb
Host smart-72247086-fb4e-4b53-8f64-0f6ca0b4f2f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149170423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.1149170423
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1787817455
Short name T311
Test name
Test status
Simulation time 57685733 ps
CPU time 0.68 seconds
Started Jan 24 01:16:51 PM PST 24
Finished Jan 24 01:17:26 PM PST 24
Peak memory 203488 kb
Host smart-13b654a9-184a-410f-a6b7-c3b39dca6eed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787817455 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
787817455
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1783240529
Short name T344
Test name
Test status
Simulation time 29582243 ps
CPU time 0.63 seconds
Started Jan 24 01:16:52 PM PST 24
Finished Jan 24 01:17:28 PM PST 24
Peak memory 203420 kb
Host smart-79b7f1e4-9547-4bc4-b989-9b2fa616b9e7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783240529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1783240529
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1713549695
Short name T268
Test name
Test status
Simulation time 39354026 ps
CPU time 0.62 seconds
Started Jan 24 01:17:01 PM PST 24
Finished Jan 24 01:17:36 PM PST 24
Peak memory 203476 kb
Host smart-8285dbb1-b792-4b84-8575-61991789ad35
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713549695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1713549695
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3522628053
Short name T99
Test name
Test status
Simulation time 1976532059 ps
CPU time 7.53 seconds
Started Jan 24 01:16:47 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 203592 kb
Host smart-91d58668-299c-41be-aaad-875c4c373660
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522628053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3522628053
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.3577606135
Short name T301
Test name
Test status
Simulation time 217010522 ps
CPU time 2.99 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 203780 kb
Host smart-26d49cb8-39de-4f90-934f-f5470bf0b2b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577606135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.3577606135
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2095194591
Short name T257
Test name
Test status
Simulation time 537765395 ps
CPU time 9.52 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:37 PM PST 24
Peak memory 211920 kb
Host smart-9a75beed-86ee-4f96-84df-6f5f112c5ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095194591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2095194591
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.3258601581
Short name T294
Test name
Test status
Simulation time 2224014578 ps
CPU time 4.09 seconds
Started Jan 24 01:16:57 PM PST 24
Finished Jan 24 01:17:36 PM PST 24
Peak memory 220028 kb
Host smart-682402a4-4212-4c0d-afac-3d509828573d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258601581 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.3258601581
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3176882682
Short name T300
Test name
Test status
Simulation time 186429640 ps
CPU time 2.3 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 211924 kb
Host smart-3cb0aa8e-c367-4cbf-95cb-8c867ec0d0f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176882682 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3176882682
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2977317123
Short name T242
Test name
Test status
Simulation time 815979118 ps
CPU time 3.14 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 203620 kb
Host smart-5be313e1-4edf-46e4-bbd5-9f3a8abf99c3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977317123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
977317123
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.724565430
Short name T260
Test name
Test status
Simulation time 140672486 ps
CPU time 0.65 seconds
Started Jan 24 01:16:47 PM PST 24
Finished Jan 24 01:17:24 PM PST 24
Peak memory 203340 kb
Host smart-ba96bbd4-be85-4889-9dbe-631bd97e1793
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724565430 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.724565430
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2286937571
Short name T120
Test name
Test status
Simulation time 9260606320 ps
CPU time 8 seconds
Started Jan 24 01:16:51 PM PST 24
Finished Jan 24 01:17:34 PM PST 24
Peak memory 203740 kb
Host smart-9fda1731-b723-4f98-8639-3b784deaf839
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286937571 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2286937571
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tap_fsm_rand_reset.500381129
Short name T325
Test name
Test status
Simulation time 4966402811 ps
CPU time 16.18 seconds
Started Jan 24 01:16:51 PM PST 24
Finished Jan 24 01:17:42 PM PST 24
Peak memory 219840 kb
Host smart-2d4a95ea-e41d-4edc-9e24-43403dea941b
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500381129 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.rv_dm_tap_fsm_rand_reset.500381129
Directory /workspace/5.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3545145529
Short name T61
Test name
Test status
Simulation time 195764988 ps
CPU time 2.92 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:31 PM PST 24
Peak memory 211940 kb
Host smart-906978ee-f993-49c0-8798-719e6a620bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3545145529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3545145529
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3530737745
Short name T329
Test name
Test status
Simulation time 3868952786 ps
CPU time 20.8 seconds
Started Jan 24 01:16:51 PM PST 24
Finished Jan 24 01:17:47 PM PST 24
Peak memory 217996 kb
Host smart-5cce42c0-a2ba-4fab-be78-25ecf06735f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3530737745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3530737745
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2139748113
Short name T57
Test name
Test status
Simulation time 1220152069 ps
CPU time 3.21 seconds
Started Jan 24 01:16:57 PM PST 24
Finished Jan 24 01:17:35 PM PST 24
Peak memory 219832 kb
Host smart-5966c9e8-27a7-4b5d-8a3c-a6a2504b45d3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139748113 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2139748113
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.496695979
Short name T111
Test name
Test status
Simulation time 56606376 ps
CPU time 1.58 seconds
Started Jan 24 01:17:01 PM PST 24
Finished Jan 24 01:17:38 PM PST 24
Peak memory 203500 kb
Host smart-ee1f6f5c-c9de-42c7-8adc-f7a4e8709da6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496695979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.496695979
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.3793916619
Short name T245
Test name
Test status
Simulation time 378795470 ps
CPU time 2.05 seconds
Started Jan 24 01:16:57 PM PST 24
Finished Jan 24 01:17:34 PM PST 24
Peak memory 203564 kb
Host smart-ae2af146-3145-4fc2-aa99-bd2d20e0d135
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793916619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.3
793916619
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2136382551
Short name T334
Test name
Test status
Simulation time 114327642 ps
CPU time 0.77 seconds
Started Jan 24 01:16:53 PM PST 24
Finished Jan 24 01:17:29 PM PST 24
Peak memory 203508 kb
Host smart-ec39d762-2bbe-46c2-bfdf-47359228df41
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136382551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
136382551
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2833138624
Short name T129
Test name
Test status
Simulation time 1572726045 ps
CPU time 8.1 seconds
Started Jan 24 01:17:00 PM PST 24
Finished Jan 24 01:17:43 PM PST 24
Peak memory 203644 kb
Host smart-0c4c2c2c-01de-45ea-974f-ddc819eaf487
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833138624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2833138624
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.980013226
Short name T269
Test name
Test status
Simulation time 328434142 ps
CPU time 2.99 seconds
Started Jan 24 01:17:00 PM PST 24
Finished Jan 24 01:17:36 PM PST 24
Peak memory 203540 kb
Host smart-5e239f1d-a09a-4da3-a7b4-d1f17b35770d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980013226 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.980013226
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.1455136845
Short name T326
Test name
Test status
Simulation time 769426057 ps
CPU time 10.3 seconds
Started Jan 24 01:16:57 PM PST 24
Finished Jan 24 01:17:42 PM PST 24
Peak memory 212300 kb
Host smart-a6ea1268-dca0-48c7-9c7c-40ddbf0a835a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455136845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.1455136845
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2228854094
Short name T270
Test name
Test status
Simulation time 3090226598 ps
CPU time 3.84 seconds
Started Jan 24 01:16:59 PM PST 24
Finished Jan 24 01:17:37 PM PST 24
Peak memory 220000 kb
Host smart-08102d92-4142-4fdf-bf3f-bd4d395249b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228854094 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2228854094
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2150023638
Short name T315
Test name
Test status
Simulation time 202381291 ps
CPU time 1.49 seconds
Started Jan 24 01:16:54 PM PST 24
Finished Jan 24 01:17:30 PM PST 24
Peak memory 203640 kb
Host smart-904f6268-1aec-4d2d-ba00-13a8f9c080ac
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150023638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2150023638
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.4095750011
Short name T240
Test name
Test status
Simulation time 125440752 ps
CPU time 1.09 seconds
Started Jan 24 01:17:01 PM PST 24
Finished Jan 24 01:17:37 PM PST 24
Peak memory 203668 kb
Host smart-97e0799d-3ba1-4930-9547-cf7749bd28af
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095750011 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.4
095750011
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.1390583684
Short name T297
Test name
Test status
Simulation time 129460872 ps
CPU time 0.62 seconds
Started Jan 24 01:17:00 PM PST 24
Finished Jan 24 01:17:36 PM PST 24
Peak memory 203500 kb
Host smart-acad4019-c21a-489d-8b38-35406f0da51e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390583684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.1
390583684
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.3051428164
Short name T143
Test name
Test status
Simulation time 819266299 ps
CPU time 7.31 seconds
Started Jan 24 01:17:06 PM PST 24
Finished Jan 24 01:17:50 PM PST 24
Peak memory 203672 kb
Host smart-a06856ac-1e68-43b9-8edd-e80718963942
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051428164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.3051428164
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2333458548
Short name T276
Test name
Test status
Simulation time 223206047 ps
CPU time 2.31 seconds
Started Jan 24 01:17:00 PM PST 24
Finished Jan 24 01:17:37 PM PST 24
Peak memory 203696 kb
Host smart-8b81248c-e90e-4dfe-87ec-512a5528b087
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333458548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2333458548
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2092109640
Short name T165
Test name
Test status
Simulation time 66823456 ps
CPU time 3.08 seconds
Started Jan 24 01:17:05 PM PST 24
Finished Jan 24 01:17:44 PM PST 24
Peak memory 214732 kb
Host smart-cf4202c0-9d32-4d2b-b666-cbeddd28726a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092109640 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2092109640
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.1073572888
Short name T336
Test name
Test status
Simulation time 192312129 ps
CPU time 2.3 seconds
Started Jan 24 01:17:01 PM PST 24
Finished Jan 24 01:17:38 PM PST 24
Peak memory 211840 kb
Host smart-88018fca-e7e7-446c-8f6f-b98d4ebc4384
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073572888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.1073572888
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.880526836
Short name T236
Test name
Test status
Simulation time 636140661 ps
CPU time 1.3 seconds
Started Jan 24 01:17:01 PM PST 24
Finished Jan 24 01:17:37 PM PST 24
Peak memory 203620 kb
Host smart-c8b87f23-851b-4dbf-9af4-a8620353fb7a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880526836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.880526836
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2154067386
Short name T83
Test name
Test status
Simulation time 64080808 ps
CPU time 0.77 seconds
Started Jan 24 01:17:04 PM PST 24
Finished Jan 24 01:17:40 PM PST 24
Peak memory 203444 kb
Host smart-51a7abaa-2c0b-43aa-bbf7-62f6d1d341f4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154067386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
154067386
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.1638116949
Short name T41
Test name
Test status
Simulation time 355991594 ps
CPU time 3.14 seconds
Started Jan 24 01:17:08 PM PST 24
Finished Jan 24 01:17:48 PM PST 24
Peak memory 211904 kb
Host smart-2acea7f4-e7b4-4a40-93d9-1455c4dbbf04
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638116949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.1638116949
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.980535656
Short name T152
Test name
Test status
Simulation time 234845509 ps
CPU time 7.75 seconds
Started Jan 24 01:17:08 PM PST 24
Finished Jan 24 01:17:53 PM PST 24
Peak memory 211684 kb
Host smart-092ed109-27fb-47d1-ab81-6a32390918bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980535656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.980535656
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2478845719
Short name T138
Test name
Test status
Simulation time 139705181 ps
CPU time 2.17 seconds
Started Jan 24 01:17:05 PM PST 24
Finished Jan 24 01:17:44 PM PST 24
Peak memory 203620 kb
Host smart-def12c0f-3bda-4a04-8831-dc45a1953a38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478845719 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2478845719
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3008910456
Short name T121
Test name
Test status
Simulation time 677350633 ps
CPU time 2.59 seconds
Started Jan 24 01:27:00 PM PST 24
Finished Jan 24 01:27:42 PM PST 24
Peak memory 203596 kb
Host smart-c26725a4-4bac-4bbf-a4a4-77011f140c71
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008910456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
008910456
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.1913838738
Short name T103
Test name
Test status
Simulation time 61390391 ps
CPU time 0.77 seconds
Started Jan 24 01:17:08 PM PST 24
Finished Jan 24 01:17:46 PM PST 24
Peak memory 203220 kb
Host smart-0b1cd23c-767e-42d2-8a62-074d0f3e35ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913838738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.1
913838738
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1328183151
Short name T133
Test name
Test status
Simulation time 272269924 ps
CPU time 6.15 seconds
Started Jan 24 01:16:59 PM PST 24
Finished Jan 24 01:17:39 PM PST 24
Peak memory 203176 kb
Host smart-22573a74-1be7-40cc-a85d-81fb26287b32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328183151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1328183151
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.1146061836
Short name T113
Test name
Test status
Simulation time 206901138 ps
CPU time 2.78 seconds
Started Jan 24 01:16:59 PM PST 24
Finished Jan 24 01:17:36 PM PST 24
Peak memory 211524 kb
Host smart-ad2ae815-7aa2-47e1-870c-9f2386648df0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146061836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.1146061836
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.1618090822
Short name T197
Test name
Test status
Simulation time 30577059 ps
CPU time 0.74 seconds
Started Jan 24 01:18:28 PM PST 24
Finished Jan 24 01:19:09 PM PST 24
Peak memory 203560 kb
Host smart-c26dd3c2-415e-4d88-a602-0786a0511b35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618090822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.1618090822
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.4216226052
Short name T54
Test name
Test status
Simulation time 1376790604 ps
CPU time 3.59 seconds
Started Jan 24 01:18:12 PM PST 24
Finished Jan 24 01:19:04 PM PST 24
Peak memory 203944 kb
Host smart-360f2b3a-1606-4f91-8a9f-00beae570bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216226052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.4216226052
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.1107468625
Short name T8
Test name
Test status
Simulation time 1414104496 ps
CPU time 5.24 seconds
Started Jan 24 01:18:17 PM PST 24
Finished Jan 24 01:19:07 PM PST 24
Peak memory 203536 kb
Host smart-15f45f6d-16f0-46a1-91a3-799181b75253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107468625 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.1107468625
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3395560766
Short name T88
Test name
Test status
Simulation time 239524741 ps
CPU time 0.68 seconds
Started Jan 24 01:47:50 PM PST 24
Finished Jan 24 01:48:11 PM PST 24
Peak memory 203432 kb
Host smart-bab445d9-1891-4af2-a576-40adfa184824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3395560766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3395560766
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1958548378
Short name T180
Test name
Test status
Simulation time 317209183 ps
CPU time 1.74 seconds
Started Jan 24 01:50:05 PM PST 24
Finished Jan 24 01:50:08 PM PST 24
Peak memory 203988 kb
Host smart-192a626c-5733-414c-9093-a16149fb9a6b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958548378 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1958548378
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1700196510
Short name T98
Test name
Test status
Simulation time 712215051 ps
CPU time 2.97 seconds
Started Jan 24 01:18:27 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 203808 kb
Host smart-b4d76ae3-06e4-4695-8744-c2d5a060ae43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700196510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1700196510
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3865856008
Short name T230
Test name
Test status
Simulation time 185278383 ps
CPU time 1.14 seconds
Started Jan 24 01:18:18 PM PST 24
Finished Jan 24 01:19:04 PM PST 24
Peak memory 203284 kb
Host smart-428ea33d-61c6-4e37-9fca-004021fe64e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865856008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3865856008
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.3397370382
Short name T24
Test name
Test status
Simulation time 136799561 ps
CPU time 0.81 seconds
Started Jan 24 01:18:26 PM PST 24
Finished Jan 24 01:19:08 PM PST 24
Peak memory 203284 kb
Host smart-8159778d-0d44-400c-87e8-dab8cb928d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397370382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.3397370382
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.221972525
Short name T18
Test name
Test status
Simulation time 105455171 ps
CPU time 0.95 seconds
Started Jan 24 01:18:26 PM PST 24
Finished Jan 24 01:19:08 PM PST 24
Peak memory 203468 kb
Host smart-56bf0767-263c-4825-8316-213b95227248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221972525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.221972525
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3912940423
Short name T68
Test name
Test status
Simulation time 34672096 ps
CPU time 0.64 seconds
Started Jan 24 01:18:28 PM PST 24
Finished Jan 24 01:19:09 PM PST 24
Peak memory 203492 kb
Host smart-5265ed11-a7e8-436c-a1c0-728cc8aac1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912940423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3912940423
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.591594398
Short name T212
Test name
Test status
Simulation time 1250704402 ps
CPU time 3.71 seconds
Started Jan 24 01:18:10 PM PST 24
Finished Jan 24 01:19:04 PM PST 24
Peak memory 203852 kb
Host smart-5a5d0a84-f21a-429d-998a-891aee54c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591594398 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.591594398
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3571644042
Short name T66
Test name
Test status
Simulation time 286802094 ps
CPU time 1.06 seconds
Started Jan 24 01:18:12 PM PST 24
Finished Jan 24 01:19:01 PM PST 24
Peak memory 203396 kb
Host smart-5f414e27-a559-49bc-8d6d-3599c394b607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571644042 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3571644042
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1631626234
Short name T177
Test name
Test status
Simulation time 52609732 ps
CPU time 0.65 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:41 PM PST 24
Peak memory 203268 kb
Host smart-17afe2c0-5f21-4beb-b5c3-0e8dadb65f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1631626234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1631626234
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.541366447
Short name T187
Test name
Test status
Simulation time 608402787 ps
CPU time 1.35 seconds
Started Jan 24 01:18:30 PM PST 24
Finished Jan 24 01:19:11 PM PST 24
Peak memory 203980 kb
Host smart-2e884b45-0199-4244-be97-b5b7b45f60f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541366447 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.541366447
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4037436628
Short name T6
Test name
Test status
Simulation time 290526681 ps
CPU time 1.51 seconds
Started Jan 24 01:18:27 PM PST 24
Finished Jan 24 01:19:08 PM PST 24
Peak memory 203644 kb
Host smart-01aa6b3e-3929-40ba-ada1-981e377df498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037436628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4037436628
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.770237291
Short name T10
Test name
Test status
Simulation time 109376708 ps
CPU time 0.89 seconds
Started Jan 24 01:18:29 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 203060 kb
Host smart-4719931b-9212-49f0-9f83-9a75e2c12998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770237291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.770237291
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.94780103
Short name T25
Test name
Test status
Simulation time 1175044233 ps
CPU time 2.53 seconds
Started Jan 24 01:18:29 PM PST 24
Finished Jan 24 01:19:12 PM PST 24
Peak memory 203740 kb
Host smart-2a543045-2e98-4ee2-bba6-59634ca70251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94780103 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.94780103
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.154040779
Short name T19
Test name
Test status
Simulation time 233365642 ps
CPU time 0.71 seconds
Started Jan 24 01:18:30 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 203632 kb
Host smart-342c02f6-f7c1-44ea-acbe-6650c3a48f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154040779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.154040779
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3228031179
Short name T186
Test name
Test status
Simulation time 14136773419 ps
CPU time 36.1 seconds
Started Jan 24 01:18:26 PM PST 24
Finished Jan 24 01:19:43 PM PST 24
Peak memory 204048 kb
Host smart-53beba97-bb1c-4137-9099-b683ce7df6a9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3228031179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3228031179
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.718276671
Short name T7
Test name
Test status
Simulation time 611464328 ps
CPU time 2.2 seconds
Started Jan 24 02:33:03 PM PST 24
Finished Jan 24 02:33:40 PM PST 24
Peak memory 203832 kb
Host smart-eb1545c7-6b69-4f7f-afab-4c4c6ab36a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718276671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.718276671
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.1219818554
Short name T78
Test name
Test status
Simulation time 61963715 ps
CPU time 0.82 seconds
Started Jan 24 01:18:30 PM PST 24
Finished Jan 24 01:19:10 PM PST 24
Peak memory 203492 kb
Host smart-df0d5f54-301a-4ac5-bab3-2660fcee1c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219818554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.1219818554
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.3429090445
Short name T32
Test name
Test status
Simulation time 141487791 ps
CPU time 0.73 seconds
Started Jan 24 01:18:44 PM PST 24
Finished Jan 24 01:19:26 PM PST 24
Peak memory 203116 kb
Host smart-9b8ae0c7-c9b5-4c6e-8ddc-14fe5fbe3410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429090445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.3429090445
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1225144250
Short name T17
Test name
Test status
Simulation time 91378215 ps
CPU time 0.81 seconds
Started Jan 24 01:18:49 PM PST 24
Finished Jan 24 01:19:33 PM PST 24
Peak memory 203448 kb
Host smart-acbd4f76-2d9d-47a3-afed-5770f2595196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1225144250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1225144250
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1985292270
Short name T63
Test name
Test status
Simulation time 592510064 ps
CPU time 1.21 seconds
Started Jan 24 01:18:51 PM PST 24
Finished Jan 24 01:19:38 PM PST 24
Peak memory 203672 kb
Host smart-fde120f3-bc17-406c-91ee-f3c7cd094c6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985292270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1985292270
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3704884204
Short name T27
Test name
Test status
Simulation time 55164688 ps
CPU time 0.64 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:41 PM PST 24
Peak memory 203152 kb
Host smart-799e895a-0822-46f3-bda4-2fac7718c7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704884204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3704884204
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.4066048956
Short name T20
Test name
Test status
Simulation time 969221307 ps
CPU time 1.47 seconds
Started Jan 24 01:18:49 PM PST 24
Finished Jan 24 01:19:34 PM PST 24
Peak memory 203824 kb
Host smart-2a3a65f2-cd12-4fab-9182-1a24efdc25d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066048956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.4066048956
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.3946742872
Short name T188
Test name
Test status
Simulation time 8795944651 ps
CPU time 12.51 seconds
Started Jan 24 01:18:31 PM PST 24
Finished Jan 24 01:19:23 PM PST 24
Peak memory 204032 kb
Host smart-c289b7a2-a99b-457b-96b2-39ed9da59dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946742872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.3946742872
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.212254223
Short name T36
Test name
Test status
Simulation time 57657087 ps
CPU time 0.98 seconds
Started Jan 24 01:18:48 PM PST 24
Finished Jan 24 01:19:32 PM PST 24
Peak memory 218644 kb
Host smart-b3353c7a-934e-4cf6-b044-fe72ce3ad7ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212254223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.212254223
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2655947120
Short name T9
Test name
Test status
Simulation time 463893673 ps
CPU time 1.63 seconds
Started Jan 24 01:18:26 PM PST 24
Finished Jan 24 01:19:08 PM PST 24
Peak memory 203448 kb
Host smart-aec2b5df-5d74-499e-9db2-c8b21ab49ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655947120 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2655947120
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.2334415107
Short name T2
Test name
Test status
Simulation time 47666121 ps
CPU time 0.64 seconds
Started Jan 24 01:19:24 PM PST 24
Finished Jan 24 01:20:24 PM PST 24
Peak memory 203620 kb
Host smart-e7ea59d1-5c15-4d6c-b569-05a518999af1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334415107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.2334415107
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1984830945
Short name T23
Test name
Test status
Simulation time 20714298162 ps
CPU time 90.12 seconds
Started Jan 24 01:19:08 PM PST 24
Finished Jan 24 01:21:39 PM PST 24
Peak memory 203996 kb
Host smart-247e8051-f256-4318-88c9-952b3a62b973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984830945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1984830945
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3342615995
Short name T224
Test name
Test status
Simulation time 2465306871 ps
CPU time 3.38 seconds
Started Jan 24 01:19:08 PM PST 24
Finished Jan 24 01:20:12 PM PST 24
Peak memory 203940 kb
Host smart-bb7bdaea-c5c4-4480-aba2-a93040551caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342615995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3342615995
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.4285374300
Short name T28
Test name
Test status
Simulation time 684160392 ps
CPU time 2.09 seconds
Started Jan 24 01:19:14 PM PST 24
Finished Jan 24 01:20:16 PM PST 24
Peak memory 204008 kb
Host smart-f6189ce0-48a6-45b1-96ef-62b31905c929
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285374300 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4285374300
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3392926351
Short name T173
Test name
Test status
Simulation time 25402329 ps
CPU time 0.67 seconds
Started Jan 24 01:19:28 PM PST 24
Finished Jan 24 01:20:30 PM PST 24
Peak memory 203640 kb
Host smart-c38cb64d-084f-4450-9893-546e6a2c81d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392926351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3392926351
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.3212124474
Short name T234
Test name
Test status
Simulation time 39570918485 ps
CPU time 142.94 seconds
Started Jan 24 01:19:28 PM PST 24
Finished Jan 24 01:22:53 PM PST 24
Peak memory 220488 kb
Host smart-0fa748bb-c667-48f9-9bf2-7df280654d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212124474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.3212124474
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.1522025438
Short name T195
Test name
Test status
Simulation time 1553441060 ps
CPU time 4.84 seconds
Started Jan 24 01:19:23 PM PST 24
Finished Jan 24 01:20:28 PM PST 24
Peak memory 203936 kb
Host smart-e7a576bc-e812-4bc9-abc5-af2933187c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522025438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.1522025438
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.814275315
Short name T3
Test name
Test status
Simulation time 1214085809 ps
CPU time 2.97 seconds
Started Jan 24 01:19:22 PM PST 24
Finished Jan 24 01:20:25 PM PST 24
Peak memory 203892 kb
Host smart-163d051f-4ad4-46f0-b253-f099c2b8b9cd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=814275315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.814275315
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.2005170176
Short name T217
Test name
Test status
Simulation time 10483107499 ps
CPU time 29.83 seconds
Started Jan 24 01:19:28 PM PST 24
Finished Jan 24 01:21:00 PM PST 24
Peak memory 204108 kb
Host smart-46c38e21-141c-43a2-b94e-619f38f725ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005170176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.2005170176
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.2750403282
Short name T216
Test name
Test status
Simulation time 31010102 ps
CPU time 0.66 seconds
Started Jan 24 01:19:27 PM PST 24
Finished Jan 24 01:20:29 PM PST 24
Peak memory 203628 kb
Host smart-ac0daa89-de74-4e3c-8337-85cbe6a2b951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750403282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.2750403282
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.2349709492
Short name T148
Test name
Test status
Simulation time 3040016916 ps
CPU time 5.26 seconds
Started Jan 24 01:19:31 PM PST 24
Finished Jan 24 01:20:38 PM PST 24
Peak memory 204016 kb
Host smart-57d3f05c-82ee-4224-8d4e-adbe9d8b4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349709492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.2349709492
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3336396531
Short name T181
Test name
Test status
Simulation time 4029113375 ps
CPU time 13.82 seconds
Started Jan 24 01:19:36 PM PST 24
Finished Jan 24 01:20:51 PM PST 24
Peak memory 204076 kb
Host smart-95292ec4-5020-4e1b-a729-889bf3ae6d5f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3336396531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3336396531
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.481340326
Short name T210
Test name
Test status
Simulation time 3836754235 ps
CPU time 7.44 seconds
Started Jan 24 01:19:21 PM PST 24
Finished Jan 24 01:20:29 PM PST 24
Peak memory 204076 kb
Host smart-1b1b7d5a-807e-4bed-af3a-19876373b10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481340326 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.481340326
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.940160328
Short name T167
Test name
Test status
Simulation time 24188677 ps
CPU time 0.71 seconds
Started Jan 24 01:32:33 PM PST 24
Finished Jan 24 01:33:11 PM PST 24
Peak memory 203620 kb
Host smart-99c5307d-db63-4e5f-88c0-5ff7b6a8448c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940160328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.940160328
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.1750144478
Short name T207
Test name
Test status
Simulation time 11522439826 ps
CPU time 13.72 seconds
Started Jan 24 01:19:44 PM PST 24
Finished Jan 24 01:20:59 PM PST 24
Peak memory 204092 kb
Host smart-d1d9e704-01ff-4554-b425-94718c163ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750144478 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.1750144478
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.1785381531
Short name T220
Test name
Test status
Simulation time 1576985003 ps
CPU time 4.29 seconds
Started Jan 24 02:29:00 PM PST 24
Finished Jan 24 02:29:21 PM PST 24
Peak memory 204032 kb
Host smart-b6dcf0f1-e1eb-4a73-87e5-6e57a0bae582
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1785381531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.1785381531
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3359486832
Short name T199
Test name
Test status
Simulation time 4718536571 ps
CPU time 16.02 seconds
Started Jan 24 01:19:32 PM PST 24
Finished Jan 24 01:20:49 PM PST 24
Peak memory 204028 kb
Host smart-f7341811-d0d0-4d30-9ea4-373d4fb26ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359486832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3359486832
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2715966534
Short name T219
Test name
Test status
Simulation time 581471312 ps
CPU time 1.85 seconds
Started Jan 24 01:19:31 PM PST 24
Finished Jan 24 01:20:35 PM PST 24
Peak memory 203860 kb
Host smart-da4e9386-7ee7-4205-b02f-00e1f1144f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715966534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2715966534
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.2292919567
Short name T211
Test name
Test status
Simulation time 6763816963 ps
CPU time 21.14 seconds
Started Jan 24 01:19:32 PM PST 24
Finished Jan 24 01:20:55 PM PST 24
Peak memory 203976 kb
Host smart-e7669738-cfc2-4e92-b6a0-329f3609e330
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2292919567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.2292919567
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1834269203
Short name T94
Test name
Test status
Simulation time 5065100452 ps
CPU time 11.15 seconds
Started Jan 24 01:19:31 PM PST 24
Finished Jan 24 01:20:44 PM PST 24
Peak memory 203912 kb
Host smart-4f182527-cef3-4e46-8677-c4cd09ec37f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834269203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1834269203
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.448231117
Short name T145
Test name
Test status
Simulation time 111947867 ps
CPU time 0.65 seconds
Started Jan 24 01:19:47 PM PST 24
Finished Jan 24 01:20:49 PM PST 24
Peak memory 203488 kb
Host smart-f9a561ce-959e-4e3a-9e02-352b21eda5d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448231117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.448231117
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.3888960295
Short name T14
Test name
Test status
Simulation time 7873508752 ps
CPU time 13.48 seconds
Started Jan 24 01:19:42 PM PST 24
Finished Jan 24 01:20:58 PM PST 24
Peak memory 204092 kb
Host smart-205def9c-e2a6-4955-a17a-294fb1516d0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888960295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.3888960295
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2543169668
Short name T200
Test name
Test status
Simulation time 1887456660 ps
CPU time 4.98 seconds
Started Jan 24 01:19:32 PM PST 24
Finished Jan 24 01:20:39 PM PST 24
Peak memory 203972 kb
Host smart-8c8f21c1-fd5d-4dc5-a8af-ef4b62bf556d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2543169668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2543169668
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.165819456
Short name T183
Test name
Test status
Simulation time 5522876271 ps
CPU time 8.57 seconds
Started Jan 24 01:19:35 PM PST 24
Finished Jan 24 01:20:46 PM PST 24
Peak memory 204068 kb
Host smart-d5a47353-4e6a-422e-9d3b-ff4ed5f06e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165819456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.165819456
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.4019231311
Short name T77
Test name
Test status
Simulation time 32477505 ps
CPU time 0.65 seconds
Started Jan 24 01:19:42 PM PST 24
Finished Jan 24 01:20:45 PM PST 24
Peak memory 203600 kb
Host smart-89a3c453-a1df-42ae-b6f1-c96e841a673e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019231311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.4019231311
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1977334090
Short name T222
Test name
Test status
Simulation time 41701108090 ps
CPU time 67.1 seconds
Started Jan 24 01:19:47 PM PST 24
Finished Jan 24 01:21:55 PM PST 24
Peak memory 203920 kb
Host smart-ced2bbc9-afd6-40f6-ae92-4808b66a96f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977334090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1977334090
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.3403464888
Short name T191
Test name
Test status
Simulation time 1832124032 ps
CPU time 4.55 seconds
Started Jan 24 01:19:46 PM PST 24
Finished Jan 24 01:20:52 PM PST 24
Peak memory 204008 kb
Host smart-2280bb2c-7233-4608-97ad-e5bc01c1f7f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403464888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.3403464888
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.230504317
Short name T11
Test name
Test status
Simulation time 2184350866 ps
CPU time 5.69 seconds
Started Jan 24 01:19:41 PM PST 24
Finished Jan 24 01:20:50 PM PST 24
Peak memory 203888 kb
Host smart-fa145174-c6c4-45c1-abb4-e6af059b1af6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=230504317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_t
l_access.230504317
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2895994835
Short name T193
Test name
Test status
Simulation time 1582415020 ps
CPU time 7.07 seconds
Started Jan 24 01:19:40 PM PST 24
Finished Jan 24 01:20:50 PM PST 24
Peak memory 203856 kb
Host smart-2221a2d7-65b4-4e0e-951f-3562a3d46fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895994835 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2895994835
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.2008577600
Short name T157
Test name
Test status
Simulation time 31967667 ps
CPU time 0.71 seconds
Started Jan 24 01:19:55 PM PST 24
Finished Jan 24 01:20:58 PM PST 24
Peak memory 203480 kb
Host smart-3ac974a5-4dc6-4770-8948-faa22d3994b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008577600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.2008577600
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3826020227
Short name T76
Test name
Test status
Simulation time 1105086322 ps
CPU time 2.24 seconds
Started Jan 24 01:19:55 PM PST 24
Finished Jan 24 01:20:59 PM PST 24
Peak memory 203844 kb
Host smart-ebbf932e-999e-4b8d-b683-31773fa02205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826020227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3826020227
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.3443656874
Short name T182
Test name
Test status
Simulation time 2755842227 ps
CPU time 2.06 seconds
Started Jan 24 01:19:54 PM PST 24
Finished Jan 24 01:20:59 PM PST 24
Peak memory 203996 kb
Host smart-d51686ee-11eb-4071-bd95-c0f238351f86
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3443656874 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.3443656874
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.608340289
Short name T232
Test name
Test status
Simulation time 986080345 ps
CPU time 1.38 seconds
Started Jan 24 01:19:54 PM PST 24
Finished Jan 24 01:20:58 PM PST 24
Peak memory 203884 kb
Host smart-c315e4a4-12be-456d-b5ed-5f31ef7f5d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608340289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.608340289
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2189621559
Short name T16
Test name
Test status
Simulation time 1733929625 ps
CPU time 2.97 seconds
Started Jan 24 01:19:47 PM PST 24
Finished Jan 24 01:20:51 PM PST 24
Peak memory 203740 kb
Host smart-b45d3b4b-834b-4e8d-9b36-c239574dae9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189621559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2189621559
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1798705676
Short name T161
Test name
Test status
Simulation time 64091953 ps
CPU time 0.63 seconds
Started Jan 24 01:20:00 PM PST 24
Finished Jan 24 01:21:04 PM PST 24
Peak memory 203428 kb
Host smart-56102cb5-dfb6-412b-9038-45d22c9d1da3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798705676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1798705676
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2147910062
Short name T231
Test name
Test status
Simulation time 14426715376 ps
CPU time 36.47 seconds
Started Jan 24 02:13:56 PM PST 24
Finished Jan 24 02:14:38 PM PST 24
Peak memory 204048 kb
Host smart-6933ccfe-ac21-44a1-8af7-86a45f8b9cbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147910062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2147910062
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3851057403
Short name T95
Test name
Test status
Simulation time 4570126419 ps
CPU time 15.65 seconds
Started Jan 24 01:19:41 PM PST 24
Finished Jan 24 01:21:00 PM PST 24
Peak memory 204096 kb
Host smart-c693ede6-69dd-492f-a46c-47cb51b6ede5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851057403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3851057403
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1899147464
Short name T233
Test name
Test status
Simulation time 2542828314 ps
CPU time 12.78 seconds
Started Jan 24 01:19:42 PM PST 24
Finished Jan 24 01:20:57 PM PST 24
Peak memory 204040 kb
Host smart-7575c1be-339f-4385-a4c8-ed63611a615c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899147464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1899147464
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.4255459374
Short name T209
Test name
Test status
Simulation time 834989402 ps
CPU time 3.74 seconds
Started Jan 24 01:19:55 PM PST 24
Finished Jan 24 01:21:01 PM PST 24
Peak memory 203876 kb
Host smart-53c6ea58-20b3-4575-ab4b-65640c034beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255459374 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.4255459374
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.3685980082
Short name T169
Test name
Test status
Simulation time 115353526 ps
CPU time 0.66 seconds
Started Jan 24 01:20:07 PM PST 24
Finished Jan 24 01:21:13 PM PST 24
Peak memory 203640 kb
Host smart-36abe22a-bb64-4541-8de9-fac0fa3b292c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685980082 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.3685980082
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.3222648707
Short name T202
Test name
Test status
Simulation time 13841855581 ps
CPU time 44.33 seconds
Started Jan 24 01:20:09 PM PST 24
Finished Jan 24 01:21:59 PM PST 24
Peak memory 203980 kb
Host smart-260fa406-f489-4e66-bfff-473e42c94f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222648707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.3222648707
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.602287087
Short name T12
Test name
Test status
Simulation time 11277831204 ps
CPU time 36.54 seconds
Started Jan 24 02:06:08 PM PST 24
Finished Jan 24 02:07:34 PM PST 24
Peak memory 204052 kb
Host smart-1f078c0b-6cbd-46be-901c-abaea75ed8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602287087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.602287087
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.1701793288
Short name T204
Test name
Test status
Simulation time 11151764064 ps
CPU time 37.25 seconds
Started Jan 24 01:19:51 PM PST 24
Finished Jan 24 01:21:29 PM PST 24
Peak memory 204048 kb
Host smart-12cb6a93-42e3-4633-8216-26b5135c34ba
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1701793288 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.1701793288
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.334376694
Short name T198
Test name
Test status
Simulation time 5266260897 ps
CPU time 9.56 seconds
Started Jan 24 01:48:12 PM PST 24
Finished Jan 24 01:48:28 PM PST 24
Peak memory 204028 kb
Host smart-d46a6422-e0a9-4bfa-b2d8-0419dff2b060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334376694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.334376694
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2781176036
Short name T75
Test name
Test status
Simulation time 51335035 ps
CPU time 0.65 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:40 PM PST 24
Peak memory 203424 kb
Host smart-3d2bea75-c948-4d16-bfa5-0f7ee8ced41d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781176036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2781176036
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3920967276
Short name T190
Test name
Test status
Simulation time 2914957152 ps
CPU time 5.39 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:45 PM PST 24
Peak memory 203852 kb
Host smart-22984214-ac1e-43e5-aaee-c3aa2265765e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920967276 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3920967276
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1939705480
Short name T225
Test name
Test status
Simulation time 69611583 ps
CPU time 0.75 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:41 PM PST 24
Peak memory 203452 kb
Host smart-e44e0f67-b294-43a4-99d4-1167db2efae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939705480 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1939705480
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1689441935
Short name T70
Test name
Test status
Simulation time 4084437414 ps
CPU time 4.76 seconds
Started Jan 24 01:18:46 PM PST 24
Finished Jan 24 01:19:32 PM PST 24
Peak memory 204028 kb
Host smart-add7fbc9-e9f6-4574-835d-3d287cdd03ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689441935 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1689441935
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3472911679
Short name T37
Test name
Test status
Simulation time 95437783 ps
CPU time 1.08 seconds
Started Jan 24 01:18:46 PM PST 24
Finished Jan 24 01:19:29 PM PST 24
Peak memory 219560 kb
Host smart-0da59dac-9b1d-49b4-a57e-1e685f67001f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472911679 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3472911679
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.7117221
Short name T175
Test name
Test status
Simulation time 25049883 ps
CPU time 0.67 seconds
Started Jan 24 01:20:11 PM PST 24
Finished Jan 24 01:21:17 PM PST 24
Peak memory 203616 kb
Host smart-7b495cf7-853e-4b11-b21c-0f3f1df24937
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7117221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.7117221
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1917742523
Short name T196
Test name
Test status
Simulation time 27955473 ps
CPU time 0.7 seconds
Started Jan 24 01:20:11 PM PST 24
Finished Jan 24 01:21:17 PM PST 24
Peak memory 203528 kb
Host smart-3409c44c-9e51-438a-bbb6-c11ddc74e5da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917742523 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1917742523
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.1869897559
Short name T156
Test name
Test status
Simulation time 32428545 ps
CPU time 0.66 seconds
Started Jan 24 01:20:10 PM PST 24
Finished Jan 24 01:21:16 PM PST 24
Peak memory 202724 kb
Host smart-f97df027-d2bd-4893-87b4-f9af57c4eebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869897559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.1869897559
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4005221519
Short name T86
Test name
Test status
Simulation time 18953363 ps
CPU time 0.66 seconds
Started Jan 24 01:20:09 PM PST 24
Finished Jan 24 01:21:14 PM PST 24
Peak memory 203608 kb
Host smart-c2d627e4-6a54-40f7-b954-0df79f1ba1c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005221519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4005221519
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_stress_all.3882866128
Short name T97
Test name
Test status
Simulation time 2282678430 ps
CPU time 2.22 seconds
Started Jan 24 01:20:09 PM PST 24
Finished Jan 24 01:21:16 PM PST 24
Peak memory 203904 kb
Host smart-e30b6741-2975-498f-99fe-40151241b241
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882866128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.3882866128
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.909287998
Short name T162
Test name
Test status
Simulation time 49188778 ps
CPU time 0.66 seconds
Started Jan 24 01:31:38 PM PST 24
Finished Jan 24 01:32:30 PM PST 24
Peak memory 203564 kb
Host smart-1af768d0-bc65-4aad-9aeb-8061312afb7a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909287998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.909287998
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.2338112061
Short name T159
Test name
Test status
Simulation time 21572864 ps
CPU time 0.66 seconds
Started Jan 24 01:28:56 PM PST 24
Finished Jan 24 01:29:14 PM PST 24
Peak memory 203624 kb
Host smart-53bb7899-9fda-493d-91d7-91e41643fd71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338112061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.2338112061
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1173897394
Short name T155
Test name
Test status
Simulation time 24262225 ps
CPU time 0.65 seconds
Started Jan 24 01:20:09 PM PST 24
Finished Jan 24 01:21:14 PM PST 24
Peak memory 203608 kb
Host smart-372ef0c5-aabd-4010-9567-23d30b5dab6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173897394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1173897394
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.1231222683
Short name T53
Test name
Test status
Simulation time 46774735 ps
CPU time 0.64 seconds
Started Jan 24 01:32:01 PM PST 24
Finished Jan 24 01:32:50 PM PST 24
Peak memory 203412 kb
Host smart-ae5da92e-6f0a-4ccd-a341-d52065aef80d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231222683 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.1231222683
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.2074107231
Short name T49
Test name
Test status
Simulation time 55895251 ps
CPU time 0.62 seconds
Started Jan 24 01:20:16 PM PST 24
Finished Jan 24 01:21:24 PM PST 24
Peak memory 203484 kb
Host smart-080105bd-51d3-4a57-8cb7-9fac41790768
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074107231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.2074107231
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.4245423669
Short name T47
Test name
Test status
Simulation time 52112353 ps
CPU time 0.65 seconds
Started Jan 24 01:25:26 PM PST 24
Finished Jan 24 01:26:17 PM PST 24
Peak memory 203604 kb
Host smart-c92b9318-8490-46b0-80cc-73e2e03dd5ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245423669 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.4245423669
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.517485244
Short name T176
Test name
Test status
Simulation time 32979198 ps
CPU time 0.64 seconds
Started Jan 24 01:18:45 PM PST 24
Finished Jan 24 01:19:27 PM PST 24
Peak memory 203536 kb
Host smart-a4a46db7-2afe-41be-aff5-dd743d203416
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517485244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.517485244
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.923573297
Short name T147
Test name
Test status
Simulation time 1944656454 ps
CPU time 8.59 seconds
Started Jan 24 01:18:49 PM PST 24
Finished Jan 24 01:19:40 PM PST 24
Peak memory 203996 kb
Host smart-3c54460b-bbef-4b4b-ac3a-0d9f2fcd6f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923573297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.923573297
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.567024313
Short name T185
Test name
Test status
Simulation time 611738052 ps
CPU time 3.09 seconds
Started Jan 24 01:18:51 PM PST 24
Finished Jan 24 01:19:40 PM PST 24
Peak memory 203980 kb
Host smart-44c4c0fd-10f7-4fb6-b21b-ca9790525e30
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=567024313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_tl
_access.567024313
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.3131673401
Short name T21
Test name
Test status
Simulation time 67214420 ps
CPU time 0.82 seconds
Started Jan 24 01:18:51 PM PST 24
Finished Jan 24 01:19:37 PM PST 24
Peak memory 203480 kb
Host smart-1c33589e-3ffc-4f67-a018-829d5e0ec172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131673401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.3131673401
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1959679395
Short name T184
Test name
Test status
Simulation time 2083162767 ps
CPU time 5.22 seconds
Started Jan 24 01:18:48 PM PST 24
Finished Jan 24 01:19:36 PM PST 24
Peak memory 203972 kb
Host smart-2c628a96-1966-47e4-a158-94e373f73eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959679395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1959679395
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3953778630
Short name T35
Test name
Test status
Simulation time 281748007 ps
CPU time 1.09 seconds
Started Jan 24 01:18:54 PM PST 24
Finished Jan 24 01:19:44 PM PST 24
Peak memory 219836 kb
Host smart-74522463-c49c-4eaf-88f4-b324dcd73076
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953778630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3953778630
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.2832680628
Short name T192
Test name
Test status
Simulation time 110764903 ps
CPU time 0.64 seconds
Started Jan 24 01:20:17 PM PST 24
Finished Jan 24 01:21:26 PM PST 24
Peak memory 203488 kb
Host smart-ce15b9d3-0e25-44a5-9f54-77db37a8a067
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832680628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.2832680628
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2973871003
Short name T170
Test name
Test status
Simulation time 56644263 ps
CPU time 0.66 seconds
Started Jan 24 01:20:19 PM PST 24
Finished Jan 24 01:21:29 PM PST 24
Peak memory 203588 kb
Host smart-81954355-a56b-460d-b444-58b0ef87a1b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973871003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2973871003
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.3194128080
Short name T154
Test name
Test status
Simulation time 25664882 ps
CPU time 0.68 seconds
Started Jan 24 01:20:29 PM PST 24
Finished Jan 24 01:21:40 PM PST 24
Peak memory 203628 kb
Host smart-e2378880-06a1-455a-9179-2a39986a999f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194128080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.3194128080
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.2697256312
Short name T168
Test name
Test status
Simulation time 147565896 ps
CPU time 0.68 seconds
Started Jan 24 01:20:23 PM PST 24
Finished Jan 24 01:21:34 PM PST 24
Peak memory 203620 kb
Host smart-8682aee3-1c8d-4c4a-8260-5e0c42c90074
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697256312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.2697256312
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.2180508030
Short name T178
Test name
Test status
Simulation time 17634824 ps
CPU time 0.65 seconds
Started Jan 24 01:20:27 PM PST 24
Finished Jan 24 01:21:39 PM PST 24
Peak memory 203536 kb
Host smart-fb599c3e-a4ab-499e-a51e-178e40c65dd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180508030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.2180508030
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.3584358063
Short name T214
Test name
Test status
Simulation time 52785233 ps
CPU time 0.65 seconds
Started Jan 24 01:20:41 PM PST 24
Finished Jan 24 01:21:52 PM PST 24
Peak memory 203596 kb
Host smart-c1daa83d-4a39-431f-bcb3-decc418f17fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584358063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.3584358063
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.307046497
Short name T174
Test name
Test status
Simulation time 25745401 ps
CPU time 0.64 seconds
Started Jan 24 01:20:42 PM PST 24
Finished Jan 24 01:21:54 PM PST 24
Peak memory 203616 kb
Host smart-61464e4d-2221-4721-9aae-7aacf93114d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307046497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.307046497
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.226733845
Short name T164
Test name
Test status
Simulation time 48518617 ps
CPU time 0.63 seconds
Started Jan 24 01:20:40 PM PST 24
Finished Jan 24 01:21:52 PM PST 24
Peak memory 203620 kb
Host smart-15ab0928-2a8f-41ce-aac8-ec3d09e72ee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226733845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.226733845
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.2029448805
Short name T34
Test name
Test status
Simulation time 17579106 ps
CPU time 0.69 seconds
Started Jan 24 01:20:32 PM PST 24
Finished Jan 24 01:21:44 PM PST 24
Peak memory 203608 kb
Host smart-dbd77a3b-6123-4aa7-9af9-077e4c10570b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029448805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.2029448805
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2826166655
Short name T50
Test name
Test status
Simulation time 32534556 ps
CPU time 0.68 seconds
Started Jan 24 01:20:37 PM PST 24
Finished Jan 24 01:21:47 PM PST 24
Peak memory 203604 kb
Host smart-b2de6742-169c-4ac3-a406-02ce4374db39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826166655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2826166655
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2962261096
Short name T163
Test name
Test status
Simulation time 23963826 ps
CPU time 0.68 seconds
Started Jan 24 03:29:47 PM PST 24
Finished Jan 24 03:29:49 PM PST 24
Peak memory 203636 kb
Host smart-8b4e1a66-c5d6-4f57-940c-2efe47152e5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962261096 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2962261096
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.622991131
Short name T22
Test name
Test status
Simulation time 18026942964 ps
CPU time 82.09 seconds
Started Jan 24 01:18:49 PM PST 24
Finished Jan 24 01:20:54 PM PST 24
Peak memory 204000 kb
Host smart-e23c0002-72ac-4ffb-9795-d6bc561e1612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622991131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.622991131
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2043540464
Short name T146
Test name
Test status
Simulation time 2032834641 ps
CPU time 3.85 seconds
Started Jan 24 01:18:51 PM PST 24
Finished Jan 24 01:19:40 PM PST 24
Peak memory 204024 kb
Host smart-933dadad-e9f4-4ca5-a5d9-99f8bc2ee834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043540464 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2043540464
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1679878580
Short name T203
Test name
Test status
Simulation time 5923336069 ps
CPU time 3.63 seconds
Started Jan 24 01:18:43 PM PST 24
Finished Jan 24 01:19:26 PM PST 24
Peak memory 204116 kb
Host smart-018ac132-0659-4ebd-af5b-cc20af518b73
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1679878580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1679878580
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.2053036768
Short name T74
Test name
Test status
Simulation time 68837756 ps
CPU time 0.66 seconds
Started Jan 24 01:18:49 PM PST 24
Finished Jan 24 01:19:32 PM PST 24
Peak memory 203204 kb
Host smart-6dc16a16-f22c-4850-892d-6a197534d1eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053036768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.2053036768
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.1407304006
Short name T93
Test name
Test status
Simulation time 2016171063 ps
CPU time 3.56 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:43 PM PST 24
Peak memory 203800 kb
Host smart-8dbd2c46-992b-4237-8a7b-f62843d711cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407304006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.1407304006
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.4224790589
Short name T73
Test name
Test status
Simulation time 254563513 ps
CPU time 1.02 seconds
Started Jan 24 01:18:53 PM PST 24
Finished Jan 24 01:19:41 PM PST 24
Peak memory 219568 kb
Host smart-9249d781-bf00-4e3b-8a2c-85dd96eea249
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224790589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.4224790589
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.3775672090
Short name T223
Test name
Test status
Simulation time 52067068 ps
CPU time 0.64 seconds
Started Jan 24 01:20:37 PM PST 24
Finished Jan 24 01:21:48 PM PST 24
Peak memory 203604 kb
Host smart-428ec1ed-b72b-412f-b79b-f72f33e6406e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775672090 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.3775672090
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3655917651
Short name T189
Test name
Test status
Simulation time 27249688 ps
CPU time 0.66 seconds
Started Jan 24 01:20:42 PM PST 24
Finished Jan 24 01:21:53 PM PST 24
Peak memory 203588 kb
Host smart-117cdf5c-6057-45d1-a84d-f7a5c66899ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655917651 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3655917651
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.2389170908
Short name T153
Test name
Test status
Simulation time 26387767 ps
CPU time 0.65 seconds
Started Jan 24 01:20:44 PM PST 24
Finished Jan 24 01:21:55 PM PST 24
Peak memory 203652 kb
Host smart-2d4c882b-d4f7-4baf-86bf-7355a46c8491
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389170908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.2389170908
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1845593832
Short name T51
Test name
Test status
Simulation time 53495437 ps
CPU time 0.61 seconds
Started Jan 24 01:20:41 PM PST 24
Finished Jan 24 01:21:53 PM PST 24
Peak memory 203568 kb
Host smart-fceaf1f6-b40e-44a9-9524-e39d9b9c83c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845593832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1845593832
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.2279987474
Short name T33
Test name
Test status
Simulation time 26623616 ps
CPU time 0.64 seconds
Started Jan 24 01:20:42 PM PST 24
Finished Jan 24 01:21:53 PM PST 24
Peak memory 203608 kb
Host smart-c53b6b94-2b0c-4510-8d07-19341442ab3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279987474 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.2279987474
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2346440824
Short name T52
Test name
Test status
Simulation time 20904967 ps
CPU time 0.66 seconds
Started Jan 24 01:20:48 PM PST 24
Finished Jan 24 01:22:00 PM PST 24
Peak memory 203600 kb
Host smart-9b042645-0779-41b7-97fa-cfcbde0f2325
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346440824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2346440824
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.3656928524
Short name T79
Test name
Test status
Simulation time 61819846 ps
CPU time 0.63 seconds
Started Jan 24 01:21:00 PM PST 24
Finished Jan 24 01:22:10 PM PST 24
Peak memory 203636 kb
Host smart-fba2c18c-dee9-4f0f-ada4-63a3039c929f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656928524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.3656928524
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.3377994520
Short name T158
Test name
Test status
Simulation time 18127222 ps
CPU time 0.65 seconds
Started Jan 24 01:21:04 PM PST 24
Finished Jan 24 01:22:12 PM PST 24
Peak memory 203604 kb
Host smart-2d65dbde-57bf-48e5-9432-1f52f5def02e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3377994520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.3377994520
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.401020454
Short name T179
Test name
Test status
Simulation time 22067015 ps
CPU time 0.68 seconds
Started Jan 24 01:21:13 PM PST 24
Finished Jan 24 01:22:20 PM PST 24
Peak memory 203600 kb
Host smart-a337c913-ce8e-489a-8d9f-d1336054bb48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401020454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.401020454
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.472402977
Short name T160
Test name
Test status
Simulation time 29446694 ps
CPU time 0.63 seconds
Started Jan 24 01:19:01 PM PST 24
Finished Jan 24 01:19:58 PM PST 24
Peak memory 203620 kb
Host smart-a8f18030-a42a-4b1b-b9a8-dfbfc3385146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472402977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.472402977
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.771368858
Short name T215
Test name
Test status
Simulation time 1961029428 ps
CPU time 6.05 seconds
Started Jan 24 02:23:17 PM PST 24
Finished Jan 24 02:23:40 PM PST 24
Peak memory 203992 kb
Host smart-88238164-62ea-4f12-87b4-80b6d0b72c9d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=771368858 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl
_access.771368858
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.483278579
Short name T227
Test name
Test status
Simulation time 2113385417 ps
CPU time 5.64 seconds
Started Jan 24 01:19:00 PM PST 24
Finished Jan 24 01:20:00 PM PST 24
Peak memory 203960 kb
Host smart-83b50330-a435-4071-81bb-61e8bf307398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483278579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.483278579
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3450158344
Short name T171
Test name
Test status
Simulation time 181710069 ps
CPU time 0.62 seconds
Started Jan 24 01:19:02 PM PST 24
Finished Jan 24 01:19:58 PM PST 24
Peak memory 202448 kb
Host smart-ef59d51a-1498-4370-9efc-8e57f8c11391
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3450158344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3450158344
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.1173923621
Short name T229
Test name
Test status
Simulation time 4175199774 ps
CPU time 5.23 seconds
Started Jan 24 01:53:05 PM PST 24
Finished Jan 24 01:53:21 PM PST 24
Peak memory 204104 kb
Host smart-fe392407-bb0a-44ce-aa86-77f105a0edf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173923621 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.1173923621
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2767069433
Short name T201
Test name
Test status
Simulation time 3979343022 ps
CPU time 8 seconds
Started Jan 24 01:22:27 PM PST 24
Finished Jan 24 01:23:32 PM PST 24
Peak memory 204088 kb
Host smart-44ffe79b-c58d-461a-afc2-c41953911992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767069433 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2767069433
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.154696504
Short name T206
Test name
Test status
Simulation time 3151456218 ps
CPU time 4.67 seconds
Started Jan 24 01:18:59 PM PST 24
Finished Jan 24 01:19:56 PM PST 24
Peak memory 204076 kb
Host smart-8251ae1b-186d-44b6-b00b-b101f52d8c8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154696504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.154696504
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.737510810
Short name T71
Test name
Test status
Simulation time 2688916377 ps
CPU time 9.34 seconds
Started Jan 24 01:18:55 PM PST 24
Finished Jan 24 01:19:55 PM PST 24
Peak memory 204068 kb
Host smart-9d90d1bf-8585-43d9-ac64-7051dd806ccc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=737510810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.737510810
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1197838280
Short name T96
Test name
Test status
Simulation time 10753014692 ps
CPU time 21.07 seconds
Started Jan 24 01:19:03 PM PST 24
Finished Jan 24 01:20:23 PM PST 24
Peak memory 204036 kb
Host smart-2a8371bd-dc93-4567-9215-6c702c5c841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197838280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1197838280
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.4126225137
Short name T205
Test name
Test status
Simulation time 19877827 ps
CPU time 0.73 seconds
Started Jan 24 01:19:14 PM PST 24
Finished Jan 24 01:20:15 PM PST 24
Peak memory 203596 kb
Host smart-93686d25-acfe-47ae-8e82-60f1320ada13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126225137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.4126225137
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_autoincr_sba_tl_access.95023578
Short name T213
Test name
Test status
Simulation time 27773658734 ps
CPU time 82.39 seconds
Started Jan 24 01:19:09 PM PST 24
Finished Jan 24 01:21:32 PM PST 24
Peak memory 204052 kb
Host smart-d27daf2c-91b8-4e95-895e-857497a293d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95023578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_autoincr_sba_tl_access.95023578
Directory /workspace/8.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.3009597356
Short name T218
Test name
Test status
Simulation time 4228148580 ps
CPU time 12.22 seconds
Started Jan 24 01:19:08 PM PST 24
Finished Jan 24 01:20:21 PM PST 24
Peak memory 203968 kb
Host smart-f1f85571-a945-4b81-87d3-25dedfbd3b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009597356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.3009597356
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1715504296
Short name T228
Test name
Test status
Simulation time 2353040489 ps
CPU time 3.88 seconds
Started Jan 24 01:28:38 PM PST 24
Finished Jan 24 01:29:04 PM PST 24
Peak memory 204096 kb
Host smart-68f05add-f53d-4ada-b8c1-b3be5467b56f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1715504296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1715504296
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.720324073
Short name T208
Test name
Test status
Simulation time 1341633068 ps
CPU time 4.52 seconds
Started Jan 24 01:19:14 PM PST 24
Finished Jan 24 01:20:18 PM PST 24
Peak memory 203952 kb
Host smart-0bdef420-f535-439b-ba5c-9b5e603e2fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720324073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.720324073
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2113261372
Short name T194
Test name
Test status
Simulation time 19396658 ps
CPU time 0.67 seconds
Started Jan 24 01:19:08 PM PST 24
Finished Jan 24 01:20:09 PM PST 24
Peak memory 203492 kb
Host smart-951422dd-fbdf-41ee-97db-9e53a02eed85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113261372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2113261372
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.4145559521
Short name T221
Test name
Test status
Simulation time 3862185158 ps
CPU time 10.88 seconds
Started Jan 24 01:56:25 PM PST 24
Finished Jan 24 01:56:39 PM PST 24
Peak memory 204040 kb
Host smart-4333d009-dfc0-4839-a551-a967fcf0de61
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4145559521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.4145559521
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.531573179
Short name T226
Test name
Test status
Simulation time 631275411 ps
CPU time 2.43 seconds
Started Jan 24 01:19:09 PM PST 24
Finished Jan 24 01:20:13 PM PST 24
Peak memory 204024 kb
Host smart-a6cb219c-f8f0-49eb-9fcc-9d35444503ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531573179 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.531573179
Directory /workspace/9.rv_dm_sba_tl_access/latest
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