4ddd81322f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V1 | jtag_dtm_csr_hw_reset | rv_dm_jtag_dtm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_rw | rv_dm_jtag_dtm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dtm_csr_bit_bash | rv_dm_jtag_dtm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dtm_csr_aliasing | rv_dm_jtag_dtm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_hw_reset | rv_dm_jtag_dmi_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_rw | rv_dm_jtag_dmi_csr_rw | 0 | 20 | 0.00 | ||
| V1 | jtag_dmi_csr_bit_bash | rv_dm_jtag_dmi_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_csr_aliasing | rv_dm_jtag_dmi_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | jtag_dmi_cmderr_busy | rv_dm_cmderr_busy | 0 | 2 | 0.00 | ||
| V1 | jtag_dmi_cmderr_not_supported | rv_dm_cmderr_not_supported | 0 | 2 | 0.00 | ||
| V1 | cmderr_exception | rv_dm_cmderr_exception | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_resuming | rv_dm_mem_tl_access_resuming | 0 | 2 | 0.00 | ||
| V1 | mem_tl_access_halted | rv_dm_mem_tl_access_halted | 0 | 2 | 0.00 | ||
| V1 | cmderr_halt_resume | rv_dm_cmderr_halt_resume | 0 | 2 | 0.00 | ||
| V1 | dataaddr_rw_access | rv_dm_dataaddr_rw_access | 0 | 2 | 0.00 | ||
| V1 | halt_resume | rv_dm_halt_resume_whereto | 0 | 2 | 0.00 | ||
| V1 | csr_hw_reset | rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||
| V1 | csr_rw | rv_dm_csr_rw | 0 | 20 | 0.00 | ||
| V1 | csr_bit_bash | rv_dm_csr_bit_bash | 0 | 5 | 0.00 | ||
| V1 | csr_aliasing | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| V1 | csr_mem_rw_with_rand_reset | rv_dm_csr_mem_rw_with_rand_reset | 0 | 20 | 0.00 | ||
| V1 | regwen_csr_and_corresponding_lockable_csr | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| V1 | mem_walk | rv_dm_mem_walk | 0 | 5 | 0.00 | ||
| V1 | mem_partial_access | rv_dm_mem_partial_access | 0 | 5 | 0.00 | ||
| V1 | TOTAL | 0 | 153 | 0.00 | |||
| V2 | idcode | rv_dm_smoke | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_hard_reset | rv_dm_jtag_dtm_hard_reset | 0 | 2 | 0.00 | ||
| V2 | jtag_dtm_idle_hint | rv_dm_jtag_dtm_idle_hint | 0 | 2 | 0.00 | ||
| V2 | jtag_dmi_failed_op | jtag_dmi_failed_op | 0 | 0 | -- | ||
| V2 | jtag_dmi_dm_inactive | rv_dm_jtag_dmi_dm_inactive | 0 | 2 | 0.00 | ||
| V2 | sba | rv_dm_sba_tl_access | 0 | 20 | 0.00 | ||
| rv_dm_delayed_resp_sba_tl_access | 0 | 20 | 0.00 | ||||
| V2 | bad_sba | rv_dm_bad_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | sba_autoincrement | rv_dm_autoincr_sba_tl_access | 0 | 20 | 0.00 | ||
| V2 | jtag_dmi_debug_disabled | rv_dm_jtag_dmi_debug_disabled | 0 | 2 | 0.00 | ||
| V2 | sba_debug_disabled | sba_debug_disabled | 0 | 0 | -- | ||
| V2 | ndmreset_req | rv_dm_ndmreset_req | 0 | 2 | 0.00 | ||
| V2 | hart_unavail | rv_dm_hart_unavail | 0 | 5 | 0.00 | ||
| V2 | tap_ctrl_transitions | rv_dm_tap_fsm | 0 | 1 | 0.00 | ||
| rv_dm_tap_fsm_rand_reset | 0 | 40 | 0.00 | ||||
| V2 | stress_all | rv_dm_stress_all | 0 | 50 | 0.00 | ||
| V2 | alert_test | rv_dm_alert_test | 0 | 50 | 0.00 | ||
| V2 | tl_d_oob_addr_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_illegal_access | rv_dm_tl_errors | 0 | 20 | 0.00 | ||
| V2 | tl_d_outstanding_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | tl_d_partial_access | rv_dm_csr_aliasing | 0 | 5 | 0.00 | ||
| rv_dm_csr_hw_reset | 0 | 5 | 0.00 | ||||
| rv_dm_csr_rw | 0 | 20 | 0.00 | ||||
| rv_dm_same_csr_outstanding | 0 | 20 | 0.00 | ||||
| V2 | TOTAL | 0 | 276 | 0.00 | |||
| V2S | tl_intg_err | rv_dm_sec_cm | 0 | 5 | 0.00 | ||
| rv_dm_tl_intg_err | 0 | 20 | 0.00 | ||||
| V2S | sec_cm_bus_integrity | sec_cm_bus_integrity | 0 | 0 | -- | ||
| V2S | sec_cm_lc_hw_debug_en_intersig_mubi | sec_cm_lc_hw_debug_en_intersig_mubi | 0 | 0 | -- | ||
| V2S | sec_cm_dm_en_ctrl_lc_gated | sec_cm_dm_en_ctrl_lc_gated | 0 | 0 | -- | ||
| V2S | sec_cm_sba_tl_lc_gate_fsm_sparse | sec_cm_sba_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_mem_tl_lc_gate_fsm_sparse | sec_cm_mem_tl_lc_gate_fsm_sparse | 0 | 0 | -- | ||
| V2S | sec_cm_exec_ctrl_mubi | sec_cm_exec_ctrl_mubi | 0 | 0 | -- | ||
| V2S | TOTAL | 0 | 25 | 0.00 | |||
| V3 | stress_all_with_rand_reset | rv_dm_stress_all_with_rand_reset | 0 | 50 | 0.00 | ||
| V3 | TOTAL | 0 | 50 | 0.00 | |||
| TOTAL | 0 | 504 | 0.00 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 24 | 24 | 0 | 0.00 |
| V2 | 18 | 16 | 0 | 0.00 |
| V2S | 8 | 2 | 0 | 0.00 |
| V3 | 1 | 1 | 0 | 0.00 |
Job killed most likely because its dependent job failed. has 506 failures:
Test rv_dm_csr_aliasing has 5 failures.
0.rv_dm_csr_aliasing.30396571574424745984833867216350808362771558657354341067797699478872420260853
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_csr_aliasing/latest/run.log
1.rv_dm_csr_aliasing.59032467292034114124752620547686723234463471030515110921621202192674106570999
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_csr_aliasing/latest/run.log
... and 3 more failures.
Test rv_dm_smoke has 2 failures.
0.rv_dm_smoke.16811505904925966101995193615912603050282724586105881183679789811337189540494
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_smoke/latest/run.log
1.rv_dm_smoke.71133680110095641067821999577800238685292027708739563018308422137843999753928
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log
Test rv_dm_tap_fsm has 1 failures.
Test rv_dm_jtag_dtm_csr_hw_reset has 5 failures.
0.rv_dm_jtag_dtm_csr_hw_reset.52444113249512836967848052615991343016923340077216087513137523512574109479847
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
1.rv_dm_jtag_dtm_csr_hw_reset.109748706319112870644296501428630720939295009547967302698870221470273567936323
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_hw_reset/latest/run.log
... and 3 more failures.
Test rv_dm_jtag_dtm_csr_rw has 20 failures.
0.rv_dm_jtag_dtm_csr_rw.14947132875096155898560455904076201818639399483425479555666311004778702727006
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_csr_rw/latest/run.log
1.rv_dm_jtag_dtm_csr_rw.35923663868261322500906208012277614394860543362329695871257232629061972319937
Log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_csr_rw/latest/run.log
... and 18 more failures.
... and 39 more tests.
Test cover_reg_top has 1 failures.
Test default has 1 failures.