RV_DM Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.640s 490.047us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.990s 186.064us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 1.080s 153.468us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 6.720s 6.154ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.130s 154.117us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 3.080s 2.207ms 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 7.380s 2.292ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 2.635m 50.000ms 4 5 80.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 59.770s 16.154ms 5 5 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 7.000s 1.971ms 2 2 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 5.730s 2.718ms 2 2 100.00
V1 cmderr_exception rv_dm_cmderr_exception 2.240s 538.618us 2 2 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 2.100s 495.045us 2 2 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.800s 64.228us 2 2 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 1.150s 959.206us 2 2 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.780s 56.533us 2 2 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.790s 45.346us 0 2 0.00
V1 progbuf_busy rv_dm_progbuf_busy 0.960s 144.952us 2 2 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 0.750s 81.740us 2 2 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.880s 95.696us 2 2 100.00
V1 progbuf_exception rv_dm_cmderr_exception 2.240s 538.618us 2 2 100.00
V1 rom_read_access rv_dm_rom_read_access 0.800s 18.785us 2 2 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.510s 113.412us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.510s 1.256ms 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 1.140m 23.248ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.128m 1.174ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 9.870s 3.923ms 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 1.128m 1.174ms 5 5 100.00
rv_dm_csr_rw 2.510s 1.256ms 20 20 100.00
V1 mem_walk rv_dm_mem_walk 0.700s 57.861us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.730s 49.856us 5 5 100.00
V1 TOTAL 158 161 98.14
V2 idcode rv_dm_smoke 1.640s 490.047us 2 2 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.080s 229.097us 2 2 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 2.301m 50.000ms 0 2 0.00
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 0.990s 99.371us 2 2 100.00
V2 sba rv_dm_sba_tl_access 1.330s 163.996us 0 20 0.00
rv_dm_delayed_resp_sba_tl_access 1.410s 576.776us 0 20 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 1.310s 177.630us 0 20 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 34.610s 50.000ms 0 20 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.680s 29.418us 0 2 0.00
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req rv_dm_ndmreset_req 1.390s 409.946us 2 2 100.00
V2 hart_unavail rv_dm_hart_unavail 0.850s 58.944us 5 5 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm 4.170s 1.487ms 1 1 100.00
rv_dm_tap_fsm_rand_reset 36.870s 11.030ms 13 40 32.50
V2 stress_all rv_dm_stress_all 16.260s 4.838ms 6 50 12.00
V2 alert_test rv_dm_alert_test 0.780s 18.684us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 6.660s 294.507us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 6.660s 294.507us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 1.128m 1.174ms 5 5 100.00
rv_dm_csr_hw_reset 2.510s 113.412us 5 5 100.00
rv_dm_csr_rw 2.510s 1.256ms 20 20 100.00
rv_dm_same_csr_outstanding 8.170s 416.771us 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 1.128m 1.174ms 5 5 100.00
rv_dm_csr_hw_reset 2.510s 113.412us 5 5 100.00
rv_dm_csr_rw 2.510s 1.256ms 20 20 100.00
rv_dm_same_csr_outstanding 8.170s 416.771us 20 20 100.00
V2 TOTAL 121 276 43.84
V2S tl_intg_err rv_dm_sec_cm 1.580s 161.115us 5 5 100.00
rv_dm_tl_intg_err 20.200s 4.473ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_lc_dft_en_intersig_mubi sec_cm_lc_dft_en_intersig_mubi 0 0 --
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 12.920s 2.936ms 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 304 512 59.38

Testplan Progress

Items Total Written Passing Progress
V1 28 28 26 92.86
V2 18 16 8 44.44
V2S 10 2 2 20.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
75.74 90.33 76.92 86.93 64.10 76.17 98.42 37.33

Failure Buckets

Past Results