RV_DM Simulation Results

Saturday March 25 2023 07:06:46 UTC

GitHub Revision: 8b50eb41f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 2145637544

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 1.160s 291.829us 2 2 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.800s 63.654us 5 5 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.840s 97.648us 20 20 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 14.460s 4.887ms 5 5 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 0.860s 77.517us 5 5 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 1.950s 504.848us 5 5 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.530s 1.146ms 20 20 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 36.620s 11.528ms 5 5 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 58.370s 20.740ms 5 5 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 2.320s 109.398us 5 5 100.00
V1 csr_rw rv_dm_csr_rw 2.270s 163.052us 20 20 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 52.260s 2.792ms 5 5 100.00
V1 csr_aliasing rv_dm_csr_aliasing 1.067m 6.823ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 8.290s 4.123ms 15 20 75.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_rw 2.270s 163.052us 20 20 100.00
rv_dm_csr_aliasing 1.067m 6.823ms 5 5 100.00
V1 mem_walk rv_dm_mem_walk 0.700s 27.796us 5 5 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.640s 21.425us 5 5 100.00
V1 TOTAL 132 137 96.35
V2 idcode rv_dm_smoke 1.160s 291.829us 2 2 100.00
V2 jtag_dtm_hard_reset jtag_dtm_hard_reset 0 0 --
V2 jtag_dtm_idle_hint jtag_dtm_idle_hint 0 0 --
V2 jtag_dmi_failed_op jtag_dmi_failed_op 0 0 --
V2 jtag_dmi_dm_inactive jtag_dmi_dm_inactive 0 0 --
V2 sba rv_dm_sba_tl_access 23.300s 7.404ms 20 20 100.00
rv_dm_delayed_resp_sba_tl_access 48.370s 16.471ms 20 20 100.00
V2 bad_sba rv_dm_bad_sba_tl_access 17.070s 8.742ms 20 20 100.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 2.987m 50.000ms 19 20 95.00
V2 jtag_dmi_debug_disabled jtag_dmi_debug_disabled 0 0 --
V2 sba_debug_disabled sba_debug_disabled 0 0 --
V2 ndmreset_req ndmreset_req 0 0 --
V2 hart_unavail hart_unavail 0 0 --
V2 tap_ctrl_transitions tap_ctrl_transitions 0 0 --
V2 stress_all rv_dm_stress_all 0.620s 0 50 0.00
V2 alert_test rv_dm_alert_test 0.730s 57.707us 50 50 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 5.730s 103.568us 20 20 100.00
V2 tl_d_illegal_access rv_dm_tl_errors 5.730s 103.568us 20 20 100.00
V2 tl_d_outstanding_access rv_dm_csr_hw_reset 2.320s 109.398us 5 5 100.00
rv_dm_csr_rw 2.270s 163.052us 20 20 100.00
rv_dm_csr_aliasing 1.067m 6.823ms 5 5 100.00
rv_dm_same_csr_outstanding 9.240s 6.552ms 20 20 100.00
V2 tl_d_partial_access rv_dm_csr_hw_reset 2.320s 109.398us 5 5 100.00
rv_dm_csr_rw 2.270s 163.052us 20 20 100.00
rv_dm_csr_aliasing 1.067m 6.823ms 5 5 100.00
rv_dm_same_csr_outstanding 9.240s 6.552ms 20 20 100.00
V2 TOTAL 169 220 76.82
V2S tl_intg_err rv_dm_sec_cm 1.060s 109.076us 5 5 100.00
rv_dm_tl_intg_err 19.440s 3.573ms 20 20 100.00
V2S sec_cm_bus_integrity sec_cm_bus_integrity 0 0 --
V2S sec_cm_lc_hw_debug_en_intersig_mubi sec_cm_lc_hw_debug_en_intersig_mubi 0 0 --
V2S sec_cm_dm_en_ctrl_lc_gated sec_cm_dm_en_ctrl_lc_gated 0 0 --
V2S sec_cm_sba_tl_lc_gate_fsm_sparse sec_cm_sba_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_mem_tl_lc_gate_fsm_sparse sec_cm_mem_tl_lc_gate_fsm_sparse 0 0 --
V2S sec_cm_exec_ctrl_mubi sec_cm_exec_ctrl_mubi 0 0 --
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0.700s 5.431us 0 50 0.00
V3 TOTAL 0 50 0.00
TOTAL 326 432 75.46

Testplan Progress

Items Total Written Passing Progress
V1 16 16 15 93.75
V2 17 8 6 35.29
V2S 8 2 2 25.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
76.97 83.23 61.69 87.95 46.15 66.67 97.75 95.34

Failure Buckets

Past Results