RV_DM Simulation Results

Monday October 14 2024 17:26:15 UTC

GitHub Revision: `12e3b8572e`

Branch: os_regression_2024_10_14

Simulator: VCS

Build randomization enabled with --build-seed 85025606402499621082521464627961092918263397067038954055071960501195381950243

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	7.850s	10.170ms	1	2	50.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	2.230s	242.896us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.340s	969.159us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	35.270s	41.374ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.890s	1.777ms	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	19.190s	7.821ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	48.690s	13.118ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	1.718m	49.084ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	2.429m	45.121ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	1.500s	1.072ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.670s	703.106us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.470s	693.030us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.390s	275.775us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.220s	446.658us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.180s	233.905us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.850s	83.075us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	23.214s		7	8	87.50
V1	progbuf_busy	rv_dm_cmderr_busy	1.500s	1.072ms	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	1.190s	444.686us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	1.790s	1.000ms	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.470s	693.030us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	0.790s	102.031us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.820s	206.921us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.630s	140.656us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.099m	20.488ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.249m	6.046ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	5.550s	79.467us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.249m	6.046ms	5	5	100.00
		rv_dm_csr_rw	3.630s	140.656us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.230s	147.740us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.360s	57.229us	5	5	100.00
V1		TOTAL			178	180	98.89
V2	idcode	rv_dm_smoke	7.850s	10.170ms	1	2	50.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.270s	261.945us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	1.860s	425.835us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.310s	290.351us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	2.070s	497.945us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	27.980s	9.098ms	19	20	95.00
		rv_dm_delayed_resp_sba_tl_access	23.072s		19	20	95.00
V2	bad_sba	rv_dm_bad_sba_tl_access	33.570s	13.978ms	19	20	95.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.733m	66.825ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	1.070s	182.847us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	6.280s	4.713ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.780s	687.409us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.970s	238.689us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.880s	7.271ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	1.592m	22.965ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	0.650s	205.587us	1	1	100.00
V2	stress_all	rv_dm_stress_all	46.140s	11.588ms	45	50	90.00
V2	alert_test	rv_dm_alert_test	23.133s		49	50	98.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	7.440s	346.461us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	7.440s	346.461us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.249m	6.046ms	5	5	100.00
		rv_dm_csr_hw_reset	2.820s	206.921us	5	5	100.00
		rv_dm_csr_rw	3.630s	140.656us	20	20	100.00
		rv_dm_same_csr_outstanding	10.930s	4.170ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.249m	6.046ms	5	5	100.00
		rv_dm_csr_hw_reset	2.820s	206.921us	5	5	100.00
		rv_dm_csr_rw	3.630s	140.656us	20	20	100.00
		rv_dm_same_csr_outstanding	10.930s	4.170ms	20	20	100.00
V2		TOTAL			242	251	96.41
V2S	tl_intg_err	rv_dm_sec_cm	3.690s	2.189ms	5	5	100.00
		rv_dm_tl_intg_err	31.400s	1.605ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	31.400s	1.605ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	6.280s	4.713ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	155.707us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	6.280s	4.713ms	2	2	100.00
		rv_dm_debug_disabled	0.970s	155.707us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	7.850s	10.170ms	1	2	50.00
V2S	sec_cm_dm_en_ctrl_lc_gated	rv_dm_buffered_enable	23.207s		9	10	90.00
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.230s	271.167us	4	4	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	rv_dm_sparse_lc_gate_fsm	1.230s	271.167us	4	4	100.00
V2S	sec_cm_exec_ctrl_mubi	rv_dm_buffered_enable	23.207s		9	10	90.00
V2S		TOTAL			40	41	97.56
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	2.504m	16.752ms	9	10	90.00
V3		TOTAL			9	10	90.00
	Unmapped tests	rv_dm_scanmode	0.630s	11.160us	1	1	100.00
		TOTAL			470	483	97.31

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	1	1	1	100.00
V1	27	27	25	92.59
V2	19	19	14	73.68
V2S	5	5	4	80.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.20	96.64	90.52	92.10	93.33	90.44	98.74	62.63

Failure Buckets

Job returned non-zero exit code has 8 failures:

Test rv_dm_bad_sba_tl_access has 1 failures.

6.rv_dm_bad_sba_tl_access.19206359337957780805654322099960881250227379147376107707197816584478241361039
Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_bad_sba_tl_access/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 01:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test rv_dm_halt_resume_whereto has 1 failures.

6.rv_dm_halt_resume_whereto.29405155505260127433385529667746704233727096700867849275996343658340816146294
Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_halt_resume_whereto/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 01:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test rv_dm_buffered_enable has 1 failures.

6.rv_dm_buffered_enable.55043204678450733689331229693312095865223531067498954472566342549450854557385
Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_buffered_enable/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 01:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test rv_dm_stress_all has 1 failures.

6.rv_dm_stress_all.40500052391827735144149479912953145274149165454033269276872852763087514468275
Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_stress_all/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 01:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test rv_dm_stress_all_with_rand_reset has 1 failures.

6.rv_dm_stress_all_with_rand_reset.4689495532114771978825918314710533001515439606615451508539444844314773156200
Log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/6.rv_dm_stress_all_with_rand_reset/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Oct 15 01:11 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 3 more tests.

UVM_FATAL (cip_base_vseq.sv:268) [rv_dm_smoke_vseq] Timeout waiting tl_access : addr=* has 5 failures:

Test rv_dm_smoke has 1 failures.

1.rv_dm_smoke.46389199370668032865899151779434311077284999009866209706809955294791322669628
Line 71, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/1.rv_dm_smoke/latest/run.log

  UVM_FATAL @ 10169817440 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Timeout waiting tl_access : addr=0x67e5ffd7
  UVM_INFO @ 10169817440 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test rv_dm_stress_all has 4 failures.

2.rv_dm_stress_all.29575530619309042190218716393052295550778317777257649055265386617691956502291
Line 82, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/2.rv_dm_stress_all/latest/run.log

  UVM_FATAL @ 12632098058 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Timeout waiting tl_access : addr=0x1431c99e
  UVM_INFO @ 12632098058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

29.rv_dm_stress_all.69551490430252871462203691144502003195655850031100697380267181349121733174532
Line 75, in log /workspaces/repo/scratch/os_regression_2024_10_14/rv_dm-sim-vcs/29.rv_dm_stress_all/latest/run.log

  UVM_FATAL @ 11101776657 ps: (cip_base_vseq.sv:268) [uvm_test_top.env.virtual_sequencer.rv_dm_smoke_vseq] Timeout waiting tl_access : addr=0x9b89a82a
  UVM_INFO @ 11101776657 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.