RV_DM Simulation Results

Wednesday November 22 2023 20:02:38 UTC

GitHub Revision: `4002b28ec4`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56541452733628775295814943325285397402671097056517970046183331126493552547969

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	1.200s	782.614us	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	0.720s	147.138us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	0.860s	112.726us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	3.680s	2.570ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	0.850s	210.491us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	1.940s	1.190ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	1.670s	747.143us	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	35.400s	30.205ms	5	5	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	18.160s	14.699ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	6.670s	7.927ms	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	4.720s	5.669ms	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	1.410s	1.132ms	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	1.280s	874.320us	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	1.230s	874.320us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	1.420s	1.256ms	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	0.660s	106.373us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	1.820s	1.395ms	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	2.490s	502.023us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	2.540s	460.611us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.218m	28.499ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.317m	19.613ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	2.940s	288.727us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.317m	19.613ms	5	5	100.00
		rv_dm_csr_rw	2.540s	460.611us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	0.740s	54.961us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	0.650s	72.196us	5	5	100.00
V1		TOTAL			153	153	100.00
V2	idcode	rv_dm_smoke	1.200s	782.614us	2	2	100.00
V2	jtag_dtm_hard_reset	jtag_dtm_hard_reset			0	0	--
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	31.530s	50.000ms	0	2	0.00
V2	jtag_dmi_failed_op	jtag_dmi_failed_op			0	0	--
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	0.810s	295.316us	2	2	100.00
V2	sba	rv_dm_sba_tl_access	5.780s	3.899ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	3.930s	2.434ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	12.920s	9.843ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.490s	1.291ms	20	20	100.00
V2	jtag_dmi_debug_disabled	jtag_dmi_debug_disabled			0	0	--
V2	sba_debug_disabled	sba_debug_disabled			0	0	--
V2	ndmreset_req	rv_dm_ndmreset_req	1.480s	1.114ms	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	0.820s	191.197us	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	0.600s	10.973us	0	1	0.00
		rv_dm_tap_fsm_rand_reset	22.080s	27.189ms	40	40	100.00
V2	stress_all	rv_dm_stress_all	0.590s		0	50	0.00
V2	alert_test	rv_dm_alert_test	0.740s	86.255us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	4.940s	928.968us	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	4.940s	928.968us	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.317m	19.613ms	5	5	100.00
		rv_dm_csr_hw_reset	2.490s	502.023us	5	5	100.00
		rv_dm_csr_rw	2.540s	460.611us	20	20	100.00
		rv_dm_same_csr_outstanding	8.270s	2.220ms	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.317m	19.613ms	5	5	100.00
		rv_dm_csr_hw_reset	2.490s	502.023us	5	5	100.00
		rv_dm_csr_rw	2.540s	460.611us	20	20	100.00
		rv_dm_same_csr_outstanding	8.270s	2.220ms	20	20	100.00
V2		TOTAL			219	272	80.51
V2S	tl_intg_err	rv_dm_sec_cm	1.260s	442.140us	5	5	100.00
		rv_dm_tl_intg_err	20.730s	4.658ms	20	20	100.00
V2S	sec_cm_bus_integrity	sec_cm_bus_integrity			0	0	--
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sec_cm_lc_hw_debug_en_intersig_mubi			0	0	--
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	0.630s	10.378us	0	50	0.00
V3		TOTAL			0	50	0.00
		TOTAL			397	500	79.40

Testplan Progress

Items	Total	Written	Passing	Progress
V1	24	24	24	100.00
V2	18	14	11	61.11
V2S	8	2	2	25.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.99	92.22	76.40	87.53	71.79	81.42	97.43	67.13

Failure Buckets

UVM_WARNING [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory. has 100 failures:

Test rv_dm_stress_all_with_rand_reset has 50 failures.

0.rv_dm_stress_all_with_rand_reset.95661554689961611876848716704883872812549070406109136074328977674753111685275
Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  10377775 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  10377775 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.rv_dm_stress_all_with_rand_reset.4233542752519099721768449712064760311366876615526766331804999898759281642960
Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all_with_rand_reset/latest/run.log

  UVM_WARNING @  10377775 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @  10377775 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

Test rv_dm_stress_all has 50 failures.

0.rv_dm_stress_all.92342671698124354862826202896677369962304953180948476949744484401265505781242
Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

1.rv_dm_stress_all.73126249017422636436943425491106952720068315352043833492518806902541725058193
Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_stress_all/latest/run.log

  UVM_WARNING @         0 ps: [BDTYP] Cannot create an object of type 'rv_dm_stress_all_vseq' because it is not registered with the factory.
  UVM_INFO @         0 ps: (uvm_factory.svh:1645) [UVM/FACTORY/PRINT]
  #### Factory Configuration (*)
  
  No instance overrides are registered with this factory

... and 48 more failures.

UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test rv_dm_jtag_dtm_idle_hint has 2 failures.
  - 0.rv_dm_jtag_dtm_idle_hint.29461833357971810018170657883767182002532617503897365451535241544121545871714
    Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_jtag_dtm_idle_hint/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.rv_dm_jtag_dtm_idle_hint.102977624072480024351356282424551906908645636502816816057511975122345046736645
    Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/1.rv_dm_jtag_dtm_idle_hint/latest/run.log
```
  UVM_FATAL @ 50000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 50000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 50000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (jtag_dmi_monitor.sv:105) m_jtag_dmi_monitor [m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request. has 1 failures:
- Test rv_dm_tap_fsm has 1 failures.
  - 0.rv_dm_tap_fsm.39281258080703865891183910177751507531062736245967338239454203997431175890518
    Line 206, in log /container/opentitan-public/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_tap_fsm/latest/run.log
```
  UVM_ERROR @  10972592 ps: (jtag_dmi_monitor.sv:105) uvm_test_top.env.m_jtag_dmi_monitor [uvm_test_top.env.m_jtag_dmi_monitor] Non-ok response seen with no previous DMI request.
  UVM_INFO @  10972592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```