RV_DM Simulation Results

Saturday February 08 2025 05:05:54 UTC

GitHub Revision: 9f20940d49

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 88344288495849993302635329522992994622996067932062874150778031027723701018040

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rv_dm_smoke	17.920s	5.130ms	2	2	100.00
V1	jtag_dtm_csr_hw_reset	rv_dm_jtag_dtm_csr_hw_reset	4.600s	607.382us	5	5	100.00
V1	jtag_dtm_csr_rw	rv_dm_jtag_dtm_csr_rw	4.930s	693.719us	20	20	100.00
V1	jtag_dtm_csr_bit_bash	rv_dm_jtag_dtm_csr_bit_bash	3.118m	38.881ms	5	5	100.00
V1	jtag_dtm_csr_aliasing	rv_dm_jtag_dtm_csr_aliasing	6.550s	960.064us	5	5	100.00
V1	jtag_dmi_csr_hw_reset	rv_dm_jtag_dmi_csr_hw_reset	28.890s	6.745ms	5	5	100.00
V1	jtag_dmi_csr_rw	rv_dm_jtag_dmi_csr_rw	48.860s	9.292ms	20	20	100.00
V1	jtag_dmi_csr_bit_bash	rv_dm_jtag_dmi_csr_bit_bash	3.010m	53.192ms	20	20	100.00
V1	jtag_dmi_csr_aliasing	rv_dm_jtag_dmi_csr_aliasing	6.979m	202.620ms	5	5	100.00
V1	jtag_dmi_cmderr_busy	rv_dm_cmderr_busy	6.000s	934.276us	2	2	100.00
V1	jtag_dmi_cmderr_not_supported	rv_dm_cmderr_not_supported	2.200s	544.178us	2	2	100.00
V1	cmderr_exception	rv_dm_cmderr_exception	2.980s	395.141us	2	2	100.00
V1	mem_tl_access_resuming	rv_dm_mem_tl_access_resuming	7.640s	3.016ms	2	2	100.00
V1	mem_tl_access_halted	rv_dm_mem_tl_access_halted	2.930s	296.593us	2	2	100.00
V1	cmderr_halt_resume	rv_dm_cmderr_halt_resume	3.720s	929.337us	2	2	100.00
V1	dataaddr_rw_access	rv_dm_dataaddr_rw_access	1.910s	280.827us	2	2	100.00
V1	halt_resume	rv_dm_halt_resume_whereto	5.140s	719.555us	8	8	100.00
V1	progbuf_busy	rv_dm_cmderr_busy	6.000s	934.276us	2	2	100.00
V1	abstractcmd_status	rv_dm_abstractcmd_status	2.680s	556.614us	2	2	100.00
V1	progbuf_read_write_execute	rv_dm_progbuf_read_write_execute	5.660s	796.609us	2	2	100.00
V1	progbuf_exception	rv_dm_cmderr_exception	2.980s	395.141us	2	2	100.00
V1	rom_read_access	rv_dm_rom_read_access	1.510s	62.412us	2	2	100.00
V1	csr_hw_reset	rv_dm_csr_hw_reset	4.840s	487.102us	5	5	100.00
V1	csr_rw	rv_dm_csr_rw	3.960s	205.411us	20	20	100.00
V1	csr_bit_bash	rv_dm_csr_bit_bash	1.587m	14.950ms	5	5	100.00
V1	csr_aliasing	rv_dm_csr_aliasing	1.599m	21.994ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	rv_dm_csr_mem_rw_with_rand_reset	8.020s	471.211us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_dm_csr_aliasing	1.599m	21.994ms	5	5	100.00
		rv_dm_csr_rw	3.960s	205.411us	20	20	100.00
V1	mem_walk	rv_dm_mem_walk	1.330s	52.501us	5	5	100.00
V1	mem_partial_access	rv_dm_mem_partial_access	1.300s	59.254us	5	5	100.00
V1		TOTAL			180	180	100.00
V2	idcode	rv_dm_smoke	17.920s	5.130ms	2	2	100.00
V2	jtag_dtm_hard_reset	rv_dm_jtag_dtm_hard_reset	1.820s	177.835us	2	2	100.00
V2	jtag_dtm_idle_hint	rv_dm_jtag_dtm_idle_hint	2.330s	249.163us	2	2	100.00
V2	jtag_dmi_failed_op	rv_dm_dmi_failed_op	1.530s	99.142us	2	2	100.00
V2	jtag_dmi_dm_inactive	rv_dm_jtag_dmi_dm_inactive	6.470s	1.052ms	2	2	100.00
V2	sba	rv_dm_sba_tl_access	36.070s	11.143ms	20	20	100.00
		rv_dm_delayed_resp_sba_tl_access	39.500s	13.181ms	20	20	100.00
V2	bad_sba	rv_dm_bad_sba_tl_access	58.520s	8.767ms	20	20	100.00
V2	sba_autoincrement	rv_dm_autoincr_sba_tl_access	2.405m	40.920ms	20	20	100.00
V2	jtag_dmi_debug_disabled	rv_dm_jtag_dmi_debug_disabled	2.130s	545.124us	2	2	100.00
V2	sba_debug_disabled	rv_dm_sba_debug_disabled	12.660s	3.927ms	2	2	100.00
V2	ndmreset_req	rv_dm_ndmreset_req	2.180s	796.938us	2	2	100.00
V2	hart_unavail	rv_dm_hart_unavail	3.170s	1.041ms	5	5	100.00
V2	tap_ctrl_transitions	rv_dm_tap_fsm	9.510s	6.190ms	1	1	100.00
		rv_dm_tap_fsm_rand_reset	6.258m	58.384ms	10	10	100.00
V2	hartsel_warl	rv_dm_hartsel_warl	1.420s	73.176us	1	1	100.00
V2	stress_all	rv_dm_stress_all	34.000s	9.087ms	50	50	100.00
V2	alert_test	rv_dm_alert_test	1.790s	132.539us	50	50	100.00
V2	tl_d_oob_addr_access	rv_dm_tl_errors	10.330s	1.381ms	20	20	100.00
V2	tl_d_illegal_access	rv_dm_tl_errors	10.330s	1.381ms	20	20	100.00
V2	tl_d_outstanding_access	rv_dm_csr_aliasing	1.599m	21.994ms	5	5	100.00
		rv_dm_csr_hw_reset	4.840s	487.102us	5	5	100.00
		rv_dm_csr_rw	3.960s	205.411us	20	20	100.00
		rv_dm_same_csr_outstanding	13.350s	618.509us	20	20	100.00
V2	tl_d_partial_access	rv_dm_csr_aliasing	1.599m	21.994ms	5	5	100.00
		rv_dm_csr_hw_reset	4.840s	487.102us	5	5	100.00
		rv_dm_csr_rw	3.960s	205.411us	20	20	100.00
		rv_dm_same_csr_outstanding	13.350s	618.509us	20	20	100.00
V2		TOTAL			251	251	100.00
V2S	tl_intg_err	rv_dm_sec_cm	4.930s	2.971ms	5	5	100.00
		rv_dm_tl_intg_err	41.570s	5.928ms	20	20	100.00
V2S	sec_cm_bus_integrity	rv_dm_tl_intg_err	41.570s	5.928ms	20	20	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	rv_dm_sba_debug_disabled	12.660s	3.927ms	2	2	100.00
		rv_dm_debug_disabled	1.430s	117.245us	2	2	100.00
V2S	sec_cm_lc_dft_en_intersig_mubi	rv_dm_sba_debug_disabled	12.660s	3.927ms	2	2	100.00
		rv_dm_debug_disabled	1.430s	117.245us	2	2	100.00
V2S	sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi	rv_dm_smoke	17.920s	5.130ms	2	2	100.00
V2S	sec_cm_dm_en_ctrl_lc_gated	sec_cm_dm_en_ctrl_lc_gated			0	0	--
V2S	sec_cm_sba_tl_lc_gate_fsm_sparse	sec_cm_sba_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	sec_cm_mem_tl_lc_gate_fsm_sparse			0	0	--
V2S	sec_cm_exec_ctrl_mubi	sec_cm_exec_ctrl_mubi			0	0	--
V2S		TOTAL			27	27	100.00
V3	stress_all_with_rand_reset	rv_dm_stress_all_with_rand_reset	40.116m	322.734ms	9	10	90.00
V3		TOTAL			9	10	90.00
		TOTAL			467	468	99.79

Testplan Progress

Items	Total	Written	Passing	Progress
V1	27	27	27	100.00
V2	19	19	19	100.00
V2S	7	3	3	42.86
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
82.47	96.32	87.13	92.10	72.50	90.44	98.21	40.57

Failure Buckets

• UVM_ERROR (rv_dm_hart_unavail_vseq.sv:22) [rv_dm_hart_unavail_vseq] Check failedgmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (* [] vs * [])` has 1 failures:
  • Test rv_dm_stress_all_with_rand_reset has 1 failures.

    • 0.rv_dm_stress_all_with_rand_reset.65035728177417805773326862255290937568374852121141681531858074495285247981731
      Line 122, in log /workspaces/repo/scratch/os_regression/rv_dm-sim-vcs/0.rv_dm_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6584209682 ps: (rv_dm_hart_unavail_vseq.sv:22) [uvm_test_top.env.virtual_sequencer.rv_dm_hart_unavail_vseq] Check failed `gmv(jtag_dmi_ral.dmstatus.anyunavail) == req_unavailable (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 6584209682 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

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