Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	228727	1		T7	6		T8	30		T9	68
full_word	559605	1		T8	6		T9	28		T19	22

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	788022	1		T7	6		T8	36		T9	96
auto[TlIntgErrCmd]	109	1		T39	8		T40	5		T41	9
auto[TlIntgErrData]	104	1		T39	5		T40	4		T41	8
auto[TlIntgErrBoth]	97	1		T39	7		T40	1		T41	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	466402	1		T9	15		T19	16		T18	24
auto[1]	321930	1		T7	6		T8	36		T9	81

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	189723	1		T9	9		T19	10		T18	8
auto[TlIntgErrNone]	partial	auto[1]	38717	1		T7	6		T8	30		T9	59
auto[TlIntgErrNone]	full_word	auto[0]	276547	1		T9	6		T19	6		T18	16
auto[TlIntgErrNone]	full_word	auto[1]	283035	1		T8	6		T9	22		T19	16
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T39	2		T40	2		T41	3
auto[TlIntgErrCmd]	partial	auto[1]	64	1		T39	6		T40	3		T41	6
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T139	1		T135	1		T140	1
auto[TlIntgErrCmd]	full_word	auto[1]	4	1		T141	1		T138	1		T142	2
auto[TlIntgErrData]	partial	auto[0]	50	1		T39	1		T40	3		T41	5
auto[TlIntgErrData]	partial	auto[1]	45	1		T39	3		T40	1		T41	3
auto[TlIntgErrData]	full_word	auto[0]	4	1		T135	2		T141	1		T142	1
auto[TlIntgErrData]	full_word	auto[1]	5	1		T39	1		T139	1		T143	2
auto[TlIntgErrBoth]	partial	auto[0]	32	1		T41	2		T144	1		T133	3
auto[TlIntgErrBoth]	partial	auto[1]	58	1		T39	4		T40	1		T41	1
auto[TlIntgErrBoth]	full_word	auto[0]	5	1		T39	2		T135	1		T141	1
auto[TlIntgErrBoth]	full_word	auto[1]	2	1		T39	1		T144	1		-	-