Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	196520	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	558460	1		T8	6		T9	28		T19	22

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	465045	1		T9	15		T19	16		T18	24
values[0x0]	142811	1		T7	2		T8	15		T9	33
values[0x1]	147124	1		T7	4		T8	21		T9	48

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	151295	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	603685	1		T7	1		T8	8		T9	37

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3308	1		T45	8		T39	63		T40	12
valid_sources[0x01]	2535	1		T9	2		T39	52		T40	19
valid_sources[0x02]	2646	1		T9	1		T59	1		T39	32
valid_sources[0x03]	2420	1		T20	1		T45	6		T39	29
valid_sources[0x04]	2924	1		T21	1		T45	35		T39	48
valid_sources[0x05]	3087	1		T39	41		T40	10		T41	67
valid_sources[0x06]	2392	1		T18	3		T39	46		T40	51
valid_sources[0x07]	2823	1		T9	1		T45	5		T39	42
valid_sources[0x08]	2811	1		T45	9		T39	33		T40	12
valid_sources[0x09]	2386	1		T9	1		T45	4		T39	46
valid_sources[0x0a]	3037	1		T45	5		T39	16		T40	14
valid_sources[0x0b]	2976	1		T18	1		T79	1		T45	10
valid_sources[0x0c]	2884	1		T39	34		T40	14		T41	56
valid_sources[0x0d]	2598	1		T45	30		T39	32		T40	11
valid_sources[0x0e]	2714	1		T45	31		T39	45		T40	28
valid_sources[0x0f]	2684	1		T18	2		T39	36		T40	13
valid_sources[0x10]	2697	1		T45	8		T39	18		T40	21
valid_sources[0x11]	2451	1		T18	2		T39	44		T40	22
valid_sources[0x12]	3061	1		T9	1		T45	5		T39	49
valid_sources[0x13]	2671	1		T9	4		T45	48		T39	44
valid_sources[0x14]	3670	1		T9	1		T39	55		T40	6
valid_sources[0x15]	3048	1		T8	18		T45	8		T39	60
valid_sources[0x16]	2601	1		T59	1		T45	15		T39	38
valid_sources[0x17]	3219	1		T18	1		T45	1		T39	18
valid_sources[0x18]	2928	1		T39	49		T40	29		T41	28
valid_sources[0x19]	2583	1		T5	1		T39	52		T40	28
valid_sources[0x1a]	2353	1		T9	1		T39	36		T40	6
valid_sources[0x1b]	2446	1		T39	33		T40	48		T41	14
valid_sources[0x1c]	3416	1		T5	2		T45	14		T39	44
valid_sources[0x1d]	2841	1		T9	1		T39	54		T40	12
valid_sources[0x1e]	3127	1		T9	1		T45	51		T39	69
valid_sources[0x1f]	3516	1		T39	26		T40	9		T41	104
valid_sources[0x20]	2740	1		T20	1		T62	2		T39	42
valid_sources[0x21]	2975	1		T39	27		T40	31		T41	34
valid_sources[0x22]	2878	1		T20	1		T45	35		T39	27
valid_sources[0x23]	3023	1		T39	33		T40	25		T41	12
valid_sources[0x24]	2869	1		T39	59		T40	10		T52	2
valid_sources[0x25]	2894	1		T45	15		T39	62		T40	17
valid_sources[0x26]	2550	1		T9	2		T39	63		T40	12
valid_sources[0x27]	2999	1		T9	1		T45	10		T39	39
valid_sources[0x28]	2628	1		T59	1		T45	20		T39	74
valid_sources[0x29]	3260	1		T9	1		T79	1		T45	24
valid_sources[0x2a]	2551	1		T9	2		T39	43		T40	41
valid_sources[0x2b]	3317	1		T39	42		T40	51		T41	94
valid_sources[0x2c]	2692	1		T79	1		T62	7		T39	28
valid_sources[0x2d]	2796	1		T45	22		T39	43		T40	18
valid_sources[0x2e]	2716	1		T18	2		T45	10		T39	63
valid_sources[0x2f]	2872	1		T9	1		T20	1		T39	57
valid_sources[0x30]	2423	1		T20	1		T14	3		T45	8
valid_sources[0x31]	2959	1		T62	3		T45	8		T39	28
valid_sources[0x32]	2600	1		T45	3		T39	27		T40	37
valid_sources[0x33]	2816	1		T14	4		T39	37		T40	29
valid_sources[0x34]	3368	1		T45	15		T39	32		T40	4
valid_sources[0x35]	2889	1		T45	21		T39	53		T40	14
valid_sources[0x36]	3124	1		T9	1		T18	1		T45	51
valid_sources[0x37]	2933	1		T9	1		T45	54		T39	44
valid_sources[0x38]	2724	1		T9	1		T45	8		T39	35
valid_sources[0x39]	2611	1		T21	1		T45	11		T39	31
valid_sources[0x3a]	2907	1		T62	2		T45	5		T39	33
valid_sources[0x3b]	2838	1		T45	28		T39	58		T40	22
valid_sources[0x3c]	3025	1		T20	1		T39	51		T40	4
valid_sources[0x3d]	2789	1		T9	2		T45	29		T39	52
valid_sources[0x3e]	2851	1		T45	15		T39	35		T40	14
valid_sources[0x3f]	2533	1		T39	40		T41	62		T52	3
valid_sources[0x40]	3129	1		T9	1		T59	1		T45	26
valid_sources[0x41]	2869	1		T9	1		T59	1		T39	39
valid_sources[0x42]	2834	1		T18	1		T45	15		T39	45
valid_sources[0x43]	2906	1		T9	1		T45	22		T39	41
valid_sources[0x44]	3441	1		T8	5		T20	1		T45	8
valid_sources[0x45]	2727	1		T39	40		T40	14		T41	12
valid_sources[0x46]	4853	1		T18	1		T62	4		T39	19
valid_sources[0x47]	2717	1		T45	35		T39	55		T40	26
valid_sources[0x48]	2947	1		T9	1		T39	25		T40	41
valid_sources[0x49]	2886	1		T45	37		T39	41		T40	15
valid_sources[0x4a]	2836	1		T18	5		T45	9		T39	53
valid_sources[0x4b]	2797	1		T45	29		T39	43		T40	5
valid_sources[0x4c]	3001	1		T45	16		T39	43		T40	5
valid_sources[0x4d]	2832	1		T45	46		T39	16		T40	30
valid_sources[0x4e]	3698	1		T20	1		T6	26		T45	26
valid_sources[0x4f]	3115	1		T45	4		T39	45		T40	10
valid_sources[0x50]	2828	1		T18	1		T20	1		T45	5
valid_sources[0x51]	2660	1		T45	12		T39	35		T40	28
valid_sources[0x52]	2535	1		T9	1		T39	46		T40	12
valid_sources[0x53]	3500	1		T45	13		T39	34		T40	6
valid_sources[0x54]	2840	1		T18	1		T45	23		T39	57
valid_sources[0x55]	2417	1		T9	1		T45	2		T39	33
valid_sources[0x56]	2292	1		T45	15		T39	42		T40	5
valid_sources[0x57]	2427	1		T45	16		T39	41		T40	32
valid_sources[0x58]	2939	1		T45	10		T39	33		T40	33
valid_sources[0x59]	3286	1		T5	1		T45	35		T39	32
valid_sources[0x5a]	2755	1		T18	1		T39	53		T40	31
valid_sources[0x5b]	3082	1		T9	4		T45	27		T39	23
valid_sources[0x5c]	3226	1		T45	8		T39	40		T40	35
valid_sources[0x5d]	2576	1		T45	27		T39	58		T40	23
valid_sources[0x5e]	2856	1		T59	1		T39	30		T40	25
valid_sources[0x5f]	2766	1		T9	1		T39	36		T40	21
valid_sources[0x60]	2853	1		T7	1		T18	1		T39	28
valid_sources[0x61]	2716	1		T45	4		T39	62		T40	48
valid_sources[0x62]	3401	1		T39	38		T40	12		T41	83
valid_sources[0x63]	2632	1		T18	1		T45	12		T39	20
valid_sources[0x64]	2997	1		T45	40		T39	40		T40	48
valid_sources[0x65]	3183	1		T20	1		T45	3		T39	37
valid_sources[0x66]	2928	1		T45	15		T39	43		T40	11
valid_sources[0x67]	3239	1		T45	12		T39	48		T40	17
valid_sources[0x68]	3338	1		T20	2		T45	5		T39	50
valid_sources[0x69]	3018	1		T45	5		T39	44		T40	21
valid_sources[0x6a]	2753	1		T18	1		T39	46		T40	31
valid_sources[0x6b]	2365	1		T9	1		T18	1		T45	27
valid_sources[0x6c]	2668	1		T18	1		T39	49		T40	1
valid_sources[0x6d]	2544	1		T21	1		T39	48		T40	21
valid_sources[0x6e]	2912	1		T7	1		T9	1		T45	7
valid_sources[0x6f]	2976	1		T9	2		T39	57		T40	17
valid_sources[0x70]	5020	1		T45	3		T39	49		T40	45
valid_sources[0x71]	3146	1		T14	12		T45	55		T39	39
valid_sources[0x72]	2814	1		T9	1		T45	17		T39	39
valid_sources[0x73]	3035	1		T45	18		T39	52		T40	3
valid_sources[0x74]	3180	1		T19	32		T5	1		T39	19
valid_sources[0x75]	2926	1		T9	2		T45	25		T39	77
valid_sources[0x76]	2848	1		T45	23		T39	35		T40	23
valid_sources[0x77]	3719	1		T45	8		T39	55		T40	19
valid_sources[0x78]	2786	1		T9	1		T18	1		T62	4
valid_sources[0x79]	3615	1		T9	1		T45	15		T39	58
valid_sources[0x7a]	3381	1		T45	16		T39	40		T40	11
valid_sources[0x7b]	2777	1		T45	1		T39	60		T40	8
valid_sources[0x7c]	2911	1		T45	1		T39	23		T40	13
valid_sources[0x7d]	3209	1		T45	28		T39	26		T40	23
valid_sources[0x7e]	2651	1		T45	5		T39	65		T40	21
valid_sources[0x7f]	3039	1		T39	46		T40	32		T41	100
valid_sources[0x80]	3249	1		T62	2		T39	46		T40	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

276410

1

T9

6

T19

6

T18

16

values[0x0]

all_enables

biggest_size

141057

1

T8

3

T9

12

T19

6

values[0x1]

all_enables

biggest_size

140993

1

T8

3

T9

10

T19

10

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2165	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	13802	1		T2	3		T3	5		T34	2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5092	1		T59	11		T45	6		T39	31
values[0x0]	5346	1		T2	2		T3	5		T34	2
values[0x1]	5529	1		T2	8		T3	4		T34	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1662	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	14305	1		T2	3		T3	5		T34	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	57	1		T43	1		T83	10		T96	4
valid_sources[0x01]	55	1		T81	4		T43	2		T83	1
valid_sources[0x02]	38	1		T53	1		T81	2		T96	3
valid_sources[0x03]	41	1		T39	2		T80	1		T81	6
valid_sources[0x04]	34	1		T81	1		T122	1		T145	4
valid_sources[0x05]	179	1		T146	3		T42	135		T43	1
valid_sources[0x06]	78	1		T147	1		T70	2		T148	2
valid_sources[0x07]	33	1		T50	3		T44	1		T97	2
valid_sources[0x08]	51	1		T50	1		T42	3		T93	2
valid_sources[0x09]	51	1		T39	2		T81	1		T44	3
valid_sources[0x0a]	56	1		T149	4		T72	1		T81	2
valid_sources[0x0b]	49	1		T150	1		T81	4		T43	1
valid_sources[0x0c]	96	1		T150	1		T39	1		T81	2
valid_sources[0x0d]	50	1		T151	1		T75	1		T145	1
valid_sources[0x0e]	68	1		T146	1		T41	12		T81	1
valid_sources[0x0f]	50	1		T40	2		T85	1		T93	1
valid_sources[0x10]	49	1		T150	1		T93	1		T81	4
valid_sources[0x11]	74	1		T85	1		T81	2		T43	3
valid_sources[0x12]	71	1		T152	1		T43	1		T96	2
valid_sources[0x13]	37	1		T153	1		T81	3		T83	3
valid_sources[0x14]	37	1		T152	1		T150	1		T81	2
valid_sources[0x15]	369	1		T154	4		T39	1		T81	3
valid_sources[0x16]	70	1		T152	1		T155	1		T81	4
valid_sources[0x17]	49	1		T147	2		T81	1		T43	1
valid_sources[0x18]	64	1		T80	2		T44	6		T82	14
valid_sources[0x19]	61	1		T156	4		T83	6		T109	1
valid_sources[0x1a]	30	1		T39	3		T81	4		T109	3
valid_sources[0x1b]	75	1		T56	3		T93	2		T81	2
valid_sources[0x1c]	40	1		T157	1		T93	3		T81	8
valid_sources[0x1d]	43	1		T158	1		T43	3		T44	2
valid_sources[0x1e]	38	1		T81	4		T43	1		T109	2
valid_sources[0x1f]	94	1		T159	2		T42	43		T81	1
valid_sources[0x20]	35	1		T85	1		T81	2		T44	2
valid_sources[0x21]	27	1		T160	1		T158	1		T59	1
valid_sources[0x22]	36	1		T161	1		T80	4		T81	2
valid_sources[0x23]	154	1		T81	3		T43	1		T44	10
valid_sources[0x24]	35	1		T152	1		T162	1		T80	2
valid_sources[0x25]	39	1		T152	2		T70	2		T153	1
valid_sources[0x26]	61	1		T39	1		T41	3		T81	3
valid_sources[0x27]	52	1		T153	1		T81	5		T83	3
valid_sources[0x28]	30	1		T44	2		T96	2		T109	2
valid_sources[0x29]	44	1		T163	1		T56	3		T81	8
valid_sources[0x2a]	79	1		T70	1		T159	1		T164	1
valid_sources[0x2b]	66	1		T159	2		T165	1		T93	1
valid_sources[0x2c]	63	1		T166	3		T165	1		T39	1
valid_sources[0x2d]	45	1		T81	4		T97	3		T145	6
valid_sources[0x2e]	44	1		T147	2		T150	1		T162	1
valid_sources[0x2f]	40	1		T81	3		T96	1		T109	1
valid_sources[0x30]	59	1		T167	1		T164	1		T81	2
valid_sources[0x31]	52	1		T164	1		T81	2		T43	1
valid_sources[0x32]	37	1		T34	1		T159	1		T81	5
valid_sources[0x33]	46	1		T148	1		T165	1		T39	1
valid_sources[0x34]	46	1		T64	1		T152	1		T150	1
valid_sources[0x35]	59	1		T168	2		T164	1		T59	1
valid_sources[0x36]	48	1		T59	3		T81	1		T83	2
valid_sources[0x37]	145	1		T49	15		T159	1		T43	1
valid_sources[0x38]	65	1		T80	1		T81	2		T82	25
valid_sources[0x39]	49	1		T39	1		T81	3		T43	1
valid_sources[0x3a]	41	1		T147	1		T85	1		T81	1
valid_sources[0x3b]	33	1		T159	1		T85	1		T81	2
valid_sources[0x3c]	45	1		T43	1		T96	1		T109	4
valid_sources[0x3d]	52	1		T93	2		T81	1		T43	2
valid_sources[0x3e]	51	1		T81	1		T96	1		T109	2
valid_sources[0x3f]	61	1		T158	1		T165	1		T164	1
valid_sources[0x40]	38	1		T81	4		T43	2		T96	2
valid_sources[0x41]	56	1		T152	1		T40	4		T81	1
valid_sources[0x42]	41	1		T154	3		T158	2		T159	1
valid_sources[0x43]	44	1		T169	1		T151	1		T93	1
valid_sources[0x44]	44	1		T39	1		T81	3		T96	2
valid_sources[0x45]	82	1		T39	1		T47	10		T80	3
valid_sources[0x46]	48	1		T170	1		T166	2		T59	1
valid_sources[0x47]	39	1		T165	1		T83	1		T109	2
valid_sources[0x48]	36	1		T93	2		T81	5		T96	3
valid_sources[0x49]	34	1		T72	1		T39	1		T81	4
valid_sources[0x4a]	51	1		T72	1		T150	1		T156	1
valid_sources[0x4b]	47	1		T30	1		T152	1		T171	1
valid_sources[0x4c]	77	1		T29	5		T72	1		T165	1
valid_sources[0x4d]	55	1		T164	1		T172	5		T80	6
valid_sources[0x4e]	39	1		T93	3		T81	5		T96	2
valid_sources[0x4f]	50	1		T81	1		T43	1		T44	2
valid_sources[0x50]	49	1		T147	1		T169	1		T40	1
valid_sources[0x51]	64	1		T167	1		T39	1		T81	1
valid_sources[0x52]	71	1		T53	1		T81	5		T97	5
valid_sources[0x53]	53	1		T153	1		T93	1		T81	3
valid_sources[0x54]	36	1		T39	2		T81	2		T97	4
valid_sources[0x55]	38	1		T151	1		T53	2		T83	2
valid_sources[0x56]	48	1		T151	1		T41	1		T93	2
valid_sources[0x57]	63	1		T150	1		T85	1		T81	1
valid_sources[0x58]	63	1		T146	1		T39	1		T81	8
valid_sources[0x59]	133	1		T55	82		T90	8		T93	2
valid_sources[0x5a]	53	1		T59	4		T54	6		T81	2
valid_sources[0x5b]	48	1		T81	4		T96	2		T97	6
valid_sources[0x5c]	95	1		T46	2		T59	1		T44	3
valid_sources[0x5d]	62	1		T147	1		T166	1		T158	1
valid_sources[0x5e]	65	1		T50	1		T47	17		T85	1
valid_sources[0x5f]	45	1		T53	2		T93	4		T81	3
valid_sources[0x60]	39	1		T39	1		T43	2		T96	1
valid_sources[0x61]	102	1		T81	1		T96	1		T74	2
valid_sources[0x62]	38	1		T158	1		T81	3		T83	1
valid_sources[0x63]	46	1		T165	1		T81	4		T43	2
valid_sources[0x64]	45	1		T173	2		T93	1		T81	3
valid_sources[0x65]	40	1		T152	1		T59	1		T93	2
valid_sources[0x66]	84	1		T42	54		T81	1		T44	5
valid_sources[0x67]	47	1		T158	1		T81	4		T83	2
valid_sources[0x68]	54	1		T174	19		T165	1		T93	1
valid_sources[0x69]	32	1		T162	1		T80	3		T81	2
valid_sources[0x6a]	47	1		T147	1		T152	1		T165	2
valid_sources[0x6b]	64	1		T72	1		T59	1		T81	5
valid_sources[0x6c]	53	1		T159	1		T93	1		T81	3
valid_sources[0x6d]	34	1		T152	1		T153	1		T40	1
valid_sources[0x6e]	142	1		T150	1		T42	100		T81	2
valid_sources[0x6f]	50	1		T167	1		T165	1		T96	1
valid_sources[0x70]	82	1		T175	10		T52	32		T85	1
valid_sources[0x71]	43	1		T162	1		T39	1		T81	5
valid_sources[0x72]	67	1		T152	1		T148	1		T162	1
valid_sources[0x73]	162	1		T42	125		T81	1		T43	1
valid_sources[0x74]	50	1		T171	1		T81	1		T43	1
valid_sources[0x75]	34	1		T64	3		T158	1		T39	1
valid_sources[0x76]	45	1		T151	2		T80	1		T81	4
valid_sources[0x77]	61	1		T81	1		T43	2		T95	1
valid_sources[0x78]	29	1		T59	1		T81	3		T83	1
valid_sources[0x79]	46	1		T81	1		T109	2		T97	1
valid_sources[0x7a]	43	1		T3	9		T48	1		T59	2
valid_sources[0x7b]	34	1		T81	1		T82	2		T96	2
valid_sources[0x7c]	59	1		T34	2		T147	1		T72	1
valid_sources[0x7d]	189	1		T52	145		T93	2		T81	1
valid_sources[0x7e]	76	1		T34	1		T150	1		T94	2
valid_sources[0x7f]	113	1		T148	3		T47	1		T55	47
valid_sources[0x80]	44	1		T152	1		T85	1		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4031

1

T59

11

T45

6

T39

5

values[0x0]

all_enables

biggest_size

4888

1

T2

1

T3

4

T34

1

values[0x1]

all_enables

biggest_size

4883

1

T2

2

T3

1

T34

1