Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	96.30	100.00	88.89				100.00
tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00
tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.30	100.00	88.89				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62
1	1	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T62
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	26385681	26384643	0	0
selKnown1	34908521	34907483	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	26385681	26384643	0	0
T1	354812	354810	0	0
T2	216	214	0	0
T3	220	218	0	0
T7	2188	2186	0	0
T8	14	12	0	0
T9	10	8	0	0
T10	4508	4506	0	0
T11	4811	4808	0	0
T12	249350	249348	0	0
T13	101134	101132	0	0
T15	22	42	0	0
T16	13	24	0	0
T17	0	58	0	0
T23	0	70	0	0
T29	235	232	0	0
T30	1	0	0	0
T34	297	294	0	0
T35	1	0	0	0
T36	0	20	0	0
T46	2	0	0	0
T48	1	0	0	0
T49	1	0	0	0
T57	0	10	0	0
T63	1	0	0	0
T65	2	0	0	0
T129	0	36	0	0
T130	0	55	0	0
T131	0	16	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	34908521	34907483	0	0
T1	257030	257028	0	0
T2	1722	1720	0	0
T3	1552	1550	0	0
T7	7204	7202	0	0
T8	12	10	0	0
T9	10	8	0	0
T10	18429	18427	0	0
T11	7845	7843	0	0
T12	164356	164354	0	0
T13	183582	183580	0	0
T15	44	42	0	0
T16	26	24	0	0
T17	0	58	0	0
T23	0	70	0	0
T26	2	0	0	0
T28	2	0	0	0
T29	1441	1439	0	0
T34	1115	1113	0	0
T36	0	20	0	0
T46	2	0	0	0
T48	2	0	0	0
T49	2	0	0	0
T65	2	0	0	0
T129	0	36	0	0
T130	0	110	0	0
T131	0	32	0	0

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62
1	1	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	10491114	10490953	0	0
selKnown1	19014067	19013906	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	10491114	10490953	0	0
T1	177406	177405	0	0
T2	108	107	0	0
T3	110	109	0	0
T7	1094	1093	0	0
T10	2254	2253	0	0
T11	2404	2403	0	0
T12	124675	124674	0	0
T13	50567	50566	0	0
T29	117	116	0	0
T34	148	147	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	19014067	19013906	0	0
T1	79624	79623	0	0
T2	1614	1613	0	0
T3	1442	1441	0	0
T7	6110	6109	0	0
T10	16175	16174	0	0
T11	5441	5440	0	0
T12	39681	39680	0	0
T13	133015	133014	0	0
T29	1324	1323	0	0
T34	967	966	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62
1	1	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	745	584	0	0
selKnown1	721	560	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	745	584	0	0
T8	7	6	0	0
T9	5	4	0	0
T15	22	21	0	0
T16	13	12	0	0
T17	0	29	0	0
T23	0	35	0	0
T26	1	0	0	0
T28	1	0	0	0
T36	0	10	0	0
T46	1	0	0	0
T48	1	0	0	0
T49	1	0	0	0
T65	1	0	0	0
T129	0	18	0	0
T130	0	55	0	0
T131	0	16	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	721	560	0	0
T8	6	5	0	0
T9	5	4	0	0
T15	22	21	0	0
T16	13	12	0	0
T17	0	29	0	0
T23	0	35	0	0
T26	1	0	0	0
T28	1	0	0	0
T36	0	10	0	0
T46	1	0	0	0
T48	1	0	0	0
T49	1	0	0	0
T65	1	0	0	0
T129	0	18	0	0
T130	0	55	0	0
T131	0	16	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62
1	1	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T62
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	15891996	15891638	0	0
selKnown1	15891996	15891638	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	15891996	15891638	0	0
T1	177406	177405	0	0
T2	108	107	0	0
T3	110	109	0	0
T7	1094	1093	0	0
T10	2254	2253	0	0
T11	2404	2403	0	0
T12	124675	124674	0	0
T13	50567	50566	0	0
T29	117	116	0	0
T34	148	147	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	15891996	15891638	0	0
T1	177406	177405	0	0
T2	108	107	0	0
T3	110	109	0	0
T7	1094	1093	0	0
T10	2254	2253	0	0
T11	2404	2403	0	0
T12	124675	124674	0	0
T13	50567	50566	0	0
T29	117	116	0	0
T34	148	147	0	0

Line Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
17	1	1

---

Cond Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T21,T62
1	1	Covered	T21,T62

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T21,T62
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.dap.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	1826	1468	0	0
selKnown1	1737	1379	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	1826	1468	0	0
T8	7	6	0	0
T9	5	4	0	0
T11	3	2	0	0
T15	0	21	0	0
T16	0	12	0	0
T17	0	29	0	0
T23	0	35	0	0
T29	1	0	0	0
T30	1	0	0	0
T34	1	0	0	0
T35	1	0	0	0
T36	0	10	0	0
T46	1	0	0	0
T57	0	10	0	0
T63	1	0	0	0
T65	1	0	0	0
T129	0	18	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	1737	1379	0	0
T8	6	5	0	0
T9	5	4	0	0
T15	22	21	0	0
T16	13	12	0	0
T17	0	29	0	0
T23	0	35	0	0
T26	1	0	0	0
T28	1	0	0	0
T36	0	10	0	0
T46	1	0	0	0
T48	1	0	0	0
T49	1	0	0	0
T65	1	0	0	0
T129	0	18	0	0
T130	0	55	0	0
T131	0	16	0	0