Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.73 92.60 78.70 89.36 78.21 82.12 97.75 95.34


Total test records in report: 356
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T144 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4049806555 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:56 PM PST 24 419545750 ps
T281 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2477208879 Feb 07 01:57:40 PM PST 24 Feb 07 01:57:43 PM PST 24 62163170 ps
T127 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2989025642 Feb 07 01:57:33 PM PST 24 Feb 07 01:57:40 PM PST 24 284560342 ps
T282 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2602167722 Feb 07 01:57:42 PM PST 24 Feb 07 01:57:48 PM PST 24 191362709 ps
T135 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1737444806 Feb 07 01:57:28 PM PST 24 Feb 07 01:57:32 PM PST 24 313270357 ps
T283 /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.2570889156 Feb 07 01:57:59 PM PST 24 Feb 07 01:58:15 PM PST 24 35802402326 ps
T284 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.682695175 Feb 07 01:57:42 PM PST 24 Feb 07 01:57:44 PM PST 24 62667390 ps
T145 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2221563425 Feb 07 01:57:21 PM PST 24 Feb 07 01:57:26 PM PST 24 275347430 ps
T285 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2582509211 Feb 07 01:57:50 PM PST 24 Feb 07 01:57:53 PM PST 24 406580594 ps
T286 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2950960688 Feb 07 01:57:20 PM PST 24 Feb 07 01:57:31 PM PST 24 1013868748 ps
T153 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3696687676 Feb 07 01:57:54 PM PST 24 Feb 07 01:58:05 PM PST 24 2117032960 ps
T128 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3603003851 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:56 PM PST 24 1688286775 ps
T136 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3975849350 Feb 07 01:57:43 PM PST 24 Feb 07 01:57:45 PM PST 24 50707057 ps
T287 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4249825717 Feb 07 01:57:47 PM PST 24 Feb 07 01:57:49 PM PST 24 58931268 ps
T288 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.575382834 Feb 07 01:57:52 PM PST 24 Feb 07 01:57:56 PM PST 24 169611458 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.423302718 Feb 07 01:57:32 PM PST 24 Feb 07 01:57:34 PM PST 24 65743659 ps
T290 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3877206204 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:57 PM PST 24 278279330 ps
T138 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1143715628 Feb 07 01:57:29 PM PST 24 Feb 07 01:57:33 PM PST 24 196064843 ps
T291 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.878078505 Feb 07 01:57:52 PM PST 24 Feb 07 01:57:54 PM PST 24 44548602 ps
T292 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.902314209 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:31 PM PST 24 73529200 ps
T293 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.862789842 Feb 07 01:58:01 PM PST 24 Feb 07 01:58:04 PM PST 24 29942559 ps
T294 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2101699080 Feb 07 01:57:49 PM PST 24 Feb 07 01:57:57 PM PST 24 403490211 ps
T295 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3604549987 Feb 07 01:57:59 PM PST 24 Feb 07 01:58:04 PM PST 24 58231632 ps
T296 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2152098423 Feb 07 01:57:43 PM PST 24 Feb 07 01:57:45 PM PST 24 179948539 ps
T297 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2066844220 Feb 07 01:57:35 PM PST 24 Feb 07 01:57:37 PM PST 24 374259921 ps
T298 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3969379075 Feb 07 01:57:20 PM PST 24 Feb 07 01:57:24 PM PST 24 1154392138 ps
T299 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3850110088 Feb 07 01:57:21 PM PST 24 Feb 07 01:57:23 PM PST 24 65938687 ps
T300 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1630116767 Feb 07 01:57:40 PM PST 24 Feb 07 01:57:42 PM PST 24 116248886 ps
T301 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1594276991 Feb 07 01:57:38 PM PST 24 Feb 07 01:57:43 PM PST 24 1088362759 ps
T302 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2627128403 Feb 07 01:57:38 PM PST 24 Feb 07 01:57:40 PM PST 24 234137225 ps
T139 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2049462299 Feb 07 01:57:56 PM PST 24 Feb 07 01:57:59 PM PST 24 464528591 ps
T303 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.62744602 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:32 PM PST 24 79343749 ps
T304 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4010847236 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:57 PM PST 24 1239771606 ps
T108 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.244021481 Feb 07 01:57:32 PM PST 24 Feb 07 01:57:35 PM PST 24 218648668 ps
T112 /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.361243330 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:58 PM PST 24 2608179696 ps
T113 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4094265609 Feb 07 01:57:44 PM PST 24 Feb 07 01:57:47 PM PST 24 562237381 ps
T114 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1587389163 Feb 07 01:58:00 PM PST 24 Feb 07 01:58:03 PM PST 24 76637391 ps
T115 /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.664777437 Feb 07 01:57:58 PM PST 24 Feb 07 01:58:23 PM PST 24 14134649158 ps
T116 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2065772147 Feb 07 01:57:17 PM PST 24 Feb 07 01:57:20 PM PST 24 167194705 ps
T117 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4202679833 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:50 PM PST 24 203869961 ps
T118 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3784876689 Feb 07 01:57:22 PM PST 24 Feb 07 01:57:27 PM PST 24 211262611 ps
T119 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4261671212 Feb 07 01:57:51 PM PST 24 Feb 07 01:58:08 PM PST 24 833402266 ps
T305 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2408067213 Feb 07 01:57:55 PM PST 24 Feb 07 01:58:05 PM PST 24 959701138 ps
T306 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1754229602 Feb 07 01:57:35 PM PST 24 Feb 07 01:57:36 PM PST 24 20118843 ps
T307 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3456399094 Feb 07 01:57:38 PM PST 24 Feb 07 01:57:40 PM PST 24 82763607 ps
T308 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2855957811 Feb 07 01:57:57 PM PST 24 Feb 07 01:57:58 PM PST 24 48917527 ps
T309 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4173661023 Feb 07 01:57:48 PM PST 24 Feb 07 01:58:08 PM PST 24 1042814089 ps
T310 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.883930595 Feb 07 01:57:54 PM PST 24 Feb 07 01:57:57 PM PST 24 465345546 ps
T311 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3506881647 Feb 07 01:57:39 PM PST 24 Feb 07 01:57:44 PM PST 24 532971836 ps
T312 /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2295029400 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:52 PM PST 24 606206597 ps
T313 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2002627661 Feb 07 01:57:27 PM PST 24 Feb 07 01:57:29 PM PST 24 29230431 ps
T314 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.176849072 Feb 07 01:57:22 PM PST 24 Feb 07 01:57:23 PM PST 24 120653768 ps
T315 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2925176517 Feb 07 01:57:55 PM PST 24 Feb 07 01:58:01 PM PST 24 1972693186 ps
T150 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.249937166 Feb 07 01:58:01 PM PST 24 Feb 07 01:58:12 PM PST 24 556007973 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2602334816 Feb 07 01:57:19 PM PST 24 Feb 07 01:57:25 PM PST 24 847829250 ps
T317 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.13755058 Feb 07 01:57:49 PM PST 24 Feb 07 01:57:52 PM PST 24 188951547 ps
T155 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.311126599 Feb 07 01:57:43 PM PST 24 Feb 07 01:57:59 PM PST 24 1376930574 ps
T318 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.281376852 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:53 PM PST 24 135286505 ps
T319 /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4221598545 Feb 07 01:57:37 PM PST 24 Feb 07 01:58:00 PM PST 24 14766266801 ps
T320 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.487804607 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:41 PM PST 24 1757219371 ps
T321 /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2471726041 Feb 07 01:57:49 PM PST 24 Feb 07 01:57:54 PM PST 24 527586549 ps
T322 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3833620151 Feb 07 01:58:00 PM PST 24 Feb 07 01:58:03 PM PST 24 37472389 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3954822490 Feb 07 01:57:38 PM PST 24 Feb 07 01:58:16 PM PST 24 3660399847 ps
T324 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1963044780 Feb 07 01:57:26 PM PST 24 Feb 07 01:57:29 PM PST 24 135503377 ps
T325 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3660893785 Feb 07 01:57:28 PM PST 24 Feb 07 01:57:30 PM PST 24 27755827 ps
T109 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3076437016 Feb 07 01:57:33 PM PST 24 Feb 07 01:57:38 PM PST 24 1210245147 ps
T129 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1394050773 Feb 07 01:57:40 PM PST 24 Feb 07 01:57:48 PM PST 24 804637413 ps
T326 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3149453331 Feb 07 01:57:28 PM PST 24 Feb 07 01:58:36 PM PST 24 18306029055 ps
T151 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2406906460 Feb 07 01:57:35 PM PST 24 Feb 07 01:57:45 PM PST 24 554769446 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2316483044 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:32 PM PST 24 513743009 ps
T328 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2864165956 Feb 07 01:57:28 PM PST 24 Feb 07 01:57:52 PM PST 24 5764262104 ps
T154 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4244007492 Feb 07 01:57:31 PM PST 24 Feb 07 01:57:51 PM PST 24 949667525 ps
T329 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4287998502 Feb 07 01:57:40 PM PST 24 Feb 07 01:57:42 PM PST 24 154412288 ps
T110 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2662017728 Feb 07 01:57:27 PM PST 24 Feb 07 01:57:31 PM PST 24 2816296244 ps
T83 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.842769486 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:38 PM PST 24 4461730329 ps
T330 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1269764215 Feb 07 01:57:29 PM PST 24 Feb 07 01:57:31 PM PST 24 53599367 ps
T331 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2455899290 Feb 07 01:57:53 PM PST 24 Feb 07 01:57:56 PM PST 24 57972751 ps
T332 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1194164254 Feb 07 01:57:17 PM PST 24 Feb 07 01:57:38 PM PST 24 7971449748 ps
T333 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3269845218 Feb 07 01:57:59 PM PST 24 Feb 07 01:58:02 PM PST 24 85174900 ps
T334 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3991549567 Feb 07 01:57:53 PM PST 24 Feb 07 01:57:57 PM PST 24 417773600 ps
T130 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2381096469 Feb 07 01:57:39 PM PST 24 Feb 07 01:57:48 PM PST 24 2773901060 ps
T335 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.3039633538 Feb 07 01:57:59 PM PST 24 Feb 07 01:58:15 PM PST 24 5841737725 ps
T336 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3218720694 Feb 07 01:57:28 PM PST 24 Feb 07 01:57:30 PM PST 24 31167259 ps
T337 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3352348437 Feb 07 01:57:35 PM PST 24 Feb 07 01:58:08 PM PST 24 5363012124 ps
T338 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2701410946 Feb 07 01:57:34 PM PST 24 Feb 07 01:57:35 PM PST 24 48096364 ps
T339 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3071707496 Feb 07 01:57:19 PM PST 24 Feb 07 01:57:21 PM PST 24 152770346 ps
T340 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.416833176 Feb 07 01:57:27 PM PST 24 Feb 07 01:57:32 PM PST 24 3966772595 ps
T131 /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2776498548 Feb 07 01:57:57 PM PST 24 Feb 07 01:58:02 PM PST 24 525762054 ps
T341 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1250517767 Feb 07 01:57:36 PM PST 24 Feb 07 01:58:05 PM PST 24 545805355 ps
T342 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2749705030 Feb 07 01:57:30 PM PST 24 Feb 07 01:57:34 PM PST 24 184329410 ps
T111 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.545069685 Feb 07 01:57:35 PM PST 24 Feb 07 01:57:37 PM PST 24 446593107 ps
T343 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2887515482 Feb 07 01:57:25 PM PST 24 Feb 07 01:57:27 PM PST 24 40348085 ps
T344 /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1812257675 Feb 07 01:57:57 PM PST 24 Feb 07 01:58:22 PM PST 24 20879226316 ps
T345 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1569251561 Feb 07 01:57:44 PM PST 24 Feb 07 01:57:55 PM PST 24 3652671639 ps
T346 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2045795278 Feb 07 01:57:19 PM PST 24 Feb 07 01:57:21 PM PST 24 710281586 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.376488593 Feb 07 01:57:22 PM PST 24 Feb 07 01:57:23 PM PST 24 30629318 ps
T348 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3317082291 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:54 PM PST 24 1917059754 ps
T84 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2611968316 Feb 07 01:58:00 PM PST 24 Feb 07 01:58:27 PM PST 24 16575124407 ps
T349 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2340866510 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:55 PM PST 24 367908447 ps
T350 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.419202281 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:53 PM PST 24 132791491 ps
T351 /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3631229762 Feb 07 01:57:27 PM PST 24 Feb 07 01:58:40 PM PST 24 7491071206 ps
T352 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2263622310 Feb 07 01:57:33 PM PST 24 Feb 07 01:57:35 PM PST 24 864206658 ps
T353 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1084193372 Feb 07 01:57:51 PM PST 24 Feb 07 01:57:56 PM PST 24 375904716 ps
T354 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3327412812 Feb 07 01:57:26 PM PST 24 Feb 07 01:58:04 PM PST 24 4005362536 ps
T355 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1949763615 Feb 07 01:57:54 PM PST 24 Feb 07 01:57:59 PM PST 24 66667010 ps
T356 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2991918445 Feb 07 01:57:48 PM PST 24 Feb 07 01:57:58 PM PST 24 541637553 ps

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.40480482
Short name T16
Test name
Test status
Simulation time 5895223482 ps
CPU time 7.67 seconds
Started Feb 07 02:17:19 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 204628 kb
Host smart-cc2b7138-fb6c-41a0-b8a6-4c99fb3b373b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40480482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.40480482
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_stress_all.723672689
Short name T5
Test name
Test status
Simulation time 8904345073 ps
CPU time 8.08 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:50 PM PST 24
Peak memory 204564 kb
Host smart-fcdbb463-4639-4f9b-a39d-75fe89bd6b64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723672689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_stress_all.723672689
Directory /workspace/2.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.4223367906
Short name T44
Test name
Test status
Simulation time 580739862 ps
CPU time 5.12 seconds
Started Feb 07 01:57:34 PM PST 24
Finished Feb 07 01:57:40 PM PST 24
Peak memory 212028 kb
Host smart-37623c1e-fe91-4aea-835e-e87705cae50f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223367906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.4223367906
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2107691131
Short name T29
Test name
Test status
Simulation time 18200294 ps
CPU time 0.66 seconds
Started Feb 07 02:18:22 PM PST 24
Finished Feb 07 02:18:23 PM PST 24
Peak memory 204160 kb
Host smart-bda89363-fad4-4c7a-9c8f-c9c9578f66c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107691131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2107691131
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/23.rv_dm_tap_fsm_rand_reset.3141953432
Short name T55
Test name
Test status
Simulation time 28216798068 ps
CPU time 16.81 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:20 PM PST 24
Peak memory 220276 kb
Host smart-d31b53ad-a352-4e78-925c-7d6466e33c1e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141953432 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 23.rv_dm_tap_fsm_rand_reset.3141953432
Directory /workspace/23.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.2968997118
Short name T40
Test name
Test status
Simulation time 3837185883 ps
CPU time 18.47 seconds
Started Feb 07 01:57:22 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 216012 kb
Host smart-ada8a1f5-28b7-4a73-bcd2-2bcc87fb8d7d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968997118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.2968997118
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.117631181
Short name T33
Test name
Test status
Simulation time 1579192411 ps
CPU time 3.08 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:23 PM PST 24
Peak memory 204408 kb
Host smart-f2065950-529c-4260-8bb1-0080a1c347d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117631181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.117631181
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.372250229
Short name T92
Test name
Test status
Simulation time 1731459102 ps
CPU time 7.63 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 212108 kb
Host smart-14032dbb-24a3-4c48-8a79-fdf66b7acbf9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372250229 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.372250229
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.2163363411
Short name T25
Test name
Test status
Simulation time 13745350053 ps
CPU time 56.9 seconds
Started Feb 07 02:18:18 PM PST 24
Finished Feb 07 02:19:15 PM PST 24
Peak memory 204688 kb
Host smart-fdb247be-fa04-4923-a5f9-76040eaa5c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163363411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.2163363411
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4261671212
Short name T119
Test name
Test status
Simulation time 833402266 ps
CPU time 15.24 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 212048 kb
Host smart-b68b279c-cdf3-4ffb-9e06-5a8507d3f4da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261671212 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
261671212
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.842769486
Short name T83
Test name
Test status
Simulation time 4461730329 ps
CPU time 7.48 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:38 PM PST 24
Peak memory 216452 kb
Host smart-98cd3657-57fe-4f61-bb8b-c928fe7a3ed3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842769486 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.842769486
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.2836641545
Short name T31
Test name
Test status
Simulation time 155294019 ps
CPU time 0.83 seconds
Started Feb 07 02:17:19 PM PST 24
Finished Feb 07 02:17:21 PM PST 24
Peak memory 204196 kb
Host smart-d4bb58da-e5d6-4415-97ee-b4381673bec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836641545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.2836641545
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2864488966
Short name T97
Test name
Test status
Simulation time 19089120025 ps
CPU time 40.39 seconds
Started Feb 07 01:57:19 PM PST 24
Finished Feb 07 01:58:01 PM PST 24
Peak memory 203884 kb
Host smart-bd058a1a-1b0b-4ac0-8616-65022fff64f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864488966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2864488966
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3036661185
Short name T73
Test name
Test status
Simulation time 352062663 ps
CPU time 1.17 seconds
Started Feb 07 02:17:22 PM PST 24
Finished Feb 07 02:17:24 PM PST 24
Peak memory 220324 kb
Host smart-be12a8d9-96a0-4b72-8067-bb57bcabac30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036661185 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3036661185
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.2754215762
Short name T15
Test name
Test status
Simulation time 1194668399 ps
CPU time 2.91 seconds
Started Feb 07 02:17:59 PM PST 24
Finished Feb 07 02:18:03 PM PST 24
Peak memory 204532 kb
Host smart-e61c07ca-859f-4466-a575-a5de34271017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754215762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.2754215762
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3499264738
Short name T54
Test name
Test status
Simulation time 21328745 ps
CPU time 0.69 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:18:29 PM PST 24
Peak memory 204140 kb
Host smart-9d3229f3-ae85-4f7c-9ce4-c49f8d2a3626
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499264738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3499264738
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_stress_all.2528987041
Short name T32
Test name
Test status
Simulation time 1094498865 ps
CPU time 4.41 seconds
Started Feb 07 02:18:30 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 204424 kb
Host smart-7477b367-c636-499a-b747-d35f1186b8b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528987041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_stress_all.2528987041
Directory /workspace/41.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.4010847236
Short name T304
Test name
Test status
Simulation time 1239771606 ps
CPU time 4.02 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 220272 kb
Host smart-29aee2d6-170f-456d-ad4e-6dde45249207
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010847236 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.4010847236
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.2991918445
Short name T356
Test name
Test status
Simulation time 541637553 ps
CPU time 9.36 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 211956 kb
Host smart-f6e8363f-6a6b-41de-bae3-7f1c68dd6b5a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991918445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.2
991918445
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.2414794181
Short name T95
Test name
Test status
Simulation time 1506404008 ps
CPU time 4.23 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:07 PM PST 24
Peak memory 203696 kb
Host smart-4e81cc68-4fcf-4357-a371-e5520d35dbfc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414794181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.2414794181
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.136492072
Short name T86
Test name
Test status
Simulation time 103931240 ps
CPU time 0.68 seconds
Started Feb 07 01:57:23 PM PST 24
Finished Feb 07 01:57:24 PM PST 24
Peak memory 203412 kb
Host smart-2f2a4652-d4de-49a8-ba7c-3f29ca52ab84
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136492072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.136492072
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2662017728
Short name T110
Test name
Test status
Simulation time 2816296244 ps
CPU time 3.1 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203768 kb
Host smart-2b04d278-a54a-4069-a507-f5a097c5cbff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662017728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2662017728
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3440224152
Short name T28
Test name
Test status
Simulation time 553250800 ps
CPU time 1.13 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:26 PM PST 24
Peak memory 203772 kb
Host smart-29d09369-a6b6-4d49-8c23-89d3f7069942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440224152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3440224152
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/29.rv_dm_stress_all.559251966
Short name T30
Test name
Test status
Simulation time 10676412244 ps
CPU time 5.74 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:42 PM PST 24
Peak memory 204512 kb
Host smart-6ff6a435-cdfc-46b1-9f15-a8f745ab5acb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559251966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_stress_all.559251966
Directory /workspace/29.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.3972305952
Short name T261
Test name
Test status
Simulation time 5908748728 ps
CPU time 73.73 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:58:42 PM PST 24
Peak memory 203816 kb
Host smart-b83409e5-9dbf-434d-a6c9-be15bb20baf1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3972305952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.3972305952
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.3789580876
Short name T133
Test name
Test status
Simulation time 85348472 ps
CPU time 2.25 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:33 PM PST 24
Peak memory 203780 kb
Host smart-e6b2e27d-ef83-45a8-9067-5cb22a2071f9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789580876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.3789580876
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.416833176
Short name T340
Test name
Test status
Simulation time 3966772595 ps
CPU time 3.86 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 215828 kb
Host smart-a3e3b787-e2fc-4f2a-a6bb-a020b1e36703
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416833176 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.416833176
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2727505563
Short name T124
Test name
Test status
Simulation time 273890610 ps
CPU time 2.11 seconds
Started Feb 07 01:57:25 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 211852 kb
Host smart-89c2b0ca-dde8-4a41-a5e7-45a5e0515658
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727505563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2727505563
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.1194164254
Short name T332
Test name
Test status
Simulation time 7971449748 ps
CPU time 19.14 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:38 PM PST 24
Peak memory 203692 kb
Host smart-22f38e11-b66f-431c-be8f-fde33c17ca87
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194164254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.1194164254
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.4124522498
Short name T264
Test name
Test status
Simulation time 12332769941 ps
CPU time 23.45 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 203784 kb
Host smart-ad4eb220-ef51-4301-b1d8-ef51dcfea663
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4124522498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_bit_bash.4124522498
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2045795278
Short name T346
Test name
Test status
Simulation time 710281586 ps
CPU time 1.4 seconds
Started Feb 07 01:57:19 PM PST 24
Finished Feb 07 01:57:21 PM PST 24
Peak memory 203748 kb
Host smart-0c066082-95fd-4955-9c13-ee4611e67e93
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045795278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
045795278
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3071707496
Short name T339
Test name
Test status
Simulation time 152770346 ps
CPU time 0.85 seconds
Started Feb 07 01:57:19 PM PST 24
Finished Feb 07 01:57:21 PM PST 24
Peak memory 203448 kb
Host smart-7a53120f-bde9-4763-b0cd-e67d2e1307f2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071707496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3071707496
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3969379075
Short name T298
Test name
Test status
Simulation time 1154392138 ps
CPU time 2.99 seconds
Started Feb 07 01:57:20 PM PST 24
Finished Feb 07 01:57:24 PM PST 24
Peak memory 203624 kb
Host smart-fcf4827e-a1c4-43a1-b018-8ac12a031b82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969379075 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3969379075
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.2065772147
Short name T116
Test name
Test status
Simulation time 167194705 ps
CPU time 0.74 seconds
Started Feb 07 01:57:17 PM PST 24
Finished Feb 07 01:57:20 PM PST 24
Peak memory 203452 kb
Host smart-51d33bf9-5751-41d5-af4d-64cb270e2475
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065772147 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.2065772147
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3850110088
Short name T299
Test name
Test status
Simulation time 65938687 ps
CPU time 0.81 seconds
Started Feb 07 01:57:21 PM PST 24
Finished Feb 07 01:57:23 PM PST 24
Peak memory 203432 kb
Host smart-35db97e8-fcbe-414e-be9e-bce78fc2e2bf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850110088 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
850110088
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.902314209
Short name T292
Test name
Test status
Simulation time 73529200 ps
CPU time 0.63 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203532 kb
Host smart-a2274776-960f-496d-919d-c8f25a385691
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902314209 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_part
ial_access.902314209
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.6869578
Short name T252
Test name
Test status
Simulation time 104211862 ps
CPU time 0.62 seconds
Started Feb 07 01:57:31 PM PST 24
Finished Feb 07 01:57:33 PM PST 24
Peak memory 203428 kb
Host smart-4221c4d1-bab5-4129-8eae-df2cf8fa3de7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6869578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.6869578
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.3083002107
Short name T142
Test name
Test status
Simulation time 588585420 ps
CPU time 6.56 seconds
Started Feb 07 01:57:21 PM PST 24
Finished Feb 07 01:57:28 PM PST 24
Peak memory 203776 kb
Host smart-01aa8468-2b8a-4270-81b0-e342f3a1f0cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083002107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.3083002107
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.1610453269
Short name T103
Test name
Test status
Simulation time 477978489 ps
CPU time 2.78 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:34 PM PST 24
Peak memory 203872 kb
Host smart-d96f05d0-5be4-4a93-96e4-0afdec01f48d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610453269 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.1610453269
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3149453331
Short name T326
Test name
Test status
Simulation time 18306029055 ps
CPU time 66.61 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:58:36 PM PST 24
Peak memory 203800 kb
Host smart-fc08337e-8400-454e-a1da-a9c7d16f5133
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3149453331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3149453331
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.3327412812
Short name T354
Test name
Test status
Simulation time 4005362536 ps
CPU time 36.2 seconds
Started Feb 07 01:57:26 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 203868 kb
Host smart-342fce1e-3ddc-44c8-b869-f6ce960dd76a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327412812 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.3327412812
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2479153170
Short name T59
Test name
Test status
Simulation time 67475454 ps
CPU time 1.6 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 203720 kb
Host smart-7473d672-9d8a-4525-8917-9895566508de
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479153170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2479153170
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2749705030
Short name T342
Test name
Test status
Simulation time 184329410 ps
CPU time 2.23 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:34 PM PST 24
Peak memory 203720 kb
Host smart-ffad09d2-a0e1-4755-88d7-98f6f7e59f39
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749705030 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2749705030
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2590728545
Short name T256
Test name
Test status
Simulation time 6983056600 ps
CPU time 16.85 seconds
Started Feb 07 01:57:21 PM PST 24
Finished Feb 07 01:57:39 PM PST 24
Peak memory 203772 kb
Host smart-6ce7e6fc-9253-4163-830e-ddde3f140aab
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590728545 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2590728545
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.533585979
Short name T101
Test name
Test status
Simulation time 15197241224 ps
CPU time 11.09 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 203784 kb
Host smart-97e7eea9-031f-46f5-a356-7f043036a90b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533585979 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr
_bit_bash.533585979
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.1513552926
Short name T107
Test name
Test status
Simulation time 832906604 ps
CPU time 3.91 seconds
Started Feb 07 01:57:22 PM PST 24
Finished Feb 07 01:57:27 PM PST 24
Peak memory 203740 kb
Host smart-b2f07c19-afaa-4ed9-848a-eb3eeced0822
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513552926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.1513552926
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.4278478709
Short name T277
Test name
Test status
Simulation time 1280556081 ps
CPU time 2.54 seconds
Started Feb 07 01:57:18 PM PST 24
Finished Feb 07 01:57:22 PM PST 24
Peak memory 203620 kb
Host smart-5a4b4997-e97e-4fa4-a2f3-556d95f36430
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278478709 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.4
278478709
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.2602334816
Short name T316
Test name
Test status
Simulation time 847829250 ps
CPU time 3.98 seconds
Started Feb 07 01:57:19 PM PST 24
Finished Feb 07 01:57:25 PM PST 24
Peak memory 203696 kb
Host smart-a8082f33-3b6d-48d1-a741-9ee83fb83dcf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602334816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.2602334816
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2002627661
Short name T313
Test name
Test status
Simulation time 29230431 ps
CPU time 0.67 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 203404 kb
Host smart-7e50bae2-354c-4cf2-8d7b-fcba80eef3e0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002627661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2002627661
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.176849072
Short name T314
Test name
Test status
Simulation time 120653768 ps
CPU time 0.65 seconds
Started Feb 07 01:57:22 PM PST 24
Finished Feb 07 01:57:23 PM PST 24
Peak memory 203452 kb
Host smart-2b738ae6-bd2e-4808-86f7-f7f7c4ce12e2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176849072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.176849072
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2410403006
Short name T120
Test name
Test status
Simulation time 44126410 ps
CPU time 0.67 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203468 kb
Host smart-ad0d0fa5-674f-44bf-8ad4-d37c1971fbf7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410403006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2410403006
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.376488593
Short name T347
Test name
Test status
Simulation time 30629318 ps
CPU time 0.62 seconds
Started Feb 07 01:57:22 PM PST 24
Finished Feb 07 01:57:23 PM PST 24
Peak memory 203444 kb
Host smart-a092d60b-8cd9-4880-9f99-094991caf0f6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376488593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.376488593
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.2221563425
Short name T145
Test name
Test status
Simulation time 275347430 ps
CPU time 4.33 seconds
Started Feb 07 01:57:21 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 203628 kb
Host smart-357860d9-7639-4aa2-a01c-ebdedc36278d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221563425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.2221563425
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3784876689
Short name T118
Test name
Test status
Simulation time 211262611 ps
CPU time 4.68 seconds
Started Feb 07 01:57:22 PM PST 24
Finished Feb 07 01:57:27 PM PST 24
Peak memory 212032 kb
Host smart-4c6355ee-f404-475f-9ff8-ebdc39f7751c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784876689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3784876689
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.2950960688
Short name T286
Test name
Test status
Simulation time 1013868748 ps
CPU time 10.05 seconds
Started Feb 07 01:57:20 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 212196 kb
Host smart-ca2b33cd-df43-4993-b686-bc484afeefb5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950960688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.2950960688
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2295029400
Short name T312
Test name
Test status
Simulation time 606206597 ps
CPU time 2.95 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 214216 kb
Host smart-9f0588f6-d0b3-4480-a63f-d981eb7baea4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295029400 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2295029400
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3991549567
Short name T334
Test name
Test status
Simulation time 417773600 ps
CPU time 2.34 seconds
Started Feb 07 01:57:53 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 203708 kb
Host smart-9e66200b-ba23-4700-8949-5ba52e1df3fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991549567 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3991549567
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4255225720
Short name T247
Test name
Test status
Simulation time 509043421 ps
CPU time 1.45 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:51 PM PST 24
Peak memory 203692 kb
Host smart-9e427525-e87b-4015-a9f4-789fce646dd6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255225720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
4255225720
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.3773298121
Short name T253
Test name
Test status
Simulation time 43210775 ps
CPU time 0.7 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 203468 kb
Host smart-e069374d-7bee-4375-8739-e09dbd93e98c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773298121 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
3773298121
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2336250045
Short name T143
Test name
Test status
Simulation time 395478891 ps
CPU time 7.16 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:58:00 PM PST 24
Peak memory 203760 kb
Host smart-ef867738-9581-4576-9217-a010fea284a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336250045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2336250045
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1949763615
Short name T355
Test name
Test status
Simulation time 66667010 ps
CPU time 3.5 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 212172 kb
Host smart-d30019c7-24e5-4f94-b92a-ed8c1d1c0a4a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949763615 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1949763615
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.761377995
Short name T152
Test name
Test status
Simulation time 6868360638 ps
CPU time 18.39 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 213832 kb
Host smart-528f9967-b62b-49e6-8fba-f0382a86825b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761377995 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.761377995
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.883930595
Short name T310
Test name
Test status
Simulation time 465345546 ps
CPU time 1.98 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 220132 kb
Host smart-8518da92-a986-4847-8768-0eb856e561e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883930595 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.883930595
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.13755058
Short name T317
Test name
Test status
Simulation time 188951547 ps
CPU time 1.6 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 203728 kb
Host smart-145b7fc3-0566-44cc-b311-ca0f0b835ce1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13755058 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.13755058
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.4120765454
Short name T249
Test name
Test status
Simulation time 311972814 ps
CPU time 0.9 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:00 PM PST 24
Peak memory 203680 kb
Host smart-3007cabb-8569-431c-b4a3-bfe0bdf86109
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120765454 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
4120765454
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.419202281
Short name T350
Test name
Test status
Simulation time 132791491 ps
CPU time 0.75 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 203476 kb
Host smart-93b88704-3adc-4de4-b7d9-73269ad4352c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419202281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.419202281
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.3317082291
Short name T348
Test name
Test status
Simulation time 1917059754 ps
CPU time 5.09 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 203760 kb
Host smart-8a3f97b6-0940-4d32-a9cf-92616eb93ce4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317082291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.3317082291
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.575382834
Short name T288
Test name
Test status
Simulation time 169611458 ps
CPU time 3.35 seconds
Started Feb 07 01:57:52 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203860 kb
Host smart-18b77e1c-1975-4de4-9f3c-b154f12a722c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575382834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.575382834
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.934072769
Short name T46
Test name
Test status
Simulation time 3280438199 ps
CPU time 2.79 seconds
Started Feb 07 01:57:55 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 211980 kb
Host smart-46a5b152-5287-4382-a9fd-ac3d89d3bdb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934072769 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.934072769
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.925716359
Short name T269
Test name
Test status
Simulation time 27192298 ps
CPU time 1.4 seconds
Started Feb 07 01:57:47 PM PST 24
Finished Feb 07 01:57:50 PM PST 24
Peak memory 203768 kb
Host smart-365ea637-13ba-4ba5-bbd8-2080a6c9207a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925716359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.925716359
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.4202679833
Short name T117
Test name
Test status
Simulation time 203869961 ps
CPU time 0.94 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:50 PM PST 24
Peak memory 203668 kb
Host smart-600d7729-ba64-4f8a-8aab-e7e933989510
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202679833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
4202679833
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.878078505
Short name T291
Test name
Test status
Simulation time 44548602 ps
CPU time 0.74 seconds
Started Feb 07 01:57:52 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 203388 kb
Host smart-fae818ee-88a4-4037-bfa6-e94b46ae7d66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878078505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.878078505
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1084193372
Short name T353
Test name
Test status
Simulation time 375904716 ps
CPU time 3.95 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203872 kb
Host smart-bf49da8e-e493-4a60-9dcc-9b90f141c102
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084193372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1084193372
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.2180009391
Short name T148
Test name
Test status
Simulation time 959597979 ps
CPU time 15.66 seconds
Started Feb 07 01:57:50 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 211980 kb
Host smart-3c9d3a19-12d4-4f0d-ab8d-186de26746b0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180009391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.2
180009391
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3829972945
Short name T105
Test name
Test status
Simulation time 4128071185 ps
CPU time 4.11 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 212132 kb
Host smart-5b5c4c1a-3faf-4411-adb8-95b0bdb737b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829972945 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3829972945
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.2455899290
Short name T331
Test name
Test status
Simulation time 57972751 ps
CPU time 1.55 seconds
Started Feb 07 01:57:53 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203656 kb
Host smart-e1c5420b-1fc0-4b1b-8148-fa152273a8ae
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455899290 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.2455899290
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.2340866510
Short name T349
Test name
Test status
Simulation time 367908447 ps
CPU time 2.29 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:55 PM PST 24
Peak memory 203660 kb
Host smart-2ed5eae9-14d0-47b1-b102-4bdcd5b01558
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340866510 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
2340866510
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.635278655
Short name T68
Test name
Test status
Simulation time 23342133 ps
CPU time 0.67 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:51 PM PST 24
Peak memory 203472 kb
Host smart-0e143c2e-3fb4-42f0-b0e2-b9769873de4c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635278655 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.635278655
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.3603003851
Short name T128
Test name
Test status
Simulation time 1688286775 ps
CPU time 6.62 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203836 kb
Host smart-a277e7e9-833b-4c91-b622-b8f0e2d68554
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603003851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.3603003851
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.361243330
Short name T112
Test name
Test status
Simulation time 2608179696 ps
CPU time 5.12 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 203948 kb
Host smart-377715d0-e0e5-407d-b579-e8861b8ed4d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361243330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.361243330
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4173661023
Short name T309
Test name
Test status
Simulation time 1042814089 ps
CPU time 18.56 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 215096 kb
Host smart-74136ad8-c409-4dbc-ac1f-d82f0b358846
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173661023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
173661023
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.793765886
Short name T132
Test name
Test status
Simulation time 26189476 ps
CPU time 1.31 seconds
Started Feb 07 01:57:57 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 211788 kb
Host smart-0b87d45f-9092-4f33-a068-ecf3f92519e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793765886 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.793765886
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.2166690291
Short name T262
Test name
Test status
Simulation time 1626205616 ps
CPU time 2.18 seconds
Started Feb 07 01:57:50 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 203644 kb
Host smart-932e3bfe-e280-44cb-98aa-50dd0202ff17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166690291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
2166690291
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.51255350
Short name T259
Test name
Test status
Simulation time 37979347 ps
CPU time 0.67 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:00 PM PST 24
Peak memory 203408 kb
Host smart-399e7f8b-e0c2-4471-be42-5e80e44c338c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51255350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.51255350
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.3877206204
Short name T290
Test name
Test status
Simulation time 278279330 ps
CPU time 4.2 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 203776 kb
Host smart-57203f7f-d490-45ef-8e98-1441a20a69f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877206204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.3877206204
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.4211266853
Short name T175
Test name
Test status
Simulation time 53394824 ps
CPU time 2.73 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 203840 kb
Host smart-22673994-65c3-49f4-85c8-ee48c041762e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211266853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.4211266853
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3696687676
Short name T153
Test name
Test status
Simulation time 2117032960 ps
CPU time 10.4 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:58:05 PM PST 24
Peak memory 212408 kb
Host smart-0a269d06-e1e4-44a5-8bc6-c7ce7596c5f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696687676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
696687676
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2049462299
Short name T139
Test name
Test status
Simulation time 464528591 ps
CPU time 2.14 seconds
Started Feb 07 01:57:56 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 211808 kb
Host smart-1758d30a-33b6-42b2-b69c-64c6377cb952
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049462299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2049462299
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2582509211
Short name T285
Test name
Test status
Simulation time 406580594 ps
CPU time 1.69 seconds
Started Feb 07 01:57:50 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 203728 kb
Host smart-b276b15e-f875-4e20-8650-d52464fec2d0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582509211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2582509211
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4249825717
Short name T287
Test name
Test status
Simulation time 58931268 ps
CPU time 0.73 seconds
Started Feb 07 01:57:47 PM PST 24
Finished Feb 07 01:57:49 PM PST 24
Peak memory 203456 kb
Host smart-4bb550c4-b772-419e-bcdd-d588b938a611
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249825717 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4249825717
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2776498548
Short name T131
Test name
Test status
Simulation time 525762054 ps
CPU time 4.15 seconds
Started Feb 07 01:57:57 PM PST 24
Finished Feb 07 01:58:02 PM PST 24
Peak memory 203648 kb
Host smart-10a15288-77c6-448b-b08f-041530e0da70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776498548 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2776498548
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3181845799
Short name T43
Test name
Test status
Simulation time 508722312 ps
CPU time 3.46 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:02 PM PST 24
Peak memory 203920 kb
Host smart-33ee2625-6a28-45e9-9f2d-0337a2706e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181845799 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3181845799
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2408067213
Short name T305
Test name
Test status
Simulation time 959701138 ps
CPU time 8.97 seconds
Started Feb 07 01:57:55 PM PST 24
Finished Feb 07 01:58:05 PM PST 24
Peak memory 211964 kb
Host smart-54665276-0b85-4d7e-a887-43fbbd8d30c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408067213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
408067213
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.2926561107
Short name T274
Test name
Test status
Simulation time 207845502 ps
CPU time 1.68 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:01 PM PST 24
Peak memory 220164 kb
Host smart-7704839b-abf1-4774-9c30-693f19504a20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926561107 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.2926561107
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3269845218
Short name T333
Test name
Test status
Simulation time 85174900 ps
CPU time 2.3 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:02 PM PST 24
Peak memory 211996 kb
Host smart-d636719d-6b2a-4a00-9713-65e086ed6591
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269845218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3269845218
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2676788113
Short name T266
Test name
Test status
Simulation time 478972495 ps
CPU time 1.32 seconds
Started Feb 07 01:57:55 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 203664 kb
Host smart-6e1ddf4b-0698-4f8b-8563-18ab5664cf48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676788113 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2676788113
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.862789842
Short name T293
Test name
Test status
Simulation time 29942559 ps
CPU time 0.66 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 203360 kb
Host smart-0f0b1f3b-1dff-4ae0-8589-c4435cdd9ec4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862789842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.862789842
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.664777437
Short name T115
Test name
Test status
Simulation time 14134649158 ps
CPU time 23.03 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:23 PM PST 24
Peak memory 228512 kb
Host smart-1a35c318-9db2-4331-8780-0786361c97b4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664777437 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.664777437
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3915779760
Short name T104
Test name
Test status
Simulation time 149552560 ps
CPU time 3.01 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 203936 kb
Host smart-0578ff75-0df8-401a-b727-4f5a81da24ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915779760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3915779760
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.249937166
Short name T150
Test name
Test status
Simulation time 556007973 ps
CPU time 9.37 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:12 PM PST 24
Peak memory 211880 kb
Host smart-f6031229-3f13-4a54-b740-80795c2f608f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249937166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.249937166
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.2925176517
Short name T315
Test name
Test status
Simulation time 1972693186 ps
CPU time 5.93 seconds
Started Feb 07 01:57:55 PM PST 24
Finished Feb 07 01:58:01 PM PST 24
Peak memory 213880 kb
Host smart-3c978b92-c5bb-4bf2-af10-ee3571a6e412
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925176517 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.2925176517
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.584644349
Short name T134
Test name
Test status
Simulation time 296021366 ps
CPU time 2.24 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 203796 kb
Host smart-dc639c78-34a1-48a9-a5ab-754ee51cdc96
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584644349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.584644349
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3497011909
Short name T123
Test name
Test status
Simulation time 723470209 ps
CPU time 1.54 seconds
Started Feb 07 01:57:55 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 203564 kb
Host smart-94db096c-01b2-40d8-a565-de5fe21b59b1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497011909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3497011909
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2855957811
Short name T308
Test name
Test status
Simulation time 48917527 ps
CPU time 0.65 seconds
Started Feb 07 01:57:57 PM PST 24
Finished Feb 07 01:57:58 PM PST 24
Peak memory 203456 kb
Host smart-878af13c-3fc2-4172-9a60-a5b811b1f061
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855957811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2855957811
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3254173962
Short name T96
Test name
Test status
Simulation time 200227917 ps
CPU time 3.82 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 203788 kb
Host smart-ed8cba01-9cd0-43dd-a405-02d60f9663bd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254173962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3254173962
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tap_fsm_rand_reset.1812257675
Short name T344
Test name
Test status
Simulation time 20879226316 ps
CPU time 23.67 seconds
Started Feb 07 01:57:57 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 220288 kb
Host smart-8d01bafc-9c56-4633-bc33-97a671741f73
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812257675 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.rv_dm_tap_fsm_rand_reset.1812257675
Directory /workspace/17.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.2471726041
Short name T321
Test name
Test status
Simulation time 527586549 ps
CPU time 3.06 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 212164 kb
Host smart-06b501d8-51b7-4c9d-b344-1d35a7010251
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471726041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.2471726041
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.531057114
Short name T156
Test name
Test status
Simulation time 60059181 ps
CPU time 1.75 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:01 PM PST 24
Peak memory 211976 kb
Host smart-7a0c02ad-6c79-4858-b755-9e8f2b788e87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531057114 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.531057114
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2820281559
Short name T125
Test name
Test status
Simulation time 85590672 ps
CPU time 2.4 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:07 PM PST 24
Peak memory 211920 kb
Host smart-9fc27719-4750-4cdf-a26c-675cc6f92ff1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820281559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2820281559
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2266717182
Short name T61
Test name
Test status
Simulation time 142371250 ps
CPU time 1.18 seconds
Started Feb 07 01:57:57 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 203716 kb
Host smart-41d00ed5-4f47-4e66-a30f-6e2fbce63f85
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266717182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2266717182
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.3704477562
Short name T279
Test name
Test status
Simulation time 156250480 ps
CPU time 0.67 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 203364 kb
Host smart-0f1a7120-7ef4-4053-8ecf-ce31d3f53f31
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704477562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
3704477562
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2553770104
Short name T126
Test name
Test status
Simulation time 142812127 ps
CPU time 3.48 seconds
Started Feb 07 01:57:58 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 203780 kb
Host smart-0d2b7fbf-22a1-4bd6-8860-1ef09a5bec10
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553770104 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2553770104
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3604549987
Short name T295
Test name
Test status
Simulation time 58231632 ps
CPU time 4 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 212120 kb
Host smart-7662145f-3822-489c-8131-a9e88e4e28dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604549987 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3604549987
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.2816311060
Short name T41
Test name
Test status
Simulation time 447566639 ps
CPU time 8.7 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:12 PM PST 24
Peak memory 211944 kb
Host smart-f585ae05-2161-4359-933d-e525f0187ff2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816311060 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.2
816311060
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.1587389163
Short name T114
Test name
Test status
Simulation time 76637391 ps
CPU time 1.83 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 212004 kb
Host smart-e01177f4-0de7-4d7f-b0ff-6e0ef5724213
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587389163 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.1587389163
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3833620151
Short name T322
Test name
Test status
Simulation time 37472389 ps
CPU time 1.36 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 203724 kb
Host smart-a170f882-da71-46c8-ab93-0b26528cc00a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833620151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3833620151
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.2878807720
Short name T276
Test name
Test status
Simulation time 1349142757 ps
CPU time 2.08 seconds
Started Feb 07 01:58:02 PM PST 24
Finished Feb 07 01:58:06 PM PST 24
Peak memory 203692 kb
Host smart-131fbb53-082f-4947-9f2e-ded4a05e677d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878807720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
2878807720
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1613331574
Short name T273
Test name
Test status
Simulation time 62183486 ps
CPU time 0.8 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:03 PM PST 24
Peak memory 203476 kb
Host smart-3b039acd-c8be-47e0-bcb2-8f4919c81e88
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613331574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1613331574
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.3459702165
Short name T141
Test name
Test status
Simulation time 201846949 ps
CPU time 3.82 seconds
Started Feb 07 01:58:01 PM PST 24
Finished Feb 07 01:58:06 PM PST 24
Peak memory 203876 kb
Host smart-0fa98179-8878-4f40-92b4-10d10793d7ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459702165 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.3459702165
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.3375134797
Short name T147
Test name
Test status
Simulation time 180755679 ps
CPU time 3.01 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 203876 kb
Host smart-3da86dc3-e435-4726-962a-b5f507a24935
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375134797 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.3375134797
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.4174386627
Short name T88
Test name
Test status
Simulation time 818692010 ps
CPU time 16.78 seconds
Started Feb 07 01:58:04 PM PST 24
Finished Feb 07 01:58:22 PM PST 24
Peak memory 212016 kb
Host smart-94bb9c60-7be2-4873-a021-895c8ef492ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174386627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.4
174386627
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.874840593
Short name T268
Test name
Test status
Simulation time 13397083573 ps
CPU time 74.64 seconds
Started Feb 07 01:57:23 PM PST 24
Finished Feb 07 01:58:38 PM PST 24
Peak memory 211984 kb
Host smart-cf9b4c90-4c96-408a-ae1e-b06c28bcf84a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874840593 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.874840593
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3994254359
Short name T60
Test name
Test status
Simulation time 10095225267 ps
CPU time 34.28 seconds
Started Feb 07 01:57:40 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 203828 kb
Host smart-7654b9eb-6de5-444e-84df-506a1f952efe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994254359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3994254359
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.423302718
Short name T289
Test name
Test status
Simulation time 65743659 ps
CPU time 1.46 seconds
Started Feb 07 01:57:32 PM PST 24
Finished Feb 07 01:57:34 PM PST 24
Peak memory 203836 kb
Host smart-641a856a-cb9e-48e6-99b5-7f532dc65675
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423302718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.423302718
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1737444806
Short name T135
Test name
Test status
Simulation time 313270357 ps
CPU time 2.11 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 203808 kb
Host smart-bd4fb487-f6f1-42c4-95ff-5c9391f25bdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737444806 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1737444806
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.430233489
Short name T63
Test name
Test status
Simulation time 26592980374 ps
CPU time 25.95 seconds
Started Feb 07 01:57:21 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 203504 kb
Host smart-d98ecd8f-0131-4fe7-8162-b1d028678413
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430233489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_aliasing.430233489
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1907516063
Short name T271
Test name
Test status
Simulation time 16120667172 ps
CPU time 19.29 seconds
Started Feb 07 01:57:32 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 203756 kb
Host smart-e554549f-492d-428c-a35c-0a1622267835
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907516063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1907516063
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.244021481
Short name T108
Test name
Test status
Simulation time 218648668 ps
CPU time 1.52 seconds
Started Feb 07 01:57:32 PM PST 24
Finished Feb 07 01:57:35 PM PST 24
Peak memory 203728 kb
Host smart-9467bdc0-bec7-4bed-9576-53ea5037fb5a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244021481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.244021481
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2316483044
Short name T327
Test name
Test status
Simulation time 513743009 ps
CPU time 0.92 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 203720 kb
Host smart-73b66ce1-ebbe-48be-89c0-800754cd49e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316483044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
316483044
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.62744602
Short name T303
Test name
Test status
Simulation time 79343749 ps
CPU time 0.71 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:32 PM PST 24
Peak memory 203476 kb
Host smart-170d36e9-9c8a-4196-9f4d-6cc14b685284
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62744602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
aliasing.62744602
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1719548105
Short name T85
Test name
Test status
Simulation time 622013075 ps
CPU time 1.7 seconds
Started Feb 07 01:57:23 PM PST 24
Finished Feb 07 01:57:26 PM PST 24
Peak memory 203620 kb
Host smart-725ad05a-0e73-4002-8858-62fc6423bcd0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719548105 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1719548105
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.3757940779
Short name T258
Test name
Test status
Simulation time 38410071 ps
CPU time 0.7 seconds
Started Feb 07 01:57:20 PM PST 24
Finished Feb 07 01:57:22 PM PST 24
Peak memory 203432 kb
Host smart-a590ef38-f41c-4758-b76a-4dfcc6e57e15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757940779 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.3757940779
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.1963044780
Short name T324
Test name
Test status
Simulation time 135503377 ps
CPU time 0.78 seconds
Started Feb 07 01:57:26 PM PST 24
Finished Feb 07 01:57:29 PM PST 24
Peak memory 203464 kb
Host smart-ccb309da-3dc1-459f-87f1-793e3997d868
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963044780 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.1
963044780
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.3660893785
Short name T325
Test name
Test status
Simulation time 27755827 ps
CPU time 0.62 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:30 PM PST 24
Peak memory 203468 kb
Host smart-3604b7eb-ceee-4359-a186-ca1bcc1ed1f6
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660893785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.3660893785
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.4245688538
Short name T257
Test name
Test status
Simulation time 18557110 ps
CPU time 0.62 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203364 kb
Host smart-c210836d-de53-4b41-af96-6ab6e25a5ab1
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245688538 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.4245688538
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.1169545044
Short name T57
Test name
Test status
Simulation time 783887636 ps
CPU time 7.04 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 203720 kb
Host smart-8fc58023-fd9b-40a3-81a1-4fbc6459128d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169545044 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.1169545044
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.2502124091
Short name T45
Test name
Test status
Simulation time 1307482343 ps
CPU time 2.4 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 212100 kb
Host smart-03a767d7-8c31-416e-9802-4af67c92ff40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502124091 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.2502124091
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.4244007492
Short name T154
Test name
Test status
Simulation time 949667525 ps
CPU time 18.72 seconds
Started Feb 07 01:57:31 PM PST 24
Finished Feb 07 01:57:51 PM PST 24
Peak memory 213928 kb
Host smart-e914d515-9923-4d91-8afc-e47be2205338
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244007492 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.4244007492
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.3962849616
Short name T280
Test name
Test status
Simulation time 3890107957 ps
CPU time 12.97 seconds
Started Feb 07 01:58:05 PM PST 24
Finished Feb 07 01:58:19 PM PST 24
Peak memory 212172 kb
Host smart-705a971d-779b-4f67-885f-c1b5290e5f38
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962849616 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.3962849616
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.782321308
Short name T81
Test name
Test status
Simulation time 4068110448 ps
CPU time 16.45 seconds
Started Feb 07 01:58:03 PM PST 24
Finished Feb 07 01:58:21 PM PST 24
Peak memory 220308 kb
Host smart-4ca7b179-f037-4d02-ab6f-01b0a93bb64f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782321308 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.782321308
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.3039633538
Short name T335
Test name
Test status
Simulation time 5841737725 ps
CPU time 14.12 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 212192 kb
Host smart-e7bc50e1-d035-4e71-8d1e-3577d52a523a
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039633538 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.3039633538
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.3352348437
Short name T337
Test name
Test status
Simulation time 5363012124 ps
CPU time 32.49 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:58:08 PM PST 24
Peak memory 203792 kb
Host smart-67a2ebbb-cccd-40ce-b3a1-cdc327f91546
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352348437 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.3352348437
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.3954822490
Short name T323
Test name
Test status
Simulation time 3660399847 ps
CPU time 36.67 seconds
Started Feb 07 01:57:38 PM PST 24
Finished Feb 07 01:58:16 PM PST 24
Peak memory 203724 kb
Host smart-93c9eaca-918e-4cc1-a859-3cd9d337408c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954822490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.3954822490
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.2887515482
Short name T343
Test name
Test status
Simulation time 40348085 ps
CPU time 1.54 seconds
Started Feb 07 01:57:25 PM PST 24
Finished Feb 07 01:57:27 PM PST 24
Peak memory 203812 kb
Host smart-d629369f-d64f-4764-932d-a5bdbe759ec4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887515482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.2887515482
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2535713607
Short name T58
Test name
Test status
Simulation time 48219326 ps
CPU time 1.42 seconds
Started Feb 07 01:57:33 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 203828 kb
Host smart-58435878-2539-425f-b566-8a7a0c359a4c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535713607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2535713607
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.2864165956
Short name T328
Test name
Test status
Simulation time 5764262104 ps
CPU time 22.43 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:52 PM PST 24
Peak memory 203788 kb
Host smart-b8cbf9eb-2b0e-4e3f-9da6-7ad7e828c3ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864165956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.2864165956
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.3846337732
Short name T278
Test name
Test status
Simulation time 46158084154 ps
CPU time 142.94 seconds
Started Feb 07 01:57:43 PM PST 24
Finished Feb 07 02:00:07 PM PST 24
Peak memory 203780 kb
Host smart-819eaa1b-3753-4f18-b038-a4637dcd0787
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846337732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.3846337732
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3076437016
Short name T109
Test name
Test status
Simulation time 1210245147 ps
CPU time 4.01 seconds
Started Feb 07 01:57:33 PM PST 24
Finished Feb 07 01:57:38 PM PST 24
Peak memory 203808 kb
Host smart-a58172a4-d66e-4561-8f8e-395ab1b35da8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076437016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3076437016
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3891949747
Short name T246
Test name
Test status
Simulation time 908897180 ps
CPU time 1.69 seconds
Started Feb 07 01:57:34 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203704 kb
Host smart-7da4b99a-a044-4cc3-9202-690b3685efb8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891949747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
891949747
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.1080469230
Short name T260
Test name
Test status
Simulation time 53950619 ps
CPU time 0.76 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203392 kb
Host smart-1ec04d17-aef3-4b3a-81db-20cc0fc0de4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080469230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.1080469230
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1594276991
Short name T301
Test name
Test status
Simulation time 1088362759 ps
CPU time 3.4 seconds
Started Feb 07 01:57:38 PM PST 24
Finished Feb 07 01:57:43 PM PST 24
Peak memory 203668 kb
Host smart-22ade196-7922-4bb0-bdc0-c177b3b7b3e6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594276991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1594276991
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3615273035
Short name T255
Test name
Test status
Simulation time 86938527 ps
CPU time 0.95 seconds
Started Feb 07 01:57:34 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 203428 kb
Host smart-2b64bf3f-a7d2-471b-8b6d-f3be2fff7b74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615273035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3615273035
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4287998502
Short name T329
Test name
Test status
Simulation time 154412288 ps
CPU time 1.06 seconds
Started Feb 07 01:57:40 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 203428 kb
Host smart-cee8b8b3-b3f9-498d-9c10-d55ad72cc5e7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287998502 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
287998502
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.3218720694
Short name T336
Test name
Test status
Simulation time 31167259 ps
CPU time 0.63 seconds
Started Feb 07 01:57:28 PM PST 24
Finished Feb 07 01:57:30 PM PST 24
Peak memory 203536 kb
Host smart-69988425-f493-4a98-aa67-542043522db8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218720694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.3218720694
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.2701410946
Short name T338
Test name
Test status
Simulation time 48096364 ps
CPU time 0.64 seconds
Started Feb 07 01:57:34 PM PST 24
Finished Feb 07 01:57:35 PM PST 24
Peak memory 203424 kb
Host smart-0fd813cd-4337-4cd0-b287-c7afc30030b3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701410946 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.2701410946
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.904076728
Short name T98
Test name
Test status
Simulation time 798513443 ps
CPU time 4.22 seconds
Started Feb 07 01:57:36 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 203856 kb
Host smart-5810ce48-3cd4-4bea-901f-dd4c02ff6d9d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904076728 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.904076728
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.3707174966
Short name T102
Test name
Test status
Simulation time 414829785 ps
CPU time 3.14 seconds
Started Feb 07 01:57:43 PM PST 24
Finished Feb 07 01:57:47 PM PST 24
Peak memory 212048 kb
Host smart-d7490cbd-daa0-4dfa-bef1-0fd89ac54279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707174966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.3707174966
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.487804607
Short name T320
Test name
Test status
Simulation time 1757219371 ps
CPU time 9.66 seconds
Started Feb 07 01:57:30 PM PST 24
Finished Feb 07 01:57:41 PM PST 24
Peak memory 211972 kb
Host smart-534d0f3d-b33e-49b6-a2fa-175d6dc561c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487804607 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.487804607
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.2570889156
Short name T283
Test name
Test status
Simulation time 35802402326 ps
CPU time 15.7 seconds
Started Feb 07 01:57:59 PM PST 24
Finished Feb 07 01:58:15 PM PST 24
Peak memory 220300 kb
Host smart-86123828-bcca-4c0c-a84b-14fb57eac936
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570889156 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.2570889156
Directory /workspace/39.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.1250517767
Short name T341
Test name
Test status
Simulation time 545805355 ps
CPU time 27.45 seconds
Started Feb 07 01:57:36 PM PST 24
Finished Feb 07 01:58:05 PM PST 24
Peak memory 203812 kb
Host smart-5bc732be-f825-4d6a-9b49-98c59a4cb70b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250517767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.1250517767
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.3631229762
Short name T351
Test name
Test status
Simulation time 7491071206 ps
CPU time 72.09 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:58:40 PM PST 24
Peak memory 203808 kb
Host smart-f0e10f3f-fd45-45d8-91eb-b5e0c1fbe714
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631229762 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.3631229762
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1143715628
Short name T138
Test name
Test status
Simulation time 196064843 ps
CPU time 2.5 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:33 PM PST 24
Peak memory 203748 kb
Host smart-7c567425-a267-4ec9-9383-ffff54fa6d8c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143715628 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1143715628
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1630116767
Short name T300
Test name
Test status
Simulation time 116248886 ps
CPU time 1.34 seconds
Started Feb 07 01:57:40 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 203764 kb
Host smart-5488a0aa-dc92-4a7c-8d05-545c4ebe117d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630116767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1630116767
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1756060681
Short name T248
Test name
Test status
Simulation time 6628774700 ps
CPU time 27.8 seconds
Started Feb 07 01:57:36 PM PST 24
Finished Feb 07 01:58:05 PM PST 24
Peak memory 203788 kb
Host smart-505394e6-042e-4854-bda1-e53ba756f914
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756060681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1756060681
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.1014364256
Short name T254
Test name
Test status
Simulation time 7292171321 ps
CPU time 15.47 seconds
Started Feb 07 01:57:31 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 203784 kb
Host smart-b5e04e9a-1904-4251-99b5-fc7c543da416
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014364256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.1014364256
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.545069685
Short name T111
Test name
Test status
Simulation time 446593107 ps
CPU time 1.07 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203672 kb
Host smart-843208b4-f0ca-490d-942b-d837767af80a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545069685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr
_hw_reset.545069685
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.2263622310
Short name T352
Test name
Test status
Simulation time 864206658 ps
CPU time 1.1 seconds
Started Feb 07 01:57:33 PM PST 24
Finished Feb 07 01:57:35 PM PST 24
Peak memory 203768 kb
Host smart-29ae5b30-98f6-4d42-b942-ef529b251879
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263622310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.2
263622310
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2467078203
Short name T267
Test name
Test status
Simulation time 78130792 ps
CPU time 0.71 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 203472 kb
Host smart-2049ed23-988c-4099-ae4e-eb20630679cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467078203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2467078203
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2928159909
Short name T121
Test name
Test status
Simulation time 957380624 ps
CPU time 4.44 seconds
Started Feb 07 01:57:27 PM PST 24
Finished Feb 07 01:57:33 PM PST 24
Peak memory 203676 kb
Host smart-fa4f9ba0-6be6-40f7-af77-0dde810cb763
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928159909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2928159909
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3456399094
Short name T307
Test name
Test status
Simulation time 82763607 ps
CPU time 0.7 seconds
Started Feb 07 01:57:38 PM PST 24
Finished Feb 07 01:57:40 PM PST 24
Peak memory 203464 kb
Host smart-5249a8e5-d65c-4842-9ff2-d0da9debbe4a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456399094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3456399094
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1269764215
Short name T330
Test name
Test status
Simulation time 53599367 ps
CPU time 0.71 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203448 kb
Host smart-8781f7dd-3de3-4169-945b-e1a78ce5347e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269764215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
269764215
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1754229602
Short name T306
Test name
Test status
Simulation time 20118843 ps
CPU time 0.72 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:36 PM PST 24
Peak memory 203520 kb
Host smart-564f9981-9ea2-4272-abc4-d4e2922ea378
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754229602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1754229602
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1821143424
Short name T137
Test name
Test status
Simulation time 16690185 ps
CPU time 0.64 seconds
Started Feb 07 01:57:29 PM PST 24
Finished Feb 07 01:57:31 PM PST 24
Peak memory 203412 kb
Host smart-9e2d9fe2-4d5b-4905-b858-bef3c00235f7
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821143424 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1821143424
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.2989025642
Short name T127
Test name
Test status
Simulation time 284560342 ps
CPU time 6.53 seconds
Started Feb 07 01:57:33 PM PST 24
Finished Feb 07 01:57:40 PM PST 24
Peak memory 203760 kb
Host smart-9184fe67-21e9-44a2-951e-210c65871000
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989025642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.2989025642
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2406906460
Short name T151
Test name
Test status
Simulation time 554769446 ps
CPU time 9.64 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:45 PM PST 24
Peak memory 212012 kb
Host smart-db6065dd-4544-4629-bea1-e4b85cb1d2e7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406906460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2406906460
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.865254725
Short name T91
Test name
Test status
Simulation time 50060722 ps
CPU time 2.01 seconds
Started Feb 07 01:57:38 PM PST 24
Finished Feb 07 01:57:41 PM PST 24
Peak memory 213116 kb
Host smart-3a76f167-fabd-4df3-b4bb-231f14827ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865254725 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.865254725
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3055118563
Short name T270
Test name
Test status
Simulation time 176730186 ps
CPU time 1.51 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203716 kb
Host smart-4f707448-8212-49fb-92d7-050bc37926a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055118563 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3055118563
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2627128403
Short name T302
Test name
Test status
Simulation time 234137225 ps
CPU time 1.42 seconds
Started Feb 07 01:57:38 PM PST 24
Finished Feb 07 01:57:40 PM PST 24
Peak memory 203636 kb
Host smart-faf08806-6c1e-4b5b-8325-201a6cae8801
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627128403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2
627128403
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.682695175
Short name T284
Test name
Test status
Simulation time 62667390 ps
CPU time 0.7 seconds
Started Feb 07 01:57:42 PM PST 24
Finished Feb 07 01:57:44 PM PST 24
Peak memory 203408 kb
Host smart-993c17cb-db45-4dd3-815c-da01a4dc060f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682695175 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.682695175
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.2101699080
Short name T294
Test name
Test status
Simulation time 403490211 ps
CPU time 6.37 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:57 PM PST 24
Peak memory 203796 kb
Host smart-7c769c6a-f9e6-4cb2-950c-64ffd6dbf014
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101699080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.2101699080
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3506881647
Short name T311
Test name
Test status
Simulation time 532971836 ps
CPU time 4.8 seconds
Started Feb 07 01:57:39 PM PST 24
Finished Feb 07 01:57:44 PM PST 24
Peak memory 211972 kb
Host smart-14961918-9a0c-4358-90f3-15a018d278e2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506881647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3506881647
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.311126599
Short name T155
Test name
Test status
Simulation time 1376930574 ps
CPU time 15.22 seconds
Started Feb 07 01:57:43 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 211884 kb
Host smart-eff86648-7105-4c1a-b00f-540aa0400ca7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311126599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.311126599
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1623244038
Short name T82
Test name
Test status
Simulation time 1735049227 ps
CPU time 4.36 seconds
Started Feb 07 01:57:41 PM PST 24
Finished Feb 07 01:57:46 PM PST 24
Peak memory 212120 kb
Host smart-5eded4dc-365b-4ede-bc50-c5ac38c6c947
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623244038 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1623244038
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4094265609
Short name T113
Test name
Test status
Simulation time 562237381 ps
CPU time 2.42 seconds
Started Feb 07 01:57:44 PM PST 24
Finished Feb 07 01:57:47 PM PST 24
Peak memory 203760 kb
Host smart-5c29b504-0abd-445a-bc42-3221c783b04f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094265609 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4094265609
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.1170908525
Short name T265
Test name
Test status
Simulation time 751909917 ps
CPU time 1.64 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203728 kb
Host smart-a128e564-3fed-4425-8de7-9cde627b83d8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170908525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.1
170908525
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.463875677
Short name T275
Test name
Test status
Simulation time 35674744 ps
CPU time 0.65 seconds
Started Feb 07 01:57:42 PM PST 24
Finished Feb 07 01:57:44 PM PST 24
Peak memory 203472 kb
Host smart-e3113ca0-c47b-4ba4-996d-f5c07c2efcad
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463875677 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.463875677
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2381096469
Short name T130
Test name
Test status
Simulation time 2773901060 ps
CPU time 7.86 seconds
Started Feb 07 01:57:39 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 203764 kb
Host smart-5cb416de-2040-43f8-9b8d-d4083e5e2b25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381096469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2381096469
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3582417694
Short name T272
Test name
Test status
Simulation time 216596682 ps
CPU time 4.56 seconds
Started Feb 07 01:57:36 PM PST 24
Finished Feb 07 01:57:42 PM PST 24
Peak memory 212140 kb
Host smart-8dd6bcf9-12f3-4976-b231-051ebe19e1db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582417694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3582417694
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.2846033901
Short name T42
Test name
Test status
Simulation time 648021283 ps
CPU time 9.59 seconds
Started Feb 07 01:57:39 PM PST 24
Finished Feb 07 01:57:50 PM PST 24
Peak memory 211984 kb
Host smart-0de29f18-7bed-4dd4-8c8b-37fa2320229b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846033901 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.2846033901
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.3975849350
Short name T136
Test name
Test status
Simulation time 50707057 ps
CPU time 1.38 seconds
Started Feb 07 01:57:43 PM PST 24
Finished Feb 07 01:57:45 PM PST 24
Peak memory 203768 kb
Host smart-0d5dc752-35ac-4ca9-893a-e9459d732ffb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975849350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.3975849350
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2066844220
Short name T297
Test name
Test status
Simulation time 374259921 ps
CPU time 1.52 seconds
Started Feb 07 01:57:35 PM PST 24
Finished Feb 07 01:57:37 PM PST 24
Peak memory 203616 kb
Host smart-cfc04c88-bf6b-4702-be63-c3f27bd64f5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066844220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
066844220
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.2299587947
Short name T263
Test name
Test status
Simulation time 56341542 ps
CPU time 0.67 seconds
Started Feb 07 01:57:45 PM PST 24
Finished Feb 07 01:57:47 PM PST 24
Peak memory 203452 kb
Host smart-d8af3d5e-db8f-4f6d-80d8-2a7ae8018e2a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299587947 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.2
299587947
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1394050773
Short name T129
Test name
Test status
Simulation time 804637413 ps
CPU time 7.49 seconds
Started Feb 07 01:57:40 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 203704 kb
Host smart-b59c9c20-6435-40e6-b3f3-46780921940d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394050773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1394050773
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2602167722
Short name T282
Test name
Test status
Simulation time 191362709 ps
CPU time 4.38 seconds
Started Feb 07 01:57:42 PM PST 24
Finished Feb 07 01:57:48 PM PST 24
Peak memory 203932 kb
Host smart-942427ef-30d7-4385-a744-bcda4d165ccf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2602167722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2602167722
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1569251561
Short name T345
Test name
Test status
Simulation time 3652671639 ps
CPU time 10.82 seconds
Started Feb 07 01:57:44 PM PST 24
Finished Feb 07 01:57:55 PM PST 24
Peak memory 212796 kb
Host smart-c0c413ae-d5ff-4c64-ae63-9ffd6f85f355
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569251561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1569251561
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.3538883055
Short name T99
Test name
Test status
Simulation time 43085761 ps
CPU time 2.17 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:51 PM PST 24
Peak memory 211872 kb
Host smart-8e099cdd-fd10-4cdc-9f76-6457f7cf189d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538883055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.3538883055
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2073931871
Short name T251
Test name
Test status
Simulation time 193343595 ps
CPU time 0.92 seconds
Started Feb 07 01:57:45 PM PST 24
Finished Feb 07 01:57:47 PM PST 24
Peak memory 203664 kb
Host smart-3c72c437-33a1-4a4d-aed4-2dc0a95e8851
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073931871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
073931871
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2152098423
Short name T296
Test name
Test status
Simulation time 179948539 ps
CPU time 0.78 seconds
Started Feb 07 01:57:43 PM PST 24
Finished Feb 07 01:57:45 PM PST 24
Peak memory 203308 kb
Host smart-28a10511-dfb6-4429-b319-da9f8619494b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152098423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
152098423
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.4049806555
Short name T144
Test name
Test status
Simulation time 419545750 ps
CPU time 3.76 seconds
Started Feb 07 01:57:51 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203764 kb
Host smart-f44beb60-326a-4dc6-bb24-5dcde5ccb9b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049806555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.4049806555
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tap_fsm_rand_reset.4221598545
Short name T319
Test name
Test status
Simulation time 14766266801 ps
CPU time 21.87 seconds
Started Feb 07 01:57:37 PM PST 24
Finished Feb 07 01:58:00 PM PST 24
Peak memory 212196 kb
Host smart-3387155c-647f-4107-9ea3-07cefc4d1b6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221598545 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rv_dm_tap_fsm_rand_reset.4221598545
Directory /workspace/8.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2477208879
Short name T281
Test name
Test status
Simulation time 62163170 ps
CPU time 2.01 seconds
Started Feb 07 01:57:40 PM PST 24
Finished Feb 07 01:57:43 PM PST 24
Peak memory 203776 kb
Host smart-3b80e45c-6787-431c-905b-b43c1faad195
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477208879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2477208879
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.1703151711
Short name T87
Test name
Test status
Simulation time 3875120828 ps
CPU time 20.22 seconds
Started Feb 07 01:57:42 PM PST 24
Finished Feb 07 01:58:04 PM PST 24
Peak memory 215688 kb
Host smart-f2a7c68f-c77b-4c5f-b0e5-6de8f596a5c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703151711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.1703151711
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.281376852
Short name T318
Test name
Test status
Simulation time 135286505 ps
CPU time 3.22 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:53 PM PST 24
Peak memory 220156 kb
Host smart-c66719fc-41b6-4a1e-81a6-734a14457189
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281376852 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.281376852
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.2283945358
Short name T56
Test name
Test status
Simulation time 90980698 ps
CPU time 1.45 seconds
Started Feb 07 01:57:53 PM PST 24
Finished Feb 07 01:57:56 PM PST 24
Peak memory 203784 kb
Host smart-b22263c0-3991-4e09-af3d-2157bace461d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283945358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.2283945358
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.222271140
Short name T250
Test name
Test status
Simulation time 314751085 ps
CPU time 1.4 seconds
Started Feb 07 01:57:48 PM PST 24
Finished Feb 07 01:57:50 PM PST 24
Peak memory 203752 kb
Host smart-1099582b-20a2-48f1-ad50-91fcc893bfba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222271140 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.222271140
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.261586307
Short name T122
Test name
Test status
Simulation time 86971946 ps
CPU time 0.72 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:57:55 PM PST 24
Peak memory 203368 kb
Host smart-731aa0dd-26ef-459d-b9bd-5d4010432ad2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261586307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.261586307
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.1212395966
Short name T140
Test name
Test status
Simulation time 456458513 ps
CPU time 4.03 seconds
Started Feb 07 01:57:54 PM PST 24
Finished Feb 07 01:57:59 PM PST 24
Peak memory 203696 kb
Host smart-92f12f9e-84e3-409f-b07f-8fd145265c41
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212395966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.1212395966
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2611968316
Short name T84
Test name
Test status
Simulation time 16575124407 ps
CPU time 26.16 seconds
Started Feb 07 01:58:00 PM PST 24
Finished Feb 07 01:58:27 PM PST 24
Peak memory 220380 kb
Host smart-724baecb-0259-4a25-b021-d802b20725c4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611968316 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2611968316
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2943104223
Short name T62
Test name
Test status
Simulation time 504943936 ps
CPU time 3.54 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:57:54 PM PST 24
Peak memory 212044 kb
Host smart-e926dd01-ec07-4dc2-8b57-4dafe97e2ffb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943104223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2943104223
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.4138495102
Short name T149
Test name
Test status
Simulation time 2079749654 ps
CPU time 20.08 seconds
Started Feb 07 01:57:49 PM PST 24
Finished Feb 07 01:58:11 PM PST 24
Peak memory 215292 kb
Host smart-a94c933c-2d43-448b-9d34-022a11666f5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138495102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.4138495102
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.107095952
Short name T168
Test name
Test status
Simulation time 84483210 ps
CPU time 0.65 seconds
Started Feb 07 02:17:20 PM PST 24
Finished Feb 07 02:17:22 PM PST 24
Peak memory 204164 kb
Host smart-8f474340-b15d-4b02-9f90-8586b814cb7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107095952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.107095952
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.290360902
Short name T13
Test name
Test status
Simulation time 937274995 ps
CPU time 4.07 seconds
Started Feb 07 02:17:23 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 204284 kb
Host smart-313f370a-2c47-48f6-b920-8325e3127bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290360902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.290360902
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2952817298
Short name T4
Test name
Test status
Simulation time 1000755667 ps
CPU time 2.55 seconds
Started Feb 07 02:17:28 PM PST 24
Finished Feb 07 02:17:31 PM PST 24
Peak memory 204392 kb
Host smart-f44889a9-d67c-43af-8ae2-537426c9eca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952817298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2952817298
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.3503747333
Short name T158
Test name
Test status
Simulation time 75629569 ps
CPU time 0.67 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:26 PM PST 24
Peak memory 203992 kb
Host smart-7a9a5099-3f53-4c64-bae6-f2a4fcdad51b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503747333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.3503747333
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.1305080210
Short name T219
Test name
Test status
Simulation time 369264114 ps
CPU time 1.77 seconds
Started Feb 07 02:17:16 PM PST 24
Finished Feb 07 02:17:19 PM PST 24
Peak memory 204568 kb
Host smart-045486b2-dd55-4ae4-9565-fde51faae8d3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305080210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.1305080210
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2085408722
Short name T93
Test name
Test status
Simulation time 708613675 ps
CPU time 1.42 seconds
Started Feb 07 02:17:30 PM PST 24
Finished Feb 07 02:17:32 PM PST 24
Peak memory 204452 kb
Host smart-769885e3-2433-43c5-a19b-dba6f0b9a298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085408722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2085408722
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3705849999
Short name T22
Test name
Test status
Simulation time 83285987 ps
CPU time 0.65 seconds
Started Feb 07 02:17:17 PM PST 24
Finished Feb 07 02:17:19 PM PST 24
Peak memory 204052 kb
Host smart-2ed00998-69ba-4d64-a415-52b9d2ec0499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705849999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3705849999
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1770434707
Short name T19
Test name
Test status
Simulation time 111105762 ps
CPU time 0.77 seconds
Started Feb 07 02:17:26 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 203800 kb
Host smart-bbd8f6bc-c81d-44d9-832e-9f1095e27a2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770434707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1770434707
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1131067403
Short name T23
Test name
Test status
Simulation time 124778507 ps
CPU time 0.94 seconds
Started Feb 07 02:17:25 PM PST 24
Finished Feb 07 02:17:27 PM PST 24
Peak memory 204112 kb
Host smart-5c647786-f54b-4f8a-b850-3dad590dc472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131067403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1131067403
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.3039779388
Short name T64
Test name
Test status
Simulation time 606047037 ps
CPU time 1.19 seconds
Started Feb 07 02:17:21 PM PST 24
Finished Feb 07 02:17:23 PM PST 24
Peak memory 204340 kb
Host smart-19d088f0-14b1-4b36-8a01-ab8b61caa53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039779388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.3039779388
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3445523902
Short name T67
Test name
Test status
Simulation time 44395546 ps
CPU time 0.84 seconds
Started Feb 07 02:17:28 PM PST 24
Finished Feb 07 02:17:30 PM PST 24
Peak memory 204088 kb
Host smart-f9f6e84b-4050-428d-a54f-ac0566686788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445523902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3445523902
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2818486066
Short name T9
Test name
Test status
Simulation time 1466023652 ps
CPU time 1.06 seconds
Started Feb 07 02:17:26 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 204212 kb
Host smart-49875002-8791-47a3-951a-8dd9bb9ada4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818486066 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2818486066
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2419059945
Short name T146
Test name
Test status
Simulation time 73212685 ps
CPU time 0.88 seconds
Started Feb 07 02:17:25 PM PST 24
Finished Feb 07 02:17:26 PM PST 24
Peak memory 203832 kb
Host smart-79a5fb50-5588-49f3-8c42-ad16669bc844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419059945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2419059945
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.2248612357
Short name T20
Test name
Test status
Simulation time 2235831174 ps
CPU time 1.31 seconds
Started Feb 07 02:17:25 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 204528 kb
Host smart-30edab18-f767-4f58-bcee-ddd9aa1dc708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248612357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.2248612357
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.3988809801
Short name T207
Test name
Test status
Simulation time 3281573779 ps
CPU time 13.22 seconds
Started Feb 07 02:17:19 PM PST 24
Finished Feb 07 02:17:34 PM PST 24
Peak memory 204728 kb
Host smart-9c06dc76-98d7-4b28-911b-afaa14630076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988809801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.3988809801
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.185910301
Short name T230
Test name
Test status
Simulation time 187013151 ps
CPU time 1.19 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:27 PM PST 24
Peak memory 203972 kb
Host smart-c1de7b91-ead0-4461-b4c4-eb13ed23dd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185910301 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.185910301
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.2926636597
Short name T65
Test name
Test status
Simulation time 1639815120 ps
CPU time 3.11 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:28 PM PST 24
Peak memory 204320 kb
Host smart-5eb40446-b2f3-4992-be65-85680d2e1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926636597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.2926636597
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2963479773
Short name T216
Test name
Test status
Simulation time 50029718 ps
CPU time 0.63 seconds
Started Feb 07 02:17:36 PM PST 24
Finished Feb 07 02:17:38 PM PST 24
Peak memory 204148 kb
Host smart-7e622c92-4f1d-42b5-9a19-7fd0c76556f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963479773 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2963479773
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.227672645
Short name T217
Test name
Test status
Simulation time 4528034414 ps
CPU time 7.08 seconds
Started Feb 07 02:17:19 PM PST 24
Finished Feb 07 02:17:27 PM PST 24
Peak memory 204504 kb
Host smart-75ab568c-05b4-4522-8488-feff67598523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227672645 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.227672645
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.2578424225
Short name T11
Test name
Test status
Simulation time 464215931 ps
CPU time 0.88 seconds
Started Feb 07 02:17:28 PM PST 24
Finished Feb 07 02:17:30 PM PST 24
Peak memory 204120 kb
Host smart-6091e751-9819-4563-b3aa-ba3e73c6da1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578424225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.2578424225
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1933942600
Short name T27
Test name
Test status
Simulation time 3607771072 ps
CPU time 3.1 seconds
Started Feb 07 02:17:27 PM PST 24
Finished Feb 07 02:17:31 PM PST 24
Peak memory 204604 kb
Host smart-31e42162-19c2-4974-853d-85bb06f4148f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933942600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1933942600
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.451628863
Short name T242
Test name
Test status
Simulation time 52409506 ps
CPU time 0.76 seconds
Started Feb 07 02:17:24 PM PST 24
Finished Feb 07 02:17:26 PM PST 24
Peak memory 204184 kb
Host smart-6ae30928-38da-49f8-bed6-d242fb2b57e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451628863 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.451628863
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1784127018
Short name T204
Test name
Test status
Simulation time 4104956114 ps
CPU time 6.74 seconds
Started Feb 07 02:17:29 PM PST 24
Finished Feb 07 02:17:37 PM PST 24
Peak memory 204588 kb
Host smart-f80c4f1e-d213-478e-87ca-f422fac3292b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1784127018 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1784127018
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.4242496627
Short name T8
Test name
Test status
Simulation time 135714137 ps
CPU time 1.2 seconds
Started Feb 07 02:17:35 PM PST 24
Finished Feb 07 02:17:37 PM PST 24
Peak memory 204412 kb
Host smart-a479528f-af46-40e8-a559-2713238ed61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242496627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.4242496627
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.3060104190
Short name T214
Test name
Test status
Simulation time 92000365 ps
CPU time 0.66 seconds
Started Feb 07 02:17:23 PM PST 24
Finished Feb 07 02:17:24 PM PST 24
Peak memory 203880 kb
Host smart-26395a77-115d-43e0-9b26-109436391be7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060104190 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.3060104190
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.1962157766
Short name T1
Test name
Test status
Simulation time 950444607 ps
CPU time 0.79 seconds
Started Feb 07 02:17:42 PM PST 24
Finished Feb 07 02:17:44 PM PST 24
Peak memory 203940 kb
Host smart-d9dfec0a-d6b4-42d1-a6bf-37f8abf68823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962157766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.1962157766
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.670635631
Short name T224
Test name
Test status
Simulation time 112248767 ps
CPU time 0.69 seconds
Started Feb 07 02:17:36 PM PST 24
Finished Feb 07 02:17:37 PM PST 24
Peak memory 203972 kb
Host smart-df786b3d-6f9f-43e2-a709-3c72cdddadb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670635631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.670635631
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3705015671
Short name T66
Test name
Test status
Simulation time 65533345 ps
CPU time 0.64 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 204060 kb
Host smart-b32df885-a703-41cd-91ac-02e1cf03cb69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705015671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3705015671
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.1195205978
Short name T236
Test name
Test status
Simulation time 59140584 ps
CPU time 0.81 seconds
Started Feb 07 02:17:20 PM PST 24
Finished Feb 07 02:17:22 PM PST 24
Peak memory 204168 kb
Host smart-a83366e0-7378-44dd-9352-d13a4142265a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195205978 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.1195205978
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.2467102608
Short name T7
Test name
Test status
Simulation time 696031101 ps
CPU time 1.63 seconds
Started Feb 07 02:17:18 PM PST 24
Finished Feb 07 02:17:21 PM PST 24
Peak memory 204296 kb
Host smart-c96a6e90-387e-4f2c-82d2-51905f4247ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467102608 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.2467102608
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2733925340
Short name T94
Test name
Test status
Simulation time 1203442467 ps
CPU time 2.96 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 204420 kb
Host smart-9fdc4549-17a9-4ea3-9c39-404ead32c134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733925340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2733925340
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1875453964
Short name T223
Test name
Test status
Simulation time 10191216521 ps
CPU time 13.53 seconds
Started Feb 07 02:17:20 PM PST 24
Finished Feb 07 02:17:35 PM PST 24
Peak memory 204624 kb
Host smart-2f73373e-c349-4598-ac41-79881695da3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875453964 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1875453964
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.912127054
Short name T74
Test name
Test status
Simulation time 358034292 ps
CPU time 1.11 seconds
Started Feb 07 02:17:42 PM PST 24
Finished Feb 07 02:17:45 PM PST 24
Peak memory 220532 kb
Host smart-faf70539-6106-4477-802a-21dd794e8fcd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912127054 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.912127054
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2972823010
Short name T205
Test name
Test status
Simulation time 449615388 ps
CPU time 0.9 seconds
Started Feb 07 02:17:30 PM PST 24
Finished Feb 07 02:17:32 PM PST 24
Peak memory 204084 kb
Host smart-4461baa2-9234-4f62-9fe2-e8399727fb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972823010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2972823010
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.1838758975
Short name T169
Test name
Test status
Simulation time 43133556 ps
CPU time 0.69 seconds
Started Feb 07 02:17:50 PM PST 24
Finished Feb 07 02:17:51 PM PST 24
Peak memory 204156 kb
Host smart-fe778c1e-f50e-445b-9b84-71b5882de62d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838758975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.1838758975
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.661815629
Short name T80
Test name
Test status
Simulation time 2800993125 ps
CPU time 10.47 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:18:00 PM PST 24
Peak memory 204608 kb
Host smart-e47a0fa4-8d46-42fd-94d3-ffd06abddb45
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=661815629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.661815629
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1064807579
Short name T190
Test name
Test status
Simulation time 14042814351 ps
CPU time 45.15 seconds
Started Feb 07 02:17:48 PM PST 24
Finished Feb 07 02:18:34 PM PST 24
Peak memory 204564 kb
Host smart-c5dd2c17-3e0d-4656-a51c-ead4f2f0937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064807579 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1064807579
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3357163418
Short name T178
Test name
Test status
Simulation time 61313793 ps
CPU time 0.64 seconds
Started Feb 07 02:17:51 PM PST 24
Finished Feb 07 02:17:52 PM PST 24
Peak memory 204172 kb
Host smart-eae1052d-7f2b-4445-a22f-5d78fcda6b39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357163418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3357163418
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.3664741473
Short name T203
Test name
Test status
Simulation time 6577956982 ps
CPU time 12.1 seconds
Started Feb 07 02:17:52 PM PST 24
Finished Feb 07 02:18:05 PM PST 24
Peak memory 204644 kb
Host smart-24c78814-6fa7-4776-bd79-6221585119e6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3664741473 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.3664741473
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.193827036
Short name T243
Test name
Test status
Simulation time 3901217662 ps
CPU time 5.44 seconds
Started Feb 07 02:17:50 PM PST 24
Finished Feb 07 02:17:56 PM PST 24
Peak memory 204672 kb
Host smart-d38f3b8a-c420-459e-ba96-906fe8819df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193827036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.193827036
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3319460244
Short name T196
Test name
Test status
Simulation time 23370340 ps
CPU time 0.66 seconds
Started Feb 07 02:17:47 PM PST 24
Finished Feb 07 02:17:49 PM PST 24
Peak memory 204156 kb
Host smart-3ebeb493-dbf5-42ca-9d55-dca8306a26af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319460244 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3319460244
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1284632240
Short name T228
Test name
Test status
Simulation time 12861981341 ps
CPU time 40.06 seconds
Started Feb 07 02:17:59 PM PST 24
Finished Feb 07 02:18:40 PM PST 24
Peak memory 204692 kb
Host smart-a21e190d-08c6-4ce8-8af0-bc9790caea7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284632240 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1284632240
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.2024113248
Short name T34
Test name
Test status
Simulation time 10915028478 ps
CPU time 36.54 seconds
Started Feb 07 02:17:52 PM PST 24
Finished Feb 07 02:18:29 PM PST 24
Peak memory 204612 kb
Host smart-6ffc23a9-f29e-4632-a24d-ce7b25c011ee
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2024113248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.2024113248
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.469881186
Short name T47
Test name
Test status
Simulation time 4544185959 ps
CPU time 17.84 seconds
Started Feb 07 02:17:59 PM PST 24
Finished Feb 07 02:18:18 PM PST 24
Peak memory 204624 kb
Host smart-fcb71c40-5f98-4ec7-9844-4b90802ed251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469881186 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.469881186
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.826732446
Short name T179
Test name
Test status
Simulation time 23212610 ps
CPU time 0.63 seconds
Started Feb 07 02:17:47 PM PST 24
Finished Feb 07 02:17:49 PM PST 24
Peak memory 204180 kb
Host smart-92b50d6c-c937-4152-8bcb-8452a0affa10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826732446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.826732446
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.3628343225
Short name T210
Test name
Test status
Simulation time 1384737384 ps
CPU time 3.2 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:04 PM PST 24
Peak memory 204568 kb
Host smart-b74939e9-ba4b-436c-8c51-28c91bd397d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628343225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.3628343225
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2090142141
Short name T186
Test name
Test status
Simulation time 1093356943 ps
CPU time 1.94 seconds
Started Feb 07 02:17:50 PM PST 24
Finished Feb 07 02:17:53 PM PST 24
Peak memory 204476 kb
Host smart-e1571c4a-1cab-42cf-8ab0-3805fb3f6425
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2090142141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2090142141
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.1511036205
Short name T220
Test name
Test status
Simulation time 1301277263 ps
CPU time 7.25 seconds
Started Feb 07 02:17:48 PM PST 24
Finished Feb 07 02:17:57 PM PST 24
Peak memory 204504 kb
Host smart-2150bcc9-40ee-4d79-975a-3cd89285898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511036205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.1511036205
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_stress_all.846101106
Short name T6
Test name
Test status
Simulation time 838674577 ps
CPU time 3.3 seconds
Started Feb 07 02:17:53 PM PST 24
Finished Feb 07 02:17:57 PM PST 24
Peak memory 204456 kb
Host smart-e95223ed-94c9-4370-b131-c982fbf3d63e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846101106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_stress_all.846101106
Directory /workspace/13.rv_dm_stress_all/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.2700368821
Short name T173
Test name
Test status
Simulation time 22085514 ps
CPU time 0.7 seconds
Started Feb 07 02:17:53 PM PST 24
Finished Feb 07 02:17:54 PM PST 24
Peak memory 204164 kb
Host smart-c3f87898-464f-4bee-aba4-4140405e1230
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700368821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.2700368821
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.2360373555
Short name T240
Test name
Test status
Simulation time 34858776564 ps
CPU time 63.74 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:18:54 PM PST 24
Peak memory 204592 kb
Host smart-06527ae6-7dc2-4371-b76b-a633680282c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2360373555 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.2360373555
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2122692126
Short name T231
Test name
Test status
Simulation time 4700078343 ps
CPU time 15.38 seconds
Started Feb 07 02:17:50 PM PST 24
Finished Feb 07 02:18:06 PM PST 24
Peak memory 204572 kb
Host smart-8ab94d17-bfd4-4967-8de5-66a0a52e5663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122692126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2122692126
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3734142270
Short name T209
Test name
Test status
Simulation time 1438231589 ps
CPU time 3.25 seconds
Started Feb 07 02:17:51 PM PST 24
Finished Feb 07 02:17:55 PM PST 24
Peak memory 204472 kb
Host smart-29a2ca4b-d034-4d94-aad1-2ca90f6ea2aa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3734142270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3734142270
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.1269779171
Short name T199
Test name
Test status
Simulation time 4109378533 ps
CPU time 5.69 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:17:55 PM PST 24
Peak memory 204644 kb
Host smart-0e15bc51-3d27-415f-bbe0-52e57f4bf882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269779171 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.1269779171
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.3069040465
Short name T182
Test name
Test status
Simulation time 24176271 ps
CPU time 0.68 seconds
Started Feb 07 02:17:59 PM PST 24
Finished Feb 07 02:18:00 PM PST 24
Peak memory 204108 kb
Host smart-1f67a967-1746-4be8-8e6d-d49a286d237c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069040465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.3069040465
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.208211343
Short name T191
Test name
Test status
Simulation time 2116323488 ps
CPU time 2.07 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:03 PM PST 24
Peak memory 204516 kb
Host smart-4fd4ee42-f5d5-4f7b-b2a6-4336bfba2d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208211343 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.208211343
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3618600671
Short name T244
Test name
Test status
Simulation time 2733478872 ps
CPU time 9.32 seconds
Started Feb 07 02:17:48 PM PST 24
Finished Feb 07 02:17:59 PM PST 24
Peak memory 204636 kb
Host smart-0b64d106-a541-4c9b-96de-3eece553cfcc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618600671 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3618600671
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_stress_all.1142019785
Short name T14
Test name
Test status
Simulation time 3572565702 ps
CPU time 12.01 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:13 PM PST 24
Peak memory 204592 kb
Host smart-86fe5faa-703a-4a91-b133-7214a27ef2c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142019785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_stress_all.1142019785
Directory /workspace/15.rv_dm_stress_all/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.187150696
Short name T171
Test name
Test status
Simulation time 62523026 ps
CPU time 0.7 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:02 PM PST 24
Peak memory 204180 kb
Host smart-3e6c21e1-256e-4d69-8594-a77ec4103ab4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187150696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.187150696
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.3635909788
Short name T225
Test name
Test status
Simulation time 1866928195 ps
CPU time 6.66 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:07 PM PST 24
Peak memory 204544 kb
Host smart-81751ad8-c34b-469d-98be-8b954c7a8e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635909788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.3635909788
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2483229181
Short name T195
Test name
Test status
Simulation time 11431376334 ps
CPU time 35.26 seconds
Started Feb 07 02:17:51 PM PST 24
Finished Feb 07 02:18:27 PM PST 24
Peak memory 204568 kb
Host smart-1dec9ed7-8191-42e7-8504-c480e9fe451c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483229181 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2483229181
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2107762150
Short name T229
Test name
Test status
Simulation time 2188110353 ps
CPU time 7.97 seconds
Started Feb 07 02:17:51 PM PST 24
Finished Feb 07 02:18:00 PM PST 24
Peak memory 204620 kb
Host smart-8f68ca24-29da-44cf-a29f-15f57fffe335
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2107762150 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2107762150
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2424093678
Short name T201
Test name
Test status
Simulation time 9242714289 ps
CPU time 17.33 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:18 PM PST 24
Peak memory 204628 kb
Host smart-17d10c7b-c1d3-4064-9b4a-ec1ea95de4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424093678 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2424093678
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_stress_all.2805185989
Short name T157
Test name
Test status
Simulation time 572007809 ps
CPU time 2.62 seconds
Started Feb 07 02:18:00 PM PST 24
Finished Feb 07 02:18:03 PM PST 24
Peak memory 204424 kb
Host smart-c575743f-8f07-42b7-b39c-b9e150ca66dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805185989 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_stress_all.2805185989
Directory /workspace/16.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.49654168
Short name T36
Test name
Test status
Simulation time 50883163 ps
CPU time 0.64 seconds
Started Feb 07 02:18:10 PM PST 24
Finished Feb 07 02:18:11 PM PST 24
Peak memory 204144 kb
Host smart-bafbb0d1-0c1e-4ca0-81c9-4ebab9bc2ea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49654168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.49654168
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1898736155
Short name T227
Test name
Test status
Simulation time 1647821154 ps
CPU time 8.78 seconds
Started Feb 07 02:17:54 PM PST 24
Finished Feb 07 02:18:04 PM PST 24
Peak memory 204456 kb
Host smart-c6dd0167-982d-434f-b476-b34a309c36f3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898736155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1898736155
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3798640352
Short name T213
Test name
Test status
Simulation time 4258459643 ps
CPU time 5.1 seconds
Started Feb 07 02:17:55 PM PST 24
Finished Feb 07 02:18:01 PM PST 24
Peak memory 204632 kb
Host smart-7caa984d-9d73-4104-ac36-dbe597aa1496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798640352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3798640352
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1170110379
Short name T163
Test name
Test status
Simulation time 47300828 ps
CPU time 0.64 seconds
Started Feb 07 02:18:29 PM PST 24
Finished Feb 07 02:18:31 PM PST 24
Peak memory 204128 kb
Host smart-a724ea15-07c7-4f8a-ac76-4ea611d8c691
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170110379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1170110379
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1339696602
Short name T17
Test name
Test status
Simulation time 11834769213 ps
CPU time 34.05 seconds
Started Feb 07 02:18:15 PM PST 24
Finished Feb 07 02:18:50 PM PST 24
Peak memory 204696 kb
Host smart-dd366473-a7ce-492f-a69c-94dda6ec22a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339696602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1339696602
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2743524038
Short name T75
Test name
Test status
Simulation time 2014731051 ps
CPU time 5.27 seconds
Started Feb 07 02:18:18 PM PST 24
Finished Feb 07 02:18:24 PM PST 24
Peak memory 204476 kb
Host smart-25c85301-6fe7-4cec-b6c7-8b10a752a5d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2743524038 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2743524038
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.1926411183
Short name T212
Test name
Test status
Simulation time 1306984967 ps
CPU time 7.32 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:27 PM PST 24
Peak memory 204604 kb
Host smart-f4261e00-23b7-4790-bd83-d1ad7a1a562c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926411183 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.1926411183
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.4067660632
Short name T79
Test name
Test status
Simulation time 51956295 ps
CPU time 0.66 seconds
Started Feb 07 02:18:24 PM PST 24
Finished Feb 07 02:18:25 PM PST 24
Peak memory 204164 kb
Host smart-b122f772-a864-4619-9398-37592145c55a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067660632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.4067660632
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3736781868
Short name T187
Test name
Test status
Simulation time 1691714290 ps
CPU time 3.53 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:23 PM PST 24
Peak memory 204540 kb
Host smart-c97b14f1-d502-4a76-91f0-2aa457a2b80e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736781868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3736781868
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.387482894
Short name T71
Test name
Test status
Simulation time 11535116263 ps
CPU time 36.26 seconds
Started Feb 07 02:18:16 PM PST 24
Finished Feb 07 02:18:53 PM PST 24
Peak memory 204576 kb
Host smart-be759cae-58e6-4c73-8744-d5b6b01baffa
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=387482894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.387482894
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2591923280
Short name T233
Test name
Test status
Simulation time 1813367170 ps
CPU time 4.36 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:40 PM PST 24
Peak memory 204504 kb
Host smart-b429d4c2-2998-4380-9117-1fe57142e0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591923280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2591923280
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_stress_all.3616065977
Short name T18
Test name
Test status
Simulation time 1572313834 ps
CPU time 2.93 seconds
Started Feb 07 02:18:27 PM PST 24
Finished Feb 07 02:18:30 PM PST 24
Peak memory 204516 kb
Host smart-dda2fc97-7f09-4c7a-8561-78fa5254ed85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616065977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_stress_all.3616065977
Directory /workspace/19.rv_dm_stress_all/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.804817041
Short name T241
Test name
Test status
Simulation time 24681463 ps
CPU time 0.65 seconds
Started Feb 07 02:17:42 PM PST 24
Finished Feb 07 02:17:44 PM PST 24
Peak memory 204160 kb
Host smart-dfe19532-048f-4648-8abd-590dcf2471d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804817041 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.804817041
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.827192871
Short name T24
Test name
Test status
Simulation time 28235181950 ps
CPU time 72.37 seconds
Started Feb 07 02:17:34 PM PST 24
Finished Feb 07 02:18:47 PM PST 24
Peak memory 204648 kb
Host smart-a3169f81-fc0e-4bf1-b74a-a336fc68a229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827192871 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.827192871
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.1080630366
Short name T208
Test name
Test status
Simulation time 7061005879 ps
CPU time 5.15 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:46 PM PST 24
Peak memory 204632 kb
Host smart-2a7cdfaa-40ea-4d11-9e10-d3bf191cd331
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080630366 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.1080630366
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.1918486630
Short name T206
Test name
Test status
Simulation time 145407097 ps
CPU time 0.67 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204108 kb
Host smart-7bf3a842-7e46-43d2-bd69-cc930f4f8db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918486630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.1918486630
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.1408546099
Short name T100
Test name
Test status
Simulation time 11274196433 ps
CPU time 31.82 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:18:11 PM PST 24
Peak memory 204672 kb
Host smart-edca0661-214b-42e7-9102-c8bfa079b632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408546099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.1408546099
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2070454504
Short name T37
Test name
Test status
Simulation time 112751132 ps
CPU time 1.12 seconds
Started Feb 07 02:17:36 PM PST 24
Finished Feb 07 02:17:38 PM PST 24
Peak memory 220176 kb
Host smart-d06ac159-abda-47d1-9b62-48e7d6656e81
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070454504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2070454504
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.689278457
Short name T172
Test name
Test status
Simulation time 49438249 ps
CPU time 0.64 seconds
Started Feb 07 02:18:21 PM PST 24
Finished Feb 07 02:18:23 PM PST 24
Peak memory 204160 kb
Host smart-37731800-fdcb-4733-a925-415ebf4f83fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689278457 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.689278457
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.3273149009
Short name T237
Test name
Test status
Simulation time 138603446 ps
CPU time 0.63 seconds
Started Feb 07 02:18:26 PM PST 24
Finished Feb 07 02:18:27 PM PST 24
Peak memory 204156 kb
Host smart-f8fb7fe6-7357-4d9e-9981-2dbf41fe0f32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273149009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.3273149009
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3570684435
Short name T90
Test name
Test status
Simulation time 24898229 ps
CPU time 0.65 seconds
Started Feb 07 02:18:21 PM PST 24
Finished Feb 07 02:18:23 PM PST 24
Peak memory 204156 kb
Host smart-658eee70-1591-4212-9876-a08a0484be9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570684435 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3570684435
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.4239301716
Short name T170
Test name
Test status
Simulation time 24736021 ps
CPU time 0.71 seconds
Started Feb 07 02:18:25 PM PST 24
Finished Feb 07 02:18:27 PM PST 24
Peak memory 204164 kb
Host smart-baed9a9e-9c74-4203-94f1-ad14a120586d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239301716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.4239301716
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.1341694953
Short name T164
Test name
Test status
Simulation time 45650602 ps
CPU time 0.64 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 204164 kb
Host smart-d2ba17fd-98ec-4082-8767-9181865e373c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341694953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.1341694953
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1386628873
Short name T50
Test name
Test status
Simulation time 51021604 ps
CPU time 0.62 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:35 PM PST 24
Peak memory 204160 kb
Host smart-e199cf8d-11bd-4976-b886-88726a120ea1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386628873 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1386628873
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.619630062
Short name T180
Test name
Test status
Simulation time 23909369 ps
CPU time 0.68 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 204164 kb
Host smart-e5cfa57a-c77d-4677-9336-bf3ba6d77ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619630062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.619630062
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.132719976
Short name T52
Test name
Test status
Simulation time 48528677 ps
CPU time 0.64 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 204168 kb
Host smart-c2b03102-ad57-4bda-879c-aa49ce631654
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132719976 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.132719976
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3318986223
Short name T183
Test name
Test status
Simulation time 18995159 ps
CPU time 0.63 seconds
Started Feb 07 02:18:33 PM PST 24
Finished Feb 07 02:18:35 PM PST 24
Peak memory 204160 kb
Host smart-6a2c6061-9c7d-4eef-91f8-be426f106c59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318986223 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3318986223
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1273889327
Short name T166
Test name
Test status
Simulation time 137914800 ps
CPU time 0.67 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204168 kb
Host smart-e11f104e-d160-4890-bd44-dbda2c503065
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273889327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1273889327
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1260379261
Short name T26
Test name
Test status
Simulation time 1734187383 ps
CPU time 6.4 seconds
Started Feb 07 02:17:33 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204468 kb
Host smart-d2c6acf4-0cc2-4486-a326-ab065312842e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260379261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1260379261
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.3200318261
Short name T245
Test name
Test status
Simulation time 965798753 ps
CPU time 2.22 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204580 kb
Host smart-03ef8179-320c-45b3-8b53-f44afa185daa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200318261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.3200318261
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.4080354591
Short name T239
Test name
Test status
Simulation time 2072316486 ps
CPU time 5.54 seconds
Started Feb 07 02:17:31 PM PST 24
Finished Feb 07 02:17:38 PM PST 24
Peak memory 204552 kb
Host smart-7d58a223-61f9-4d72-adfe-6074cccdb912
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4080354591 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.4080354591
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.160531942
Short name T192
Test name
Test status
Simulation time 166478185 ps
CPU time 0.75 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204104 kb
Host smart-8ca1a31c-39e5-47c4-9f49-8e06218be412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160531942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.160531942
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.3908913580
Short name T35
Test name
Test status
Simulation time 980907311 ps
CPU time 5.67 seconds
Started Feb 07 02:17:34 PM PST 24
Finished Feb 07 02:17:40 PM PST 24
Peak memory 204460 kb
Host smart-72028436-ffba-4f8d-9fe0-a39699cf1e99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908913580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.3908913580
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.1222803370
Short name T39
Test name
Test status
Simulation time 399555158 ps
CPU time 1.32 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 220388 kb
Host smart-6bd238a8-36b1-456d-aa56-90883a4e284d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222803370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.1222803370
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4199914890
Short name T177
Test name
Test status
Simulation time 20382503 ps
CPU time 0.64 seconds
Started Feb 07 02:18:34 PM PST 24
Finished Feb 07 02:18:36 PM PST 24
Peak memory 204144 kb
Host smart-5a626889-2190-4222-8bc2-1c83fd9a80eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199914890 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4199914890
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.106203956
Short name T53
Test name
Test status
Simulation time 18461807 ps
CPU time 0.66 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:20 PM PST 24
Peak memory 204128 kb
Host smart-e86c0d4f-a919-4704-b78f-97b7975a8b4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106203956 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.106203956
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.779134713
Short name T174
Test name
Test status
Simulation time 17893725 ps
CPU time 0.66 seconds
Started Feb 07 02:18:09 PM PST 24
Finished Feb 07 02:18:10 PM PST 24
Peak memory 204072 kb
Host smart-fc6ad682-1ed6-4011-9a91-b264ea9a9407
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779134713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.779134713
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.4049648875
Short name T77
Test name
Test status
Simulation time 29300720 ps
CPU time 0.67 seconds
Started Feb 07 02:18:18 PM PST 24
Finished Feb 07 02:18:19 PM PST 24
Peak memory 204156 kb
Host smart-c52176be-9845-4b93-a232-6e93d266e845
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049648875 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.4049648875
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3894900315
Short name T159
Test name
Test status
Simulation time 25187782 ps
CPU time 0.71 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:20 PM PST 24
Peak memory 204120 kb
Host smart-65df5938-c4b1-4ec2-89d1-e921608936f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3894900315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3894900315
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.2278222599
Short name T162
Test name
Test status
Simulation time 28042844 ps
CPU time 0.68 seconds
Started Feb 07 02:18:07 PM PST 24
Finished Feb 07 02:18:09 PM PST 24
Peak memory 204172 kb
Host smart-885863f2-3658-4223-b482-18bfa5e49a9e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278222599 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.2278222599
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.4100976194
Short name T202
Test name
Test status
Simulation time 24877326 ps
CPU time 0.67 seconds
Started Feb 07 02:18:20 PM PST 24
Finished Feb 07 02:18:22 PM PST 24
Peak memory 204172 kb
Host smart-68370f89-c112-4bc7-9644-99c0ad33bb2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100976194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.4100976194
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3810312561
Short name T176
Test name
Test status
Simulation time 33214609 ps
CPU time 0.66 seconds
Started Feb 07 02:18:25 PM PST 24
Finished Feb 07 02:18:26 PM PST 24
Peak memory 204196 kb
Host smart-55ae0b41-5373-46fb-8879-958d8e122cfe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810312561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3810312561
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3595295062
Short name T49
Test name
Test status
Simulation time 28334663 ps
CPU time 0.65 seconds
Started Feb 07 02:18:21 PM PST 24
Finished Feb 07 02:18:22 PM PST 24
Peak memory 204152 kb
Host smart-b7a2622f-94cf-4bce-9c30-fb0267ac7bc8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595295062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3595295062
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.3124347373
Short name T161
Test name
Test status
Simulation time 46581611 ps
CPU time 0.64 seconds
Started Feb 07 02:18:22 PM PST 24
Finished Feb 07 02:18:24 PM PST 24
Peak memory 204160 kb
Host smart-517711f4-3420-4f7f-842a-4cb80702d1c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124347373 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.3124347373
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.570418860
Short name T160
Test name
Test status
Simulation time 46210145 ps
CPU time 0.66 seconds
Started Feb 07 02:17:34 PM PST 24
Finished Feb 07 02:17:36 PM PST 24
Peak memory 204148 kb
Host smart-425dcedf-b5ed-4603-bb61-3f749999d84e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570418860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.570418860
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.2116780888
Short name T215
Test name
Test status
Simulation time 4801833265 ps
CPU time 7.86 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:47 PM PST 24
Peak memory 204652 kb
Host smart-c0c3c80f-0482-43c3-834b-be2b4db8cfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116780888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.2116780888
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.2699185918
Short name T70
Test name
Test status
Simulation time 2084913353 ps
CPU time 6.85 seconds
Started Feb 07 02:17:35 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 204412 kb
Host smart-0143920e-6f98-474c-b218-1224d71f15e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699185918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.2699185918
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.2283922760
Short name T238
Test name
Test status
Simulation time 11327075995 ps
CPU time 20.2 seconds
Started Feb 07 02:17:42 PM PST 24
Finished Feb 07 02:18:03 PM PST 24
Peak memory 204620 kb
Host smart-03d6f126-0066-4691-92d2-6597e5fa3b78
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2283922760 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.2283922760
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1776600221
Short name T10
Test name
Test status
Simulation time 171145629 ps
CPU time 0.86 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 203880 kb
Host smart-0b8ff326-dec6-4145-85d9-067a2400ed0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776600221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1776600221
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.353533860
Short name T106
Test name
Test status
Simulation time 4807742878 ps
CPU time 8.95 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:48 PM PST 24
Peak memory 204596 kb
Host smart-e39896da-25a0-4b81-831e-0f86a12883ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353533860 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.353533860
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3463543383
Short name T38
Test name
Test status
Simulation time 232891211 ps
CPU time 1.25 seconds
Started Feb 07 02:17:34 PM PST 24
Finished Feb 07 02:17:35 PM PST 24
Peak memory 220424 kb
Host smart-e0a04954-7ec9-4c32-81fc-946aa688a213
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463543383 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3463543383
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1355826061
Short name T198
Test name
Test status
Simulation time 21672646 ps
CPU time 0.65 seconds
Started Feb 07 02:18:23 PM PST 24
Finished Feb 07 02:18:24 PM PST 24
Peak memory 204184 kb
Host smart-8304b523-eb8c-42eb-aa86-b981a018f670
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355826061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1355826061
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.2318664467
Short name T188
Test name
Test status
Simulation time 27253746 ps
CPU time 0.68 seconds
Started Feb 07 02:18:24 PM PST 24
Finished Feb 07 02:18:25 PM PST 24
Peak memory 204164 kb
Host smart-9b24e5de-fa95-4787-8921-ef69e3f8264f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318664467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.2318664467
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.3052530661
Short name T78
Test name
Test status
Simulation time 14356919 ps
CPU time 0.67 seconds
Started Feb 07 02:18:26 PM PST 24
Finished Feb 07 02:18:27 PM PST 24
Peak memory 204112 kb
Host smart-99cce74e-a632-4018-992c-148016c1087e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052530661 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.3052530661
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.772692848
Short name T51
Test name
Test status
Simulation time 66803879 ps
CPU time 0.63 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:21 PM PST 24
Peak memory 204148 kb
Host smart-a2df7fd8-3dec-4a77-a97f-13c00fa58b3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772692848 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.772692848
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_stress_all.470370313
Short name T21
Test name
Test status
Simulation time 2812265360 ps
CPU time 5.2 seconds
Started Feb 07 02:18:19 PM PST 24
Finished Feb 07 02:18:25 PM PST 24
Peak memory 204556 kb
Host smart-544e3d91-33ad-4082-8174-9ee3bfbf2db5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470370313 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_stress_all.470370313
Directory /workspace/43.rv_dm_stress_all/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1462307815
Short name T200
Test name
Test status
Simulation time 32994718 ps
CPU time 0.64 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:18:29 PM PST 24
Peak memory 204152 kb
Host smart-1ea947c1-3b09-4b75-8f8b-a352fe25a8a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462307815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1462307815
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.4012739792
Short name T2
Test name
Test status
Simulation time 111546101 ps
CPU time 0.65 seconds
Started Feb 07 02:18:28 PM PST 24
Finished Feb 07 02:18:29 PM PST 24
Peak memory 204112 kb
Host smart-4ab9f818-8a10-4021-a22f-832b70742776
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012739792 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.4012739792
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2517753619
Short name T185
Test name
Test status
Simulation time 35164424 ps
CPU time 0.7 seconds
Started Feb 07 02:18:20 PM PST 24
Finished Feb 07 02:18:22 PM PST 24
Peak memory 204064 kb
Host smart-76a6a494-b2be-4cca-b4b1-674b3993f10f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517753619 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2517753619
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.4144951907
Short name T189
Test name
Test status
Simulation time 18308848 ps
CPU time 0.67 seconds
Started Feb 07 02:18:20 PM PST 24
Finished Feb 07 02:18:22 PM PST 24
Peak memory 204120 kb
Host smart-61381cd2-4e42-4a5a-907e-e946d3331045
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144951907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.4144951907
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.546929172
Short name T181
Test name
Test status
Simulation time 15960515 ps
CPU time 0.64 seconds
Started Feb 07 02:18:31 PM PST 24
Finished Feb 07 02:18:32 PM PST 24
Peak memory 204172 kb
Host smart-07e95c56-9c18-4314-8a59-67c81b2b512c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546929172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.546929172
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.338957846
Short name T184
Test name
Test status
Simulation time 23464502 ps
CPU time 0.69 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:42 PM PST 24
Peak memory 204132 kb
Host smart-a50fe916-41c2-483d-9f35-803014e8e877
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338957846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.338957846
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.1647370504
Short name T235
Test name
Test status
Simulation time 1697967445 ps
CPU time 3.8 seconds
Started Feb 07 02:17:43 PM PST 24
Finished Feb 07 02:17:48 PM PST 24
Peak memory 204452 kb
Host smart-f4c83421-2022-4504-bf38-4effd64be25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647370504 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.1647370504
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1730376496
Short name T218
Test name
Test status
Simulation time 6155261776 ps
CPU time 17.12 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:58 PM PST 24
Peak memory 204684 kb
Host smart-69e7a48b-7176-45e6-95aa-52ed2154f1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730376496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1730376496
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3466979327
Short name T76
Test name
Test status
Simulation time 4271866183 ps
CPU time 11.43 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:50 PM PST 24
Peak memory 204576 kb
Host smart-5e085352-ba7c-4a62-bce7-c8311ff4df60
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3466979327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3466979327
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1133791712
Short name T232
Test name
Test status
Simulation time 695628757 ps
CPU time 2.67 seconds
Started Feb 07 02:17:33 PM PST 24
Finished Feb 07 02:17:37 PM PST 24
Peak memory 204564 kb
Host smart-fdf0b119-e2b2-4539-97a2-5c574d0db787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133791712 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1133791712
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.2831005662
Short name T48
Test name
Test status
Simulation time 25573739 ps
CPU time 0.61 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204168 kb
Host smart-78cd329f-b92c-436d-a627-a7c1b23b7648
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831005662 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.2831005662
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.2223260908
Short name T211
Test name
Test status
Simulation time 824216406 ps
CPU time 4.85 seconds
Started Feb 07 02:17:43 PM PST 24
Finished Feb 07 02:17:49 PM PST 24
Peak memory 204452 kb
Host smart-bba17d4b-f887-4043-8548-4e5648bc8237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223260908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.2223260908
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.3239922428
Short name T72
Test name
Test status
Simulation time 2992619549 ps
CPU time 3.74 seconds
Started Feb 07 02:17:37 PM PST 24
Finished Feb 07 02:17:42 PM PST 24
Peak memory 204636 kb
Host smart-3d8fb6f4-f0d4-47b9-84e9-0063d390b774
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3239922428 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.3239922428
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1766540237
Short name T194
Test name
Test status
Simulation time 2388194694 ps
CPU time 2.41 seconds
Started Feb 07 02:17:42 PM PST 24
Finished Feb 07 02:17:45 PM PST 24
Peak memory 204708 kb
Host smart-145213ff-3768-4180-842d-a0fefce10f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766540237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1766540237
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.4210451821
Short name T89
Test name
Test status
Simulation time 53745167 ps
CPU time 0.63 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:41 PM PST 24
Peak memory 204168 kb
Host smart-cd1d33fb-cd00-4b51-b73b-15b833bfe278
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210451821 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.4210451821
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.905873520
Short name T234
Test name
Test status
Simulation time 9239554809 ps
CPU time 14.04 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:52 PM PST 24
Peak memory 204600 kb
Host smart-c4ba0a62-83bb-44fb-b2ef-5129a0cfaac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905873520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.905873520
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2650074468
Short name T197
Test name
Test status
Simulation time 3420591368 ps
CPU time 5.11 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:17:55 PM PST 24
Peak memory 204592 kb
Host smart-b6c0c203-9a43-41d3-b5ab-e7a5eb265ce7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650074468 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2650074468
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1838676782
Short name T226
Test name
Test status
Simulation time 7214840816 ps
CPU time 22.32 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:18:04 PM PST 24
Peak memory 204624 kb
Host smart-2f1960b3-a5cd-4606-8eae-3906d0162df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838676782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1838676782
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1714763764
Short name T167
Test name
Test status
Simulation time 57989129 ps
CPU time 0.64 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:40 PM PST 24
Peak memory 204188 kb
Host smart-6e6c4363-0824-4026-8faf-a90108f50003
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714763764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1714763764
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.986205529
Short name T69
Test name
Test status
Simulation time 3304150513 ps
CPU time 13.22 seconds
Started Feb 07 02:17:38 PM PST 24
Finished Feb 07 02:17:52 PM PST 24
Peak memory 204640 kb
Host smart-33aac55e-485a-469d-a022-d1425c243ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986205529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.986205529
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.20421012
Short name T12
Test name
Test status
Simulation time 7095872038 ps
CPU time 25.9 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:18:06 PM PST 24
Peak memory 204660 kb
Host smart-cf85a809-b343-477a-9e6d-c3c7c9c50552
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=20421012 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_
access.20421012
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3866497707
Short name T221
Test name
Test status
Simulation time 7814864830 ps
CPU time 5.93 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:17:55 PM PST 24
Peak memory 204576 kb
Host smart-815c814c-0494-4578-a7d5-eb5972a41122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866497707 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3866497707
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.2654099961
Short name T165
Test name
Test status
Simulation time 19406567 ps
CPU time 0.65 seconds
Started Feb 07 02:17:49 PM PST 24
Finished Feb 07 02:17:50 PM PST 24
Peak memory 204140 kb
Host smart-e077e828-a606-498f-af73-069c2f746cb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654099961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.2654099961
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1549453176
Short name T3
Test name
Test status
Simulation time 2669407765 ps
CPU time 5.76 seconds
Started Feb 07 02:17:54 PM PST 24
Finished Feb 07 02:18:01 PM PST 24
Peak memory 204616 kb
Host smart-4d1a71c0-74ea-413b-a490-3b27fb878fe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549453176 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1549453176
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.280041336
Short name T222
Test name
Test status
Simulation time 3095930528 ps
CPU time 12.28 seconds
Started Feb 07 02:17:40 PM PST 24
Finished Feb 07 02:17:54 PM PST 24
Peak memory 204640 kb
Host smart-706ab25b-204c-4f54-a4ec-7ca0545f7021
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=280041336 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_tl
_access.280041336
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.1715149925
Short name T193
Test name
Test status
Simulation time 538112974 ps
CPU time 1.59 seconds
Started Feb 07 02:17:39 PM PST 24
Finished Feb 07 02:17:43 PM PST 24
Peak memory 204552 kb
Host smart-2e338019-6e1a-4440-b76f-54acdb0e5d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715149925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.1715149925
Directory /workspace/9.rv_dm_sba_tl_access/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%