Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	220783	1		T4	101		T7	13		T5	3
full_word	521511	1		T4	39		T7	7		T5	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	742004	1		T4	140		T7	20		T5	4
auto[TlIntgErrCmd]	99	1		T41	4		T42	5		T77	6
auto[TlIntgErrData]	104	1		T40	4		T41	2		T42	6
auto[TlIntgErrBoth]	87	1		T40	6		T41	4		T42	9

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	424101	1		T16	6		T27	6		T19	18
auto[1]	318193	1		T4	140		T7	20		T5	4

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	168465	1		T16	1		T27	2		T19	6
auto[TlIntgErrNone]	partial	auto[1]	52048	1		T4	101		T7	13		T5	3
auto[TlIntgErrNone]	full_word	auto[0]	255503	1		T16	5		T27	4		T19	12
auto[TlIntgErrNone]	full_word	auto[1]	265988	1		T4	39		T7	7		T5	1
auto[TlIntgErrCmd]	partial	auto[0]	38	1		T41	2		T42	3		T77	2
auto[TlIntgErrCmd]	partial	auto[1]	53	1		T41	1		T42	2		T77	3
auto[TlIntgErrCmd]	full_word	auto[0]	2	1		T77	1		T133	1		-	-
auto[TlIntgErrCmd]	full_word	auto[1]	6	1		T41	1		T78	1		T128	1
auto[TlIntgErrData]	partial	auto[0]	54	1		T40	2		T41	2		T42	4
auto[TlIntgErrData]	partial	auto[1]	45	1		T40	1		T42	2		T77	2
auto[TlIntgErrData]	full_word	auto[0]	3	1		T40	1		T77	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	2	1		T128	1		T135	1		-	-
auto[TlIntgErrBoth]	partial	auto[0]	34	1		T40	1		T41	1		T42	4
auto[TlIntgErrBoth]	partial	auto[1]	46	1		T40	5		T41	3		T42	5
auto[TlIntgErrBoth]	full_word	auto[0]	2	1		T136	1		T135	1		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	5	1		T78	1		T128	1		T129	1