Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	176232	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	519749	1		T4	39		T7	7		T5	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	421887	1		T16	6		T27	6		T19	18
values[0x0]	134318	1		T4	70		T7	9		T5	2
values[0x1]	139776	1		T4	70		T7	11		T5	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	135207	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	560774	1		T4	50		T7	9		T5	2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2594	1		T35	1		T46	263		T121	112
valid_sources[0x01]	2412	1		T35	1		T46	291		T121	106
valid_sources[0x02]	2185	1		T21	1		T137	1		T46	273
valid_sources[0x03]	2744	1		T21	5		T35	1		T46	290
valid_sources[0x04]	2781	1		T46	293		T121	93		T47	1
valid_sources[0x05]	2509	1		T21	1		T46	322		T121	98
valid_sources[0x06]	3333	1		T8	1		T21	1		T137	1
valid_sources[0x07]	2645	1		T46	282		T121	120		T47	8
valid_sources[0x08]	2498	1		T35	1		T46	286		T121	121
valid_sources[0x09]	2440	1		T21	1		T137	1		T46	226
valid_sources[0x0a]	2879	1		T84	1		T46	268		T121	99
valid_sources[0x0b]	2287	1		T46	262		T121	98		T47	2
valid_sources[0x0c]	2514	1		T86	1		T46	251		T121	90
valid_sources[0x0d]	2331	1		T21	4		T46	273		T121	97
valid_sources[0x0e]	2728	1		T4	22		T21	2		T46	295
valid_sources[0x0f]	2703	1		T46	312		T121	108		T122	484
valid_sources[0x10]	3640	1		T7	1		T21	2		T84	2
valid_sources[0x11]	2914	1		T138	1		T137	1		T46	264
valid_sources[0x12]	2682	1		T85	17		T46	240		T121	123
valid_sources[0x13]	2667	1		T21	1		T138	1		T84	2
valid_sources[0x14]	2579	1		T35	1		T46	267		T121	123
valid_sources[0x15]	2508	1		T137	1		T46	292		T121	115
valid_sources[0x16]	2649	1		T46	286		T121	114		T47	3
valid_sources[0x17]	2665	1		T7	1		T16	4		T21	3
valid_sources[0x18]	2772	1		T46	234		T121	126		T48	1
valid_sources[0x19]	2666	1		T8	2		T46	266		T121	106
valid_sources[0x1a]	2496	1		T35	1		T46	256		T121	99
valid_sources[0x1b]	2717	1		T8	2		T21	2		T46	257
valid_sources[0x1c]	3142	1		T8	1		T84	1		T46	275
valid_sources[0x1d]	2759	1		T21	1		T46	292		T121	99
valid_sources[0x1e]	2433	1		T8	2		T46	267		T121	109
valid_sources[0x1f]	2569	1		T46	273		T121	97		T47	1
valid_sources[0x20]	2587	1		T21	3		T139	1		T46	266
valid_sources[0x21]	2518	1		T84	2		T35	1		T46	286
valid_sources[0x22]	2540	1		T21	1		T137	2		T46	285
valid_sources[0x23]	2750	1		T21	2		T85	10		T46	287
valid_sources[0x24]	2624	1		T21	1		T84	2		T137	3
valid_sources[0x25]	2716	1		T21	1		T46	275		T121	122
valid_sources[0x26]	2714	1		T46	281		T121	105		T48	2
valid_sources[0x27]	2613	1		T46	247		T121	111		T48	2
valid_sources[0x28]	3150	1		T21	3		T84	2		T46	266
valid_sources[0x29]	2893	1		T46	261		T121	120		T47	6
valid_sources[0x2a]	2805	1		T84	1		T46	271		T121	115
valid_sources[0x2b]	2539	1		T27	1		T140	1		T46	287
valid_sources[0x2c]	3058	1		T35	2		T137	1		T46	275
valid_sources[0x2d]	2616	1		T46	252		T121	105		T122	192
valid_sources[0x2e]	2807	1		T8	5		T84	1		T46	258
valid_sources[0x2f]	3174	1		T8	1		T137	2		T46	280
valid_sources[0x30]	2519	1		T8	1		T21	2		T46	241
valid_sources[0x31]	2625	1		T35	1		T46	266		T121	116
valid_sources[0x32]	2217	1		T8	2		T84	1		T46	258
valid_sources[0x33]	2403	1		T21	1		T137	1		T46	263
valid_sources[0x34]	2867	1		T21	1		T46	283		T121	118
valid_sources[0x35]	2347	1		T8	1		T21	1		T46	270
valid_sources[0x36]	2909	1		T46	242		T121	100		T47	1
valid_sources[0x37]	2668	1		T84	1		T46	278		T121	88
valid_sources[0x38]	2668	1		T137	1		T46	258		T121	109
valid_sources[0x39]	2535	1		T84	4		T35	2		T140	1
valid_sources[0x3a]	2859	1		T46	249		T121	112		T47	7
valid_sources[0x3b]	2819	1		T46	289		T121	102		T47	1
valid_sources[0x3c]	2821	1		T46	258		T121	119		T48	3
valid_sources[0x3d]	2545	1		T84	1		T46	265		T121	134
valid_sources[0x3e]	2742	1		T46	250		T121	112		T48	3
valid_sources[0x3f]	2516	1		T21	1		T46	300		T121	97
valid_sources[0x40]	3362	1		T7	1		T46	292		T121	110
valid_sources[0x41]	2631	1		T8	1		T46	278		T121	105
valid_sources[0x42]	2499	1		T46	243		T121	144		T48	4
valid_sources[0x43]	2943	1		T84	1		T46	282		T121	119
valid_sources[0x44]	2720	1		T84	1		T46	285		T121	98
valid_sources[0x45]	3430	1		T21	1		T46	260		T121	129
valid_sources[0x46]	2827	1		T27	1		T85	1		T46	297
valid_sources[0x47]	2961	1		T137	2		T46	286		T121	96
valid_sources[0x48]	2824	1		T21	1		T84	1		T46	257
valid_sources[0x49]	3504	1		T35	1		T46	260		T121	113
valid_sources[0x4a]	2990	1		T84	1		T46	274		T121	118
valid_sources[0x4b]	2479	1		T5	3		T19	36		T21	1
valid_sources[0x4c]	2588	1		T35	1		T46	273		T121	110
valid_sources[0x4d]	2665	1		T21	1		T84	1		T46	287
valid_sources[0x4e]	2779	1		T21	2		T46	290		T121	108
valid_sources[0x4f]	3165	1		T46	296		T121	84		T48	2
valid_sources[0x50]	2389	1		T46	262		T121	90		T48	3
valid_sources[0x51]	3732	1		T35	2		T140	1		T46	285
valid_sources[0x52]	2830	1		T21	1		T46	284		T121	102
valid_sources[0x53]	2827	1		T7	2		T46	240		T121	89
valid_sources[0x54]	2406	1		T8	3		T84	1		T35	1
valid_sources[0x55]	3282	1		T46	271		T121	95		T122	196
valid_sources[0x56]	2934	1		T46	263		T121	123		T48	1
valid_sources[0x57]	2659	1		T46	236		T121	125		T47	8
valid_sources[0x58]	2270	1		T35	1		T46	252		T121	130
valid_sources[0x59]	2695	1		T21	2		T46	273		T121	116
valid_sources[0x5a]	2197	1		T84	3		T46	239		T121	106
valid_sources[0x5b]	2468	1		T46	288		T121	100		T48	3
valid_sources[0x5c]	2295	1		T21	3		T46	236		T121	117
valid_sources[0x5d]	2476	1		T7	1		T46	276		T121	110
valid_sources[0x5e]	2684	1		T137	1		T46	301		T121	83
valid_sources[0x5f]	2796	1		T27	1		T21	1		T46	258
valid_sources[0x60]	2690	1		T46	256		T121	99		T48	3
valid_sources[0x61]	3120	1		T46	277		T121	118		T47	4
valid_sources[0x62]	2863	1		T46	248		T121	109		T48	2
valid_sources[0x63]	2615	1		T16	2		T46	252		T121	90
valid_sources[0x64]	2596	1		T8	4		T21	3		T46	269
valid_sources[0x65]	2818	1		T35	1		T46	269		T121	103
valid_sources[0x66]	2551	1		T27	1		T84	1		T46	263
valid_sources[0x67]	2493	1		T8	3		T84	2		T85	1
valid_sources[0x68]	3022	1		T84	1		T46	293		T121	138
valid_sources[0x69]	2561	1		T35	1		T46	234		T121	108
valid_sources[0x6a]	3630	1		T4	5		T46	279		T121	96
valid_sources[0x6b]	2696	1		T7	1		T27	1		T34	1
valid_sources[0x6c]	2791	1		T84	1		T46	283		T121	95
valid_sources[0x6d]	2471	1		T46	276		T121	150		T47	7
valid_sources[0x6e]	2732	1		T46	277		T121	87		T48	5
valid_sources[0x6f]	2667	1		T25	30		T137	1		T46	239
valid_sources[0x70]	2491	1		T21	4		T35	1		T140	1
valid_sources[0x71]	2577	1		T21	2		T46	261		T121	120
valid_sources[0x72]	2456	1		T46	260		T121	113		T47	5
valid_sources[0x73]	2565	1		T21	1		T35	1		T46	264
valid_sources[0x74]	2979	1		T21	2		T46	245		T121	101
valid_sources[0x75]	2895	1		T7	1		T84	1		T46	265
valid_sources[0x76]	3412	1		T12	96		T46	273		T121	111
valid_sources[0x77]	2724	1		T21	1		T35	1		T46	261
valid_sources[0x78]	3170	1		T21	3		T35	1		T46	221
valid_sources[0x79]	4435	1		T46	268		T121	111		T48	1
valid_sources[0x7a]	2970	1		T7	1		T84	1		T35	1
valid_sources[0x7b]	3183	1		T27	1		T46	308		T121	117
valid_sources[0x7c]	2495	1		T21	3		T46	277		T121	111
valid_sources[0x7d]	2672	1		T46	286		T121	117		T48	3
valid_sources[0x7e]	2982	1		T6	10		T35	1		T46	254
valid_sources[0x7f]	2252	1		T46	259		T121	99		T47	6
valid_sources[0x80]	2583	1		T21	1		T46	264		T121	101

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255281

1

T16

5

T27

4

T19

12

values[0x0]

all_enables

biggest_size

132469

1

T4

22

T7

5

T6

3

values[0x1]

all_enables

biggest_size

131999

1

T4

17

T7

2

T5

1

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1660	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	17334	1		T2	2		T33	2		T36	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5141	1		T46	128		T47	1		T48	1
values[0x0]	6862	1		T2	1		T33	6		T36	2
values[0x1]	6991	1		T2	3		T33	4		T36	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1306	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	17688	1		T2	3		T33	3		T36	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	39	1		T92	2		T74	2		T141	2
valid_sources[0x01]	48	1		T142	1		T143	6		T45	6
valid_sources[0x02]	137	1		T74	2		T96	3		T141	1
valid_sources[0x03]	60	1		T54	1		T144	4		T87	1
valid_sources[0x04]	53	1		T74	2		T81	3		T145	1
valid_sources[0x05]	73	1		T2	1		T146	10		T43	5
valid_sources[0x06]	50	1		T36	1		T44	1		T74	3
valid_sources[0x07]	62	1		T147	1		T121	1		T43	3
valid_sources[0x08]	29	1		T53	3		T61	1		T81	2
valid_sources[0x09]	68	1		T148	1		T42	8		T74	2
valid_sources[0x0a]	71	1		T33	1		T54	1		T149	1
valid_sources[0x0b]	293	1		T90	19		T46	53		T44	1
valid_sources[0x0c]	43	1		T43	6		T74	3		T115	3
valid_sources[0x0d]	61	1		T148	1		T43	1		T74	1
valid_sources[0x0e]	56	1		T56	2		T149	1		T74	3
valid_sources[0x0f]	54	1		T144	2		T74	1		T63	11
valid_sources[0x10]	39	1		T149	1		T74	3		T81	1
valid_sources[0x11]	47	1		T43	3		T74	1		T81	1
valid_sources[0x12]	114	1		T93	1		T74	1		T141	1
valid_sources[0x13]	66	1		T56	1		T150	1		T47	2
valid_sources[0x14]	52	1		T43	2		T44	1		T74	2
valid_sources[0x15]	47	1		T147	2		T142	1		T143	4
valid_sources[0x16]	124	1		T93	3		T43	3		T40	1
valid_sources[0x17]	38	1		T150	2		T74	1		T81	1
valid_sources[0x18]	40	1		T74	1		T81	2		T96	1
valid_sources[0x19]	48	1		T41	1		T74	1		T81	4
valid_sources[0x1a]	94	1		T43	1		T44	2		T81	3
valid_sources[0x1b]	72	1		T151	2		T43	1		T74	4
valid_sources[0x1c]	47	1		T152	1		T150	1		T43	2
valid_sources[0x1d]	93	1		T43	1		T45	7		T74	4
valid_sources[0x1e]	55	1		T44	1		T74	2		T81	2
valid_sources[0x1f]	67	1		T74	3		T82	11		T96	1
valid_sources[0x20]	37	1		T122	1		T81	2		T95	1
valid_sources[0x21]	41	1		T74	2		T81	1		T96	1
valid_sources[0x22]	62	1		T44	1		T74	5		T81	1
valid_sources[0x23]	31	1		T148	1		T43	1		T122	1
valid_sources[0x24]	66	1		T44	1		T45	16		T74	2
valid_sources[0x25]	199	1		T56	1		T153	1		T154	10
valid_sources[0x26]	109	1		T152	1		T74	1		T81	9
valid_sources[0x27]	39	1		T74	1		T96	1		T63	2
valid_sources[0x28]	63	1		T153	1		T43	1		T44	1
valid_sources[0x29]	259	1		T43	1		T45	1		T74	2
valid_sources[0x2a]	98	1		T155	5		T43	1		T74	1
valid_sources[0x2b]	55	1		T43	1		T74	4		T81	2
valid_sources[0x2c]	64	1		T149	1		T43	3		T74	5
valid_sources[0x2d]	94	1		T54	1		T156	1		T102	1
valid_sources[0x2e]	90	1		T74	2		T81	4		T95	1
valid_sources[0x2f]	50	1		T52	1		T45	6		T74	1
valid_sources[0x30]	78	1		T74	3		T81	10		T96	2
valid_sources[0x31]	42	1		T43	1		T41	1		T87	1
valid_sources[0x32]	47	1		T153	1		T48	1		T43	4
valid_sources[0x33]	49	1		T74	1		T96	6		T141	3
valid_sources[0x34]	48	1		T153	1		T42	1		T74	3
valid_sources[0x35]	34	1		T150	1		T156	1		T157	1
valid_sources[0x36]	78	1		T44	1		T74	1		T141	1
valid_sources[0x37]	39	1		T74	1		T95	1		T141	1
valid_sources[0x38]	63	1		T74	4		T81	1		T96	1
valid_sources[0x39]	30	1		T33	1		T74	3		T81	2
valid_sources[0x3a]	55	1		T158	2		T142	2		T40	1
valid_sources[0x3b]	46	1		T159	12		T44	1		T74	2
valid_sources[0x3c]	87	1		T42	17		T74	1		T96	1
valid_sources[0x3d]	66	1		T160	4		T156	2		T142	1
valid_sources[0x3e]	112	1		T43	5		T74	2		T81	1
valid_sources[0x3f]	397	1		T43	1		T41	1		T74	3
valid_sources[0x40]	75	1		T45	5		T81	1		T141	2
valid_sources[0x41]	68	1		T74	6		T81	1		T96	1
valid_sources[0x42]	45	1		T157	5		T74	1		T63	3
valid_sources[0x43]	46	1		T96	4		T141	4		T145	1
valid_sources[0x44]	61	1		T44	1		T74	1		T81	1
valid_sources[0x45]	50	1		T44	1		T74	1		T77	5
valid_sources[0x46]	50	1		T81	5		T96	1		T161	1
valid_sources[0x47]	35	1		T74	3		T81	3		T141	1
valid_sources[0x48]	44	1		T162	8		T74	2		T96	1
valid_sources[0x49]	100	1		T60	6		T81	2		T96	3
valid_sources[0x4a]	91	1		T43	2		T74	1		T81	1
valid_sources[0x4b]	142	1		T43	4		T40	1		T74	5
valid_sources[0x4c]	49	1		T54	2		T43	1		T41	3
valid_sources[0x4d]	62	1		T153	1		T43	19		T74	6
valid_sources[0x4e]	40	1		T95	1		T96	3		T141	1
valid_sources[0x4f]	53	1		T33	1		T163	8		T43	2
valid_sources[0x50]	38	1		T141	1		T145	3		T119	1
valid_sources[0x51]	50	1		T144	2		T147	1		T74	1
valid_sources[0x52]	125	1		T97	91		T141	1		T145	11
valid_sources[0x53]	81	1		T164	10		T74	1		T81	7
valid_sources[0x54]	37	1		T55	1		T165	1		T43	1
valid_sources[0x55]	172	1		T153	1		T74	2		T80	112
valid_sources[0x56]	54	1		T165	1		T74	3		T81	12
valid_sources[0x57]	86	1		T156	1		T43	4		T96	3
valid_sources[0x58]	57	1		T43	1		T74	1		T80	2
valid_sources[0x59]	57	1		T147	1		T87	1		T74	4
valid_sources[0x5a]	69	1		T88	11		T81	2		T96	10
valid_sources[0x5b]	54	1		T74	3		T81	3		T82	5
valid_sources[0x5c]	39	1		T45	3		T42	1		T74	3
valid_sources[0x5d]	60	1		T147	1		T74	1		T96	2
valid_sources[0x5e]	76	1		T153	1		T63	17		T166	17
valid_sources[0x5f]	169	1		T153	1		T74	3		T81	5
valid_sources[0x60]	103	1		T44	1		T74	1		T95	2
valid_sources[0x61]	35	1		T74	1		T81	7		T141	3
valid_sources[0x62]	153	1		T43	8		T74	4		T81	2
valid_sources[0x63]	95	1		T165	1		T144	4		T42	3
valid_sources[0x64]	360	1		T44	1		T74	1		T95	2
valid_sources[0x65]	49	1		T87	1		T74	6		T81	1
valid_sources[0x66]	52	1		T87	1		T74	3		T141	2
valid_sources[0x67]	58	1		T55	3		T74	4		T104	2
valid_sources[0x68]	134	1		T43	4		T87	1		T74	1
valid_sources[0x69]	76	1		T33	1		T74	3		T81	2
valid_sources[0x6a]	68	1		T165	1		T45	2		T74	3
valid_sources[0x6b]	42	1		T56	1		T156	2		T74	2
valid_sources[0x6c]	62	1		T43	2		T74	4		T77	4
valid_sources[0x6d]	58	1		T167	1		T153	1		T40	2
valid_sources[0x6e]	57	1		T44	1		T74	2		T77	2
valid_sources[0x6f]	124	1		T46	48		T45	9		T87	1
valid_sources[0x70]	61	1		T142	1		T43	5		T44	3
valid_sources[0x71]	60	1		T44	1		T45	10		T87	1
valid_sources[0x72]	47	1		T147	1		T142	1		T40	1
valid_sources[0x73]	70	1		T43	3		T44	2		T81	1
valid_sources[0x74]	60	1		T149	1		T74	5		T77	3
valid_sources[0x75]	61	1		T56	1		T91	3		T156	2
valid_sources[0x76]	64	1		T43	1		T40	4		T87	2
valid_sources[0x77]	45	1		T74	2		T81	2		T116	1
valid_sources[0x78]	104	1		T59	1		T41	1		T42	3
valid_sources[0x79]	53	1		T44	2		T45	4		T74	4
valid_sources[0x7a]	43	1		T61	1		T142	1		T74	3
valid_sources[0x7b]	39	1		T43	1		T74	3		T115	1
valid_sources[0x7c]	95	1		T44	1		T41	1		T74	3
valid_sources[0x7d]	81	1		T56	2		T74	2		T81	1
valid_sources[0x7e]	48	1		T52	1		T74	4		T63	3
valid_sources[0x7f]	143	1		T74	3		T81	1		T95	1
valid_sources[0x80]	80	1		T43	1		T74	8		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4540

1

T46

66

T43

57

T40

3

values[0x0]

all_enables

biggest_size

6408

1

T2

1

T33

2

T36

1

values[0x1]

all_enables

biggest_size

6386

1

T2

1

T31

1

T53

1