Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.47 92.73 78.99 89.36 75.64 82.48 97.75 95.34


Total test records in report: 369
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T111 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1559438138 Feb 25 12:33:04 PM PST 24 Feb 25 12:33:06 PM PST 24 197842371 ps
T266 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.447831891 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:36 PM PST 24 75128228 ps
T118 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2370912046 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:39 PM PST 24 582922519 ps
T267 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.725894716 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:59 PM PST 24 6399254005 ps
T268 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1312746952 Feb 25 12:32:19 PM PST 24 Feb 25 12:32:21 PM PST 24 99839337 ps
T269 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2490141547 Feb 25 12:32:49 PM PST 24 Feb 25 12:32:50 PM PST 24 128692014 ps
T270 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3273797360 Feb 25 12:32:49 PM PST 24 Feb 25 12:32:51 PM PST 24 340237599 ps
T271 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1984578556 Feb 25 12:32:48 PM PST 24 Feb 25 12:32:49 PM PST 24 19770212 ps
T272 /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.209727286 Feb 25 12:32:25 PM PST 24 Feb 25 12:32:27 PM PST 24 342447305 ps
T273 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1129850439 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:48 PM PST 24 3379680226 ps
T274 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.520525334 Feb 25 12:33:38 PM PST 24 Feb 25 12:33:41 PM PST 24 199644050 ps
T275 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1200294291 Feb 25 12:33:59 PM PST 24 Feb 25 12:34:24 PM PST 24 44938539578 ps
T276 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.737426405 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:36 PM PST 24 101125008 ps
T277 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2744926536 Feb 25 12:32:16 PM PST 24 Feb 25 12:32:19 PM PST 24 747303705 ps
T278 /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2930171733 Feb 25 12:32:46 PM PST 24 Feb 25 12:32:58 PM PST 24 14734103139 ps
T129 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3729778734 Feb 25 12:32:59 PM PST 24 Feb 25 12:33:15 PM PST 24 890512366 ps
T279 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2994634100 Feb 25 12:32:48 PM PST 24 Feb 25 12:32:54 PM PST 24 414791475 ps
T280 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3409998344 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:38 PM PST 24 135268052 ps
T112 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.468458759 Feb 25 12:32:25 PM PST 24 Feb 25 12:33:45 PM PST 24 5223506305 ps
T281 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4110340860 Feb 25 12:34:28 PM PST 24 Feb 25 12:34:32 PM PST 24 57963192 ps
T282 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1916721328 Feb 25 12:33:43 PM PST 24 Feb 25 12:33:44 PM PST 24 396393868 ps
T283 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1427478904 Feb 25 12:33:00 PM PST 24 Feb 25 12:33:01 PM PST 24 80286940 ps
T284 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2875465401 Feb 25 12:32:41 PM PST 24 Feb 25 12:32:48 PM PST 24 4384182412 ps
T285 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2240422027 Feb 25 12:32:29 PM PST 24 Feb 25 12:32:30 PM PST 24 88876708 ps
T286 /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2483387166 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:38 PM PST 24 166341830 ps
T287 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1742175344 Feb 25 12:32:25 PM PST 24 Feb 25 12:32:27 PM PST 24 633339875 ps
T126 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3266525108 Feb 25 12:32:36 PM PST 24 Feb 25 12:32:45 PM PST 24 823766313 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4081861310 Feb 25 12:32:21 PM PST 24 Feb 25 12:32:22 PM PST 24 239730611 ps
T289 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2108266216 Feb 25 12:32:51 PM PST 24 Feb 25 12:32:54 PM PST 24 1313579787 ps
T290 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.521609774 Feb 25 12:32:16 PM PST 24 Feb 25 12:33:24 PM PST 24 21698365549 ps
T291 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1346617089 Feb 25 12:32:33 PM PST 24 Feb 25 12:32:34 PM PST 24 92237136 ps
T292 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2633655856 Feb 25 12:32:33 PM PST 24 Feb 25 12:33:08 PM PST 24 10091025681 ps
T293 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2387948969 Feb 25 12:32:50 PM PST 24 Feb 25 12:32:53 PM PST 24 381548749 ps
T294 /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.550285312 Feb 25 12:32:50 PM PST 24 Feb 25 12:33:01 PM PST 24 7069711805 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2927097988 Feb 25 12:32:18 PM PST 24 Feb 25 12:32:22 PM PST 24 225065859 ps
T296 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.956670355 Feb 25 12:32:45 PM PST 24 Feb 25 12:32:47 PM PST 24 373887142 ps
T297 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2719676407 Feb 25 12:32:36 PM PST 24 Feb 25 12:32:40 PM PST 24 797236652 ps
T113 /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3439845346 Feb 25 12:32:27 PM PST 24 Feb 25 12:32:30 PM PST 24 50580603 ps
T298 /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3250190685 Feb 25 12:32:29 PM PST 24 Feb 25 12:32:36 PM PST 24 1829587972 ps
T299 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.529647554 Feb 25 12:32:31 PM PST 24 Feb 25 12:32:32 PM PST 24 321921306 ps
T300 /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2572579906 Feb 25 12:32:20 PM PST 24 Feb 25 12:32:30 PM PST 24 1627863297 ps
T301 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4223304446 Feb 25 12:32:41 PM PST 24 Feb 25 12:33:18 PM PST 24 10579918797 ps
T302 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.11076889 Feb 25 12:32:21 PM PST 24 Feb 25 12:32:23 PM PST 24 198958006 ps
T303 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.773340383 Feb 25 12:32:41 PM PST 24 Feb 25 12:32:45 PM PST 24 1518591942 ps
T304 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3148797686 Feb 25 12:32:37 PM PST 24 Feb 25 12:33:57 PM PST 24 27320805864 ps
T305 /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2676891282 Feb 25 12:32:15 PM PST 24 Feb 25 12:32:17 PM PST 24 88589843 ps
T306 /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1651349200 Feb 25 12:32:32 PM PST 24 Feb 25 12:32:38 PM PST 24 27112673 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3949004695 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:41 PM PST 24 1043288951 ps
T308 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2540264334 Feb 25 12:32:32 PM PST 24 Feb 25 12:33:48 PM PST 24 28937714402 ps
T309 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4015512354 Feb 25 12:32:30 PM PST 24 Feb 25 12:32:31 PM PST 24 50306974 ps
T310 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.57279202 Feb 25 12:32:31 PM PST 24 Feb 25 12:32:36 PM PST 24 731052950 ps
T311 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2136147099 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:55 PM PST 24 337699047 ps
T312 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3577050017 Feb 25 12:32:52 PM PST 24 Feb 25 12:32:55 PM PST 24 57976203 ps
T119 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.613076652 Feb 25 12:32:46 PM PST 24 Feb 25 12:32:53 PM PST 24 513095333 ps
T313 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1317553254 Feb 25 12:32:34 PM PST 24 Feb 25 12:33:48 PM PST 24 44737117890 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.93830250 Feb 25 12:32:30 PM PST 24 Feb 25 12:32:31 PM PST 24 99941905 ps
T315 /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4250655768 Feb 25 12:32:24 PM PST 24 Feb 25 12:32:59 PM PST 24 8513878226 ps
T316 /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2657477898 Feb 25 12:32:15 PM PST 24 Feb 25 12:32:33 PM PST 24 13937947712 ps
T317 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2686355297 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:37 PM PST 24 77387367 ps
T98 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.546574708 Feb 25 12:32:13 PM PST 24 Feb 25 12:32:14 PM PST 24 392977385 ps
T318 /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.711773401 Feb 25 12:32:50 PM PST 24 Feb 25 12:33:07 PM PST 24 8451242073 ps
T319 /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.391029015 Feb 25 12:32:36 PM PST 24 Feb 25 12:33:04 PM PST 24 28087271384 ps
T104 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.577740595 Feb 25 12:32:19 PM PST 24 Feb 25 12:32:27 PM PST 24 414734637 ps
T320 /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2482299068 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:41 PM PST 24 300806254 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2830501891 Feb 25 12:32:27 PM PST 24 Feb 25 12:32:28 PM PST 24 28092742 ps
T322 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.359615117 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:48 PM PST 24 47559912 ps
T130 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1683372164 Feb 25 12:32:44 PM PST 24 Feb 25 12:32:53 PM PST 24 1036373018 ps
T323 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.474726371 Feb 25 12:32:19 PM PST 24 Feb 25 12:32:37 PM PST 24 14340778796 ps
T324 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4101480991 Feb 25 12:32:53 PM PST 24 Feb 25 12:32:54 PM PST 24 42501539 ps
T325 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3250176916 Feb 25 12:32:42 PM PST 24 Feb 25 12:32:43 PM PST 24 142721176 ps
T326 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2755137497 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:35 PM PST 24 121142896 ps
T327 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1693912425 Feb 25 12:32:36 PM PST 24 Feb 25 12:33:29 PM PST 24 13534817825 ps
T328 /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.430183332 Feb 25 12:32:56 PM PST 24 Feb 25 12:33:25 PM PST 24 26637702211 ps
T329 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.788184629 Feb 25 12:32:31 PM PST 24 Feb 25 12:32:36 PM PST 24 213993320 ps
T330 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3733759856 Feb 25 12:32:44 PM PST 24 Feb 25 12:32:48 PM PST 24 2045706509 ps
T331 /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1330374855 Feb 25 12:32:49 PM PST 24 Feb 25 12:33:02 PM PST 24 2742584298 ps
T332 /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.505662003 Feb 25 12:32:50 PM PST 24 Feb 25 12:33:17 PM PST 24 20708512123 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1138589962 Feb 25 12:32:33 PM PST 24 Feb 25 12:32:33 PM PST 24 43243647 ps
T334 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2982663310 Feb 25 12:32:39 PM PST 24 Feb 25 12:32:45 PM PST 24 147214087 ps
T127 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4275786744 Feb 25 12:32:50 PM PST 24 Feb 25 12:33:13 PM PST 24 9244944969 ps
T128 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1774212465 Feb 25 12:32:31 PM PST 24 Feb 25 12:32:51 PM PST 24 2409078807 ps
T131 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1580825855 Feb 25 12:32:41 PM PST 24 Feb 25 12:32:50 PM PST 24 4259057832 ps
T335 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3396554925 Feb 25 12:32:40 PM PST 24 Feb 25 12:32:49 PM PST 24 1950944252 ps
T336 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1448875149 Feb 25 12:32:36 PM PST 24 Feb 25 12:32:41 PM PST 24 222377347 ps
T337 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3914468110 Feb 25 12:32:54 PM PST 24 Feb 25 12:32:56 PM PST 24 698748397 ps
T338 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1378534557 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:41 PM PST 24 283188377 ps
T339 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3407950634 Feb 25 12:32:38 PM PST 24 Feb 25 12:32:42 PM PST 24 470221269 ps
T105 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1679472864 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:39 PM PST 24 3667714064 ps
T340 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1004392784 Feb 25 12:32:50 PM PST 24 Feb 25 12:32:54 PM PST 24 185612492 ps
T341 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1065340210 Feb 25 12:32:12 PM PST 24 Feb 25 12:32:13 PM PST 24 132669659 ps
T342 /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.638351247 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:37 PM PST 24 28850112 ps
T343 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3567463073 Feb 25 12:32:35 PM PST 24 Feb 25 12:32:36 PM PST 24 52986624 ps
T344 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.54845224 Feb 25 12:32:36 PM PST 24 Feb 25 12:32:37 PM PST 24 45279942 ps
T345 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2233557 Feb 25 12:32:25 PM PST 24 Feb 25 12:32:27 PM PST 24 1192889045 ps
T346 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2955846006 Feb 25 12:32:31 PM PST 24 Feb 25 12:32:47 PM PST 24 739875711 ps
T347 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.449996413 Feb 25 12:32:43 PM PST 24 Feb 25 12:32:50 PM PST 24 505113987 ps
T348 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2551809221 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:37 PM PST 24 925862134 ps
T349 /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3330147241 Feb 25 12:32:58 PM PST 24 Feb 25 12:33:13 PM PST 24 11576261576 ps
T350 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.710858668 Feb 25 12:32:33 PM PST 24 Feb 25 12:32:37 PM PST 24 77884877 ps
T351 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3036513482 Feb 25 12:32:18 PM PST 24 Feb 25 12:32:18 PM PST 24 93111674 ps
T352 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1071186045 Feb 25 12:32:44 PM PST 24 Feb 25 12:33:06 PM PST 24 14732610484 ps
T353 /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2584350600 Feb 25 12:32:22 PM PST 24 Feb 25 12:32:27 PM PST 24 172808068 ps
T354 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.315065895 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:48 PM PST 24 3354625423 ps
T99 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3559357101 Feb 25 12:32:34 PM PST 24 Feb 25 12:32:36 PM PST 24 1323312129 ps
T355 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1924372697 Feb 25 12:32:45 PM PST 24 Feb 25 12:34:02 PM PST 24 26848100673 ps
T356 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3507432704 Feb 25 12:32:33 PM PST 24 Feb 25 12:32:34 PM PST 24 58975131 ps
T357 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.843766601 Feb 25 12:32:38 PM PST 24 Feb 25 12:32:40 PM PST 24 482691125 ps
T358 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2832770308 Feb 25 12:32:43 PM PST 24 Feb 25 12:32:46 PM PST 24 163804915 ps
T359 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1847869415 Feb 25 12:34:33 PM PST 24 Feb 25 12:34:34 PM PST 24 85053575 ps
T360 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4219821354 Feb 25 12:32:45 PM PST 24 Feb 25 12:32:46 PM PST 24 158167710 ps
T361 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.706008993 Feb 25 12:32:38 PM PST 24 Feb 25 12:32:43 PM PST 24 1976992830 ps
T362 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3359797008 Feb 25 12:32:37 PM PST 24 Feb 25 12:32:40 PM PST 24 565427592 ps
T363 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2740676770 Feb 25 12:32:24 PM PST 24 Feb 25 12:32:27 PM PST 24 38820818 ps
T364 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4094779505 Feb 25 12:32:23 PM PST 24 Feb 25 12:32:25 PM PST 24 56267738 ps
T365 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2637115263 Feb 25 12:32:38 PM PST 24 Feb 25 12:33:00 PM PST 24 19539588090 ps
T366 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1689227950 Feb 25 12:33:01 PM PST 24 Feb 25 12:33:05 PM PST 24 1679683184 ps
T367 /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.741558876 Feb 25 12:32:26 PM PST 24 Feb 25 12:32:28 PM PST 24 49443767 ps
T368 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.387935531 Feb 25 12:32:41 PM PST 24 Feb 25 12:32:43 PM PST 24 1974560379 ps
T369 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.261935965 Feb 25 12:32:27 PM PST 24 Feb 25 12:32:29 PM PST 24 73776957 ps

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.375799116
Short name T36
Test name
Test status
Simulation time 1180726219 ps
CPU time 4.13 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:33:58 PM PST 24
Peak memory 203684 kb
Host smart-135959cc-5237-42b1-9a9c-49aff2fd3955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375799116 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.375799116
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.3676705676
Short name T5
Test name
Test status
Simulation time 442993153 ps
CPU time 0.88 seconds
Started Feb 25 12:33:40 PM PST 24
Finished Feb 25 12:33:42 PM PST 24
Peak memory 203364 kb
Host smart-bea8c4c6-e27f-40df-b839-3904072b2b88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676705676 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.3676705676
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.1570381343
Short name T44
Test name
Test status
Simulation time 5771029716 ps
CPU time 19.14 seconds
Started Feb 25 12:32:32 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 212484 kb
Host smart-27b3593d-9143-4faa-b3fc-1892bc996e73
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570381343 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.1570381343
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.2210080898
Short name T41
Test name
Test status
Simulation time 18177102598 ps
CPU time 20.81 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:33:02 PM PST 24
Peak memory 217436 kb
Host smart-75bbdb99-9ea0-45f5-9b23-9042dbc669b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210080898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.2210080898
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.1714321279
Short name T50
Test name
Test status
Simulation time 49931730 ps
CPU time 0.64 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203500 kb
Host smart-fe816748-c340-4be6-86ac-e30a9fb37c3c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714321279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.1714321279
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_stress_all.4028089010
Short name T22
Test name
Test status
Simulation time 3805230439 ps
CPU time 3.82 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203580 kb
Host smart-4fb40e6a-2aca-4a59-9b61-fabf6d6fbbb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028089010 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_stress_all.4028089010
Directory /workspace/6.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3347421369
Short name T65
Test name
Test status
Simulation time 9434403468 ps
CPU time 12.36 seconds
Started Feb 25 12:33:53 PM PST 24
Finished Feb 25 12:34:06 PM PST 24
Peak memory 203776 kb
Host smart-a2be757f-118a-4616-8ae8-bb84230e2781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347421369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3347421369
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/38.rv_dm_stress_all.3349404975
Short name T12
Test name
Test status
Simulation time 4325559037 ps
CPU time 14.12 seconds
Started Feb 25 12:34:07 PM PST 24
Finished Feb 25 12:34:22 PM PST 24
Peak memory 203588 kb
Host smart-f0cd92f1-c986-4925-a87a-7e68dd5faf6c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349404975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_stress_all.3349404975
Directory /workspace/38.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.2935228126
Short name T160
Test name
Test status
Simulation time 75690367 ps
CPU time 4.81 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 204272 kb
Host smart-3f5a4b38-cae9-4762-8e46-bca68e68d8d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935228126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.2935228126
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.445718215
Short name T191
Test name
Test status
Simulation time 17454693670 ps
CPU time 20.9 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 203692 kb
Host smart-ecd59e6a-3ccf-4267-b1dc-fc7f12737ed0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445718215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.445718215
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.2862013725
Short name T56
Test name
Test status
Simulation time 14134195909 ps
CPU time 79.56 seconds
Started Feb 25 12:32:28 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 204316 kb
Host smart-26e249d2-f466-4272-be96-6e73fbbc7ae0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862013725 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 3.rv_dm_csr_aliasing.2862013725
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4275786744
Short name T127
Test name
Test status
Simulation time 9244944969 ps
CPU time 18.63 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:33:13 PM PST 24
Peak memory 216744 kb
Host smart-7f211d77-84c3-48da-9ae9-598582e23033
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275786744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
275786744
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.3903731077
Short name T60
Test name
Test status
Simulation time 4124175121 ps
CPU time 2.99 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:15 PM PST 24
Peak memory 203532 kb
Host smart-190376de-da37-4842-91b4-a2d160dc54f1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903731077 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.3903731077
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.3362389716
Short name T39
Test name
Test status
Simulation time 239396264 ps
CPU time 1.06 seconds
Started Feb 25 12:33:31 PM PST 24
Finished Feb 25 12:33:33 PM PST 24
Peak memory 219416 kb
Host smart-8835a236-9437-47a0-b26d-b67ade7f7f0e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362389716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.3362389716
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4250794641
Short name T6
Test name
Test status
Simulation time 712635085 ps
CPU time 1.42 seconds
Started Feb 25 12:33:41 PM PST 24
Finished Feb 25 12:33:43 PM PST 24
Peak memory 203308 kb
Host smart-237afa29-288c-4f81-aa64-24c8efbe4e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250794641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4250794641
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.236582514
Short name T54
Test name
Test status
Simulation time 18277588 ps
CPU time 0.63 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:33:55 PM PST 24
Peak memory 203496 kb
Host smart-d8cf4a2e-0e1f-4859-ab58-afb13c3ddf07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236582514 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.236582514
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3947392284
Short name T14
Test name
Test status
Simulation time 161377290 ps
CPU time 0.86 seconds
Started Feb 25 12:33:42 PM PST 24
Finished Feb 25 12:33:44 PM PST 24
Peak memory 203352 kb
Host smart-8a5163d4-2737-4f36-96e0-0e928f85ef33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947392284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3947392284
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.1580825855
Short name T131
Test name
Test status
Simulation time 4259057832 ps
CPU time 9.37 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 213316 kb
Host smart-81bcc7b7-9515-4abc-b82d-51fe2e672400
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580825855 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.1
580825855
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.1605987737
Short name T58
Test name
Test status
Simulation time 1863394486 ps
CPU time 7.52 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 204252 kb
Host smart-6f6855bd-4d74-4b87-82b6-0bf3a82ab7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605987737 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.1605987737
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3157067782
Short name T68
Test name
Test status
Simulation time 149512997 ps
CPU time 0.65 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:31 PM PST 24
Peak memory 203952 kb
Host smart-970eaf3a-a209-47af-a65a-d13c42898b66
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157067782 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3157067782
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1979689819
Short name T123
Test name
Test status
Simulation time 3237762610 ps
CPU time 17.7 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:33:02 PM PST 24
Peak memory 216520 kb
Host smart-8b18af68-d56c-4675-8f02-0fae1f577c4d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979689819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1979689819
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.645861633
Short name T37
Test name
Test status
Simulation time 32133525 ps
CPU time 0.7 seconds
Started Feb 25 12:33:49 PM PST 24
Finished Feb 25 12:33:50 PM PST 24
Peak memory 203492 kb
Host smart-c520b636-a7b0-46e0-bffa-f37a50520379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645861633 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.645861633
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.546574708
Short name T98
Test name
Test status
Simulation time 392977385 ps
CPU time 1.03 seconds
Started Feb 25 12:32:13 PM PST 24
Finished Feb 25 12:32:14 PM PST 24
Peak memory 204196 kb
Host smart-4011763a-2530-47d9-9560-22130c053893
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546574708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_hw_reset.546574708
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.3717772845
Short name T28
Test name
Test status
Simulation time 605021952 ps
CPU time 0.81 seconds
Started Feb 25 12:33:32 PM PST 24
Finished Feb 25 12:33:34 PM PST 24
Peak memory 203168 kb
Host smart-fa5a072b-5316-4147-b6a2-659c3c4f1563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717772845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.3717772845
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3417795462
Short name T72
Test name
Test status
Simulation time 5423549242 ps
CPU time 17 seconds
Started Feb 25 12:33:48 PM PST 24
Finished Feb 25 12:34:05 PM PST 24
Peak memory 203736 kb
Host smart-329e5aa3-0574-4f91-bd04-7667eac9c4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417795462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3417795462
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.4250655768
Short name T315
Test name
Test status
Simulation time 8513878226 ps
CPU time 33.99 seconds
Started Feb 25 12:32:24 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 204156 kb
Host smart-23aa0a6a-9e08-4ad1-9e56-3f0cc56b7ba4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250655768 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.4250655768
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2954073411
Short name T243
Test name
Test status
Simulation time 2651361586 ps
CPU time 33.43 seconds
Started Feb 25 12:32:20 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 204224 kb
Host smart-f8ee99c2-b6c5-4f02-8716-c100bfd40bb5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954073411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2954073411
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.209727286
Short name T272
Test name
Test status
Simulation time 342447305 ps
CPU time 1.49 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204232 kb
Host smart-7de4a53b-f055-4ab7-aad9-862119284775
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209727286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.209727286
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1129850439
Short name T273
Test name
Test status
Simulation time 3379680226 ps
CPU time 9.05 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 216236 kb
Host smart-2337602f-b2f5-4ae4-a170-48503c618c95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129850439 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1129850439
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2740676770
Short name T363
Test name
Test status
Simulation time 38820818 ps
CPU time 2.06 seconds
Started Feb 25 12:32:24 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204140 kb
Host smart-a959b8df-0c32-4e11-972d-c96c56de0e69
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740676770 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2740676770
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3701826547
Short name T239
Test name
Test status
Simulation time 19414729739 ps
CPU time 38.34 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:33:10 PM PST 24
Peak memory 204144 kb
Host smart-1b038338-4b74-40fc-b892-fda7d49f0e79
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701826547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3701826547
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_bit_bash.474726371
Short name T323
Test name
Test status
Simulation time 14340778796 ps
CPU time 18.34 seconds
Started Feb 25 12:32:19 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 204164 kb
Host smart-9bfb6136-6494-4d41-80a2-7c12ae777a53
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474726371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_bit_bash.474726371
Directory /workspace/0.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.2744926536
Short name T277
Test name
Test status
Simulation time 747303705 ps
CPU time 2.93 seconds
Started Feb 25 12:32:16 PM PST 24
Finished Feb 25 12:32:19 PM PST 24
Peak memory 204124 kb
Host smart-1bc849ac-ac96-453d-9aea-a72fe7dd9d30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744926536 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.2
744926536
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.359615117
Short name T322
Test name
Test status
Simulation time 47559912 ps
CPU time 0.74 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 203904 kb
Host smart-caa0abd6-f3cd-4447-9e4d-e4a8cc8dec57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359615117 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.359615117
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.387935531
Short name T368
Test name
Test status
Simulation time 1974560379 ps
CPU time 2.82 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 204100 kb
Host smart-bf1bce9a-1872-4eaa-a325-b32ebd9ab988
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387935531 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_bit_bash.387935531
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.1339460321
Short name T229
Test name
Test status
Simulation time 80391753 ps
CPU time 0.76 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:32:33 PM PST 24
Peak memory 203896 kb
Host smart-256c7f24-0553-48ca-abaa-9a5cf3442344
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339460321 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.1
339460321
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.54845224
Short name T344
Test name
Test status
Simulation time 45279942 ps
CPU time 0.62 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 203840 kb
Host smart-fc530799-8f7d-4555-9e65-e1c5bf50a6a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54845224 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_parti
al_access.54845224
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.263532830
Short name T227
Test name
Test status
Simulation time 19799147 ps
CPU time 0.62 seconds
Started Feb 25 12:32:28 PM PST 24
Finished Feb 25 12:32:29 PM PST 24
Peak memory 203892 kb
Host smart-37b3d834-b8e4-4234-91d6-79df865cec06
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263532830 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.263532830
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.2370912046
Short name T118
Test name
Test status
Simulation time 582922519 ps
CPU time 4.49 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 204188 kb
Host smart-92e78298-5422-4c33-9cf6-e9b9813d3b6a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370912046 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.2370912046
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.2927097988
Short name T295
Test name
Test status
Simulation time 225065859 ps
CPU time 4.19 seconds
Started Feb 25 12:32:18 PM PST 24
Finished Feb 25 12:32:22 PM PST 24
Peak memory 212500 kb
Host smart-790b564e-4e9d-49ea-b936-b73bc4c9a749
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927097988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.2927097988
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.3766099278
Short name T42
Test name
Test status
Simulation time 2806429086 ps
CPU time 9.6 seconds
Started Feb 25 12:32:23 PM PST 24
Finished Feb 25 12:32:34 PM PST 24
Peak memory 212484 kb
Host smart-c82e9140-84b1-482f-8096-a782598fb3ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766099278 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.3766099278
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.4174282565
Short name T106
Test name
Test status
Simulation time 1083725082 ps
CPU time 25.94 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 204216 kb
Host smart-41758ad2-6fe9-47b2-b334-ffa5327ac0f3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4174282565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.4174282565
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2633655856
Short name T292
Test name
Test status
Simulation time 10091025681 ps
CPU time 35.55 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:33:08 PM PST 24
Peak memory 204276 kb
Host smart-9f75f07b-2309-45ec-889b-83ba05524910
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633655856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2633655856
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.2832770308
Short name T358
Test name
Test status
Simulation time 163804915 ps
CPU time 2.33 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 204204 kb
Host smart-35aa814b-7acf-4f29-b295-9c6bb3ab67aa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832770308 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.2832770308
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.2686355297
Short name T317
Test name
Test status
Simulation time 77387367 ps
CPU time 3.33 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 215504 kb
Host smart-2db77446-4383-4296-9c60-184b26604e5b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686355297 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.2686355297
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2676891282
Short name T305
Test name
Test status
Simulation time 88589843 ps
CPU time 1.34 seconds
Started Feb 25 12:32:15 PM PST 24
Finished Feb 25 12:32:17 PM PST 24
Peak memory 204180 kb
Host smart-6d0c6fd9-afd3-45fc-b932-97e398d94530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676891282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2676891282
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2332197630
Short name T248
Test name
Test status
Simulation time 6938506377 ps
CPU time 23.56 seconds
Started Feb 25 12:32:29 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 204132 kb
Host smart-ef8c3dee-c46b-40d5-91ae-23f3860893ce
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332197630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2332197630
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.4223304446
Short name T301
Test name
Test status
Simulation time 10579918797 ps
CPU time 36.23 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:33:18 PM PST 24
Peak memory 204140 kb
Host smart-4720b8de-b063-4a9e-9f83-90637e311fee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223304446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.4223304446
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3559357101
Short name T99
Test name
Test status
Simulation time 1323312129 ps
CPU time 2.65 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 204160 kb
Host smart-a2fbefd7-567a-45d7-8524-909f510299fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559357101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3559357101
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2462332355
Short name T233
Test name
Test status
Simulation time 324534722 ps
CPU time 1.05 seconds
Started Feb 25 12:32:14 PM PST 24
Finished Feb 25 12:32:15 PM PST 24
Peak memory 204072 kb
Host smart-c1f27538-f6e3-4b5a-b533-db1c8a5eabf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462332355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
462332355
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.1065340210
Short name T341
Test name
Test status
Simulation time 132669659 ps
CPU time 1.01 seconds
Started Feb 25 12:32:12 PM PST 24
Finished Feb 25 12:32:13 PM PST 24
Peak memory 203920 kb
Host smart-700598ad-ea50-40ea-97bd-a67112dff5ea
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065340210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.1065340210
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3385713203
Short name T69
Test name
Test status
Simulation time 496704831 ps
CPU time 2.02 seconds
Started Feb 25 12:32:17 PM PST 24
Finished Feb 25 12:32:19 PM PST 24
Peak memory 204132 kb
Host smart-6a3b4033-834c-4f6d-9a6a-0feed225d08c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385713203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3385713203
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.4294035756
Short name T247
Test name
Test status
Simulation time 60840128 ps
CPU time 0.79 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 203948 kb
Host smart-790fd1a1-7c5b-466b-b655-f6efd06558ee
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294035756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.4294035756
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.1138589962
Short name T333
Test name
Test status
Simulation time 43243647 ps
CPU time 0.64 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:32:33 PM PST 24
Peak memory 203912 kb
Host smart-f9a5ec20-7aab-4f3e-9a0b-c17e27724f83
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138589962 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.1
138589962
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.3567463073
Short name T343
Test name
Test status
Simulation time 52986624 ps
CPU time 0.66 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 203848 kb
Host smart-95128c31-99c3-42d8-8301-5854c8656cd1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567463073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.3567463073
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4015512354
Short name T309
Test name
Test status
Simulation time 50306974 ps
CPU time 0.62 seconds
Started Feb 25 12:32:30 PM PST 24
Finished Feb 25 12:32:31 PM PST 24
Peak memory 203880 kb
Host smart-fcd08080-22a9-4ec4-a28f-325a178de2e3
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015512354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4015512354
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.1872577089
Short name T117
Test name
Test status
Simulation time 591934939 ps
CPU time 4.46 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:41 PM PST 24
Peak memory 204300 kb
Host smart-3991bd0d-175d-41e5-9a97-68f1005f6277
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872577089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.1872577089
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.2657477898
Short name T316
Test name
Test status
Simulation time 13937947712 ps
CPU time 17.17 seconds
Started Feb 25 12:32:15 PM PST 24
Finished Feb 25 12:32:33 PM PST 24
Peak memory 204364 kb
Host smart-94bc7619-6b25-4add-8d8c-5f1303b34196
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657477898 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.2657477898
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.788184629
Short name T329
Test name
Test status
Simulation time 213993320 ps
CPU time 5.05 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 212548 kb
Host smart-0bfd0709-549e-47fb-8cea-5eba1bfd07c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788184629 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.788184629
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.1774212465
Short name T128
Test name
Test status
Simulation time 2409078807 ps
CPU time 19.43 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 216236 kb
Host smart-06d03f68-79e9-45d7-8256-e1ebf66ac43d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774212465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.1774212465
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.2474763379
Short name T253
Test name
Test status
Simulation time 935857847 ps
CPU time 3.69 seconds
Started Feb 25 12:33:30 PM PST 24
Finished Feb 25 12:33:36 PM PST 24
Peak memory 215584 kb
Host smart-f6b444f3-cd34-4aa6-abc4-e0ff71dd2a72
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474763379 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.2474763379
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2387948969
Short name T293
Test name
Test status
Simulation time 381548749 ps
CPU time 2.2 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 212412 kb
Host smart-f5b07bf4-2da2-45a8-8e00-220b71b9a9e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387948969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2387948969
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.4219821354
Short name T360
Test name
Test status
Simulation time 158167710 ps
CPU time 1.19 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 204092 kb
Host smart-fd45ff4e-49e1-4a0c-a9f8-7e3df5473cff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219821354 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
4219821354
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.2683069429
Short name T258
Test name
Test status
Simulation time 142846889 ps
CPU time 0.68 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 203908 kb
Host smart-7e9ffd15-6bbd-4f2f-8385-9e70b00b513b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683069429 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
2683069429
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.2195095500
Short name T252
Test name
Test status
Simulation time 142686459 ps
CPU time 4.81 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 204324 kb
Host smart-f92447df-0a02-46b2-9e22-1997d7693560
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195095500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.2195095500
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.3266525108
Short name T126
Test name
Test status
Simulation time 823766313 ps
CPU time 8.49 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:45 PM PST 24
Peak memory 212424 kb
Host smart-76205157-bf22-4745-86bf-9bfac6627c2d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266525108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.3
266525108
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3733759856
Short name T330
Test name
Test status
Simulation time 2045706509 ps
CPU time 4.16 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 220676 kb
Host smart-958a036e-c75e-488f-8e4a-131f2b0457c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733759856 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3733759856
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.92473073
Short name T88
Test name
Test status
Simulation time 344046517 ps
CPU time 1.47 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 212320 kb
Host smart-281c68e6-6799-4a05-875b-942b85319251
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92473073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.92473073
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.891947062
Short name T231
Test name
Test status
Simulation time 202446462 ps
CPU time 0.97 seconds
Started Feb 25 12:32:47 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 204132 kb
Host smart-d9773ca1-ffab-47c3-b2aa-ac23108ad4eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891947062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.891947062
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.4220201148
Short name T235
Test name
Test status
Simulation time 41011407 ps
CPU time 0.64 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:42 PM PST 24
Peak memory 203904 kb
Host smart-e30e0697-a6c0-4d06-a9a2-70fdb7cb1209
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220201148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
4220201148
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.279290033
Short name T115
Test name
Test status
Simulation time 520007870 ps
CPU time 4.08 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 204228 kb
Host smart-f20ecabd-efcf-4ffe-a4b9-c4bac6dc6f66
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279290033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.279290033
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.489355206
Short name T79
Test name
Test status
Simulation time 70405044 ps
CPU time 1.98 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 204280 kb
Host smart-205b9e7c-1cb0-4ff4-afb4-c6e8c7223a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489355206 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.489355206
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.550285312
Short name T294
Test name
Test status
Simulation time 7069711805 ps
CPU time 10.37 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:33:01 PM PST 24
Peak memory 213692 kb
Host smart-b8cea4f3-ed75-4cab-8ade-e38060200089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550285312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.550285312
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2535556533
Short name T242
Test name
Test status
Simulation time 3371417143 ps
CPU time 4.75 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:43 PM PST 24
Peak memory 214828 kb
Host smart-bb844898-7ab7-4626-ba2d-c69ac06b7253
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535556533 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2535556533
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3949004695
Short name T307
Test name
Test status
Simulation time 1043288951 ps
CPU time 2.41 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:41 PM PST 24
Peak memory 212428 kb
Host smart-54b4e4c0-c721-4b6b-81ae-a4c7a6116a47
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949004695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3949004695
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.1916721328
Short name T282
Test name
Test status
Simulation time 396393868 ps
CPU time 0.8 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:44 PM PST 24
Peak memory 204024 kb
Host smart-f475b559-cc0c-4b91-a944-3f650515bbaf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916721328 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.
1916721328
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3855838065
Short name T244
Test name
Test status
Simulation time 68183334 ps
CPU time 0.79 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 203916 kb
Host smart-d9e4f28b-03d5-4b24-835d-d774b067d956
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855838065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3855838065
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3331584778
Short name T57
Test name
Test status
Simulation time 848417834 ps
CPU time 4.25 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 204204 kb
Host smart-a43336a8-110a-43f1-8fae-2c121a0644a2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331584778 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3331584778
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.1312746952
Short name T268
Test name
Test status
Simulation time 99839337 ps
CPU time 1.95 seconds
Started Feb 25 12:32:19 PM PST 24
Finished Feb 25 12:32:21 PM PST 24
Peak memory 212492 kb
Host smart-fa2a3db8-dd1f-4389-9a79-18798d2c39c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312746952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.1312746952
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.3625505239
Short name T254
Test name
Test status
Simulation time 141043667 ps
CPU time 2.25 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 212472 kb
Host smart-c8e83dae-dab8-4d31-b2f4-b677a68a8d6e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625505239 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.3625505239
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3527008807
Short name T89
Test name
Test status
Simulation time 398592681 ps
CPU time 1.49 seconds
Started Feb 25 12:33:39 PM PST 24
Finished Feb 25 12:33:41 PM PST 24
Peak memory 204176 kb
Host smart-893faca3-1ef7-4767-b802-0cfe8f0105e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527008807 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3527008807
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.3250176916
Short name T325
Test name
Test status
Simulation time 142721176 ps
CPU time 1.13 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 204064 kb
Host smart-2d0d1c63-d201-46a6-ab7f-ebd2710c28b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250176916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.
3250176916
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.4101480991
Short name T324
Test name
Test status
Simulation time 42501539 ps
CPU time 0.73 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 203928 kb
Host smart-4fe1dcf4-e5a7-4081-92eb-6a13596bc39c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101480991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
4101480991
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2982663310
Short name T334
Test name
Test status
Simulation time 147214087 ps
CPU time 6.25 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:45 PM PST 24
Peak memory 204240 kb
Host smart-c4b7d275-62b7-4241-bed7-272576ab2fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982663310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2982663310
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.2595324131
Short name T255
Test name
Test status
Simulation time 1256036970 ps
CPU time 10.81 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 212568 kb
Host smart-02688f84-656f-4189-8a2e-458424e36df7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595324131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.2
595324131
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1004392784
Short name T340
Test name
Test status
Simulation time 185612492 ps
CPU time 3.72 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 219492 kb
Host smart-9a101169-9ba8-4166-a9e2-8ce907333b3b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004392784 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1004392784
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.3692229909
Short name T110
Test name
Test status
Simulation time 343279932 ps
CPU time 2.45 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 204164 kb
Host smart-2ceff97f-8d5e-445d-bfd5-d1773f5a6da0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692229909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.3692229909
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3273797360
Short name T270
Test name
Test status
Simulation time 340237599 ps
CPU time 1.96 seconds
Started Feb 25 12:32:49 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 204120 kb
Host smart-208daf1c-9b1b-4d55-a1ea-8d1e5501fd80
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273797360 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3273797360
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.3411783550
Short name T230
Test name
Test status
Simulation time 115957797 ps
CPU time 0.72 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 203840 kb
Host smart-6f764117-2f2c-47a6-a59e-7d40c1c9bccb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411783550 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.
3411783550
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2482299068
Short name T320
Test name
Test status
Simulation time 300806254 ps
CPU time 3.53 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:41 PM PST 24
Peak memory 204196 kb
Host smart-96d264dd-5c33-4bc7-9dc9-d078f31871c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2482299068 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2482299068
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2875872757
Short name T75
Test name
Test status
Simulation time 445308911 ps
CPU time 3.84 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 212556 kb
Host smart-069f0561-bb48-49c9-892a-3927ef70c592
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875872757 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2875872757
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.3396554925
Short name T335
Test name
Test status
Simulation time 1950944252 ps
CPU time 9.55 seconds
Started Feb 25 12:32:40 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 212532 kb
Host smart-23ae3b0d-305d-4709-90a5-972830619f7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396554925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.3
396554925
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3839382036
Short name T241
Test name
Test status
Simulation time 685806479 ps
CPU time 4.3 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 214920 kb
Host smart-d24c9263-c74c-4be4-b78e-a130cb8a1af3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839382036 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3839382036
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2093187063
Short name T265
Test name
Test status
Simulation time 109426065 ps
CPU time 1.39 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:44 PM PST 24
Peak memory 204236 kb
Host smart-4ca242aa-4018-4763-b90b-0100df7ea2fd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093187063 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2093187063
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.3914468110
Short name T337
Test name
Test status
Simulation time 698748397 ps
CPU time 1.74 seconds
Started Feb 25 12:32:54 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 204088 kb
Host smart-e615bda4-ae54-4c52-9d90-fb812b5cb619
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914468110 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
3914468110
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.3502548912
Short name T234
Test name
Test status
Simulation time 35354993 ps
CPU time 0.73 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 203928 kb
Host smart-7ced5ac0-3843-4249-9860-0900995ae760
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502548912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
3502548912
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.1732745904
Short name T103
Test name
Test status
Simulation time 311881558 ps
CPU time 3.92 seconds
Started Feb 25 12:32:53 PM PST 24
Finished Feb 25 12:32:57 PM PST 24
Peak memory 204208 kb
Host smart-49c112d4-4005-4e2d-83e1-ca1f8a44c26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732745904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.1732745904
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.3577232235
Short name T261
Test name
Test status
Simulation time 145568431 ps
CPU time 4.52 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 212472 kb
Host smart-e82ac010-e333-42aa-b163-2594de582473
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577232235 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.3577232235
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.2431411486
Short name T71
Test name
Test status
Simulation time 1288585858 ps
CPU time 15.6 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 212548 kb
Host smart-d956fd12-ffb1-4520-be9d-b63616ae65ba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431411486 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.2
431411486
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4032255010
Short name T43
Test name
Test status
Simulation time 123811165 ps
CPU time 2.2 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 220696 kb
Host smart-2633385b-eb70-414f-8e2b-79a3c6829734
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032255010 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4032255010
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.1559438138
Short name T111
Test name
Test status
Simulation time 197842371 ps
CPU time 2.31 seconds
Started Feb 25 12:33:04 PM PST 24
Finished Feb 25 12:33:06 PM PST 24
Peak memory 204268 kb
Host smart-8fa3fe7d-3d00-43d5-912c-48e83bb3002d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559438138 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.1559438138
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.2108266216
Short name T289
Test name
Test status
Simulation time 1313579787 ps
CPU time 2.76 seconds
Started Feb 25 12:32:51 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 204124 kb
Host smart-a8ae0836-16a2-44ce-9557-4bc4532dd2c7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108266216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
2108266216
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.2755137497
Short name T326
Test name
Test status
Simulation time 121142896 ps
CPU time 0.73 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:35 PM PST 24
Peak memory 203908 kb
Host smart-8dcdaba9-d5b9-48e8-9986-ce9079b3fd4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2755137497 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
2755137497
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.3407950634
Short name T339
Test name
Test status
Simulation time 470221269 ps
CPU time 3.91 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:42 PM PST 24
Peak memory 204176 kb
Host smart-6a34fdc3-398d-4c00-a6d4-0a0503e81029
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3407950634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.3407950634
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.3577050017
Short name T312
Test name
Test status
Simulation time 57976203 ps
CPU time 3.09 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:55 PM PST 24
Peak memory 204256 kb
Host smart-b7827756-c4d8-4cc0-bc40-0ad8b09cb9ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577050017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.3577050017
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1683372164
Short name T130
Test name
Test status
Simulation time 1036373018 ps
CPU time 9 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 212468 kb
Host smart-8b4d1801-ba0b-4625-b288-4a6612de0768
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683372164 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
683372164
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.773340383
Short name T303
Test name
Test status
Simulation time 1518591942 ps
CPU time 3.09 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:45 PM PST 24
Peak memory 212524 kb
Host smart-f3b9843a-240c-4cc8-8d7c-9c466061f41b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773340383 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.773340383
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.520525334
Short name T274
Test name
Test status
Simulation time 199644050 ps
CPU time 2.07 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:41 PM PST 24
Peak memory 204092 kb
Host smart-8b21a350-f8da-4eed-bbed-6a0ca2835a5e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520525334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.520525334
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.956670355
Short name T296
Test name
Test status
Simulation time 373887142 ps
CPU time 1.48 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 204196 kb
Host smart-39615026-fc41-4521-b08e-787dd27b3e1e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956670355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.956670355
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2547173495
Short name T238
Test name
Test status
Simulation time 59008910 ps
CPU time 0.78 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 203916 kb
Host smart-758c0eb5-980a-4e25-8abe-2fc0ad5068dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547173495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2547173495
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.613076652
Short name T119
Test name
Test status
Simulation time 513095333 ps
CPU time 7.09 seconds
Started Feb 25 12:32:46 PM PST 24
Finished Feb 25 12:32:53 PM PST 24
Peak memory 204128 kb
Host smart-84a38ce0-e77a-4fca-a07e-cad8824aca72
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613076652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same_
csr_outstanding.613076652
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.501348592
Short name T80
Test name
Test status
Simulation time 764244253 ps
CPU time 4.21 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:32:55 PM PST 24
Peak memory 212532 kb
Host smart-605c5333-0606-46e5-9e93-f475a600da65
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501348592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.501348592
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4259969400
Short name T125
Test name
Test status
Simulation time 635789482 ps
CPU time 9.19 seconds
Started Feb 25 12:32:40 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 212508 kb
Host smart-4488f830-f8ca-4e90-8d24-93980053bf44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259969400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
259969400
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.1310721323
Short name T260
Test name
Test status
Simulation time 3290008028 ps
CPU time 6.06 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:44 PM PST 24
Peak memory 216288 kb
Host smart-6cdd2946-8155-48ac-ad25-f9ac1561254d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310721323 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.1310721323
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.693611758
Short name T109
Test name
Test status
Simulation time 82173327 ps
CPU time 2 seconds
Started Feb 25 12:32:57 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 212472 kb
Host smart-cec87ee5-e59a-4ab7-92aa-92c41a284a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693611758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.693611758
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.2068345237
Short name T236
Test name
Test status
Simulation time 493549520 ps
CPU time 1.29 seconds
Started Feb 25 12:32:47 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 204092 kb
Host smart-dbcde739-9fd4-4841-9a63-ed15086f296d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068345237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
2068345237
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.1847869415
Short name T359
Test name
Test status
Simulation time 85053575 ps
CPU time 0.66 seconds
Started Feb 25 12:34:33 PM PST 24
Finished Feb 25 12:34:34 PM PST 24
Peak memory 203852 kb
Host smart-ff182885-e779-449f-b73f-8e6c8f6ca625
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847869415 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
1847869415
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.3574427562
Short name T116
Test name
Test status
Simulation time 227453165 ps
CPU time 3.45 seconds
Started Feb 25 12:32:47 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 204184 kb
Host smart-d0f98451-5ce7-4ba5-ac76-7559cdb2b7e4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574427562 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.3574427562
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tap_fsm_rand_reset.430183332
Short name T328
Test name
Test status
Simulation time 26637702211 ps
CPU time 28.17 seconds
Started Feb 25 12:32:56 PM PST 24
Finished Feb 25 12:33:25 PM PST 24
Peak memory 228524 kb
Host smart-33ba58d5-3a19-4b14-b7b0-116841925b07
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430183332 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.rv_dm_tap_fsm_rand_reset.430183332
Directory /workspace/18.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.2994634100
Short name T279
Test name
Test status
Simulation time 414791475 ps
CPU time 6.1 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 212464 kb
Host smart-a239fda6-0849-477e-acda-006dfdef87d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994634100 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.2994634100
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.4110340860
Short name T281
Test name
Test status
Simulation time 57963192 ps
CPU time 1.78 seconds
Started Feb 25 12:34:28 PM PST 24
Finished Feb 25 12:34:32 PM PST 24
Peak memory 212784 kb
Host smart-66d3c081-df28-4d19-824a-38e2972fbc57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110340860 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.4110340860
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.591965061
Short name T102
Test name
Test status
Simulation time 160831107 ps
CPU time 2.22 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 202672 kb
Host smart-67608b93-1a9a-43c2-bd49-2f49c0583ac0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591965061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.591965061
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1366860445
Short name T240
Test name
Test status
Simulation time 518347032 ps
CPU time 1.62 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:45 PM PST 24
Peak memory 204400 kb
Host smart-625c47fe-87ff-4203-9848-b4deabf61679
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366860445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1366860445
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.2442994205
Short name T232
Test name
Test status
Simulation time 60803322 ps
CPU time 0.83 seconds
Started Feb 25 12:32:40 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 203904 kb
Host smart-055c9e3d-81a8-4dbf-8a58-d936d66897eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442994205 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
2442994205
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.31439251
Short name T46
Test name
Test status
Simulation time 150011561 ps
CPU time 6.17 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 204252 kb
Host smart-ffdc5116-c771-420c-aeb7-b838342a2453
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31439251 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_c
sr_outstanding.31439251
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.3877090306
Short name T146
Test name
Test status
Simulation time 4694077783 ps
CPU time 17.49 seconds
Started Feb 25 12:32:49 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 212524 kb
Host smart-a9ecf41e-228b-450e-ab99-474060a05199
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877090306 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.3877090306
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.4031302069
Short name T257
Test name
Test status
Simulation time 135065504 ps
CPU time 4.08 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:56 PM PST 24
Peak memory 204696 kb
Host smart-de43d27e-90c2-4977-8a62-71057c2d6a12
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031302069 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.4031302069
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.308040050
Short name T40
Test name
Test status
Simulation time 3998907418 ps
CPU time 16.04 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 213092 kb
Host smart-723917b8-37de-45e6-b8e1-b532fd0c1cb4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308040050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.308040050
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.468458759
Short name T112
Test name
Test status
Simulation time 5223506305 ps
CPU time 79.31 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 204256 kb
Host smart-c34f7e07-086d-4293-8aef-9591dcce6040
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468458759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 2.rv_dm_csr_aliasing.468458759
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.1924372697
Short name T355
Test name
Test status
Simulation time 26848100673 ps
CPU time 76.78 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 204228 kb
Host smart-b339ffd3-95bc-49ad-876e-c67a8180465b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924372697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.1924372697
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.2136147099
Short name T311
Test name
Test status
Simulation time 337699047 ps
CPU time 2.35 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:55 PM PST 24
Peak memory 204160 kb
Host smart-1c4416a1-f1fb-43dd-9db5-3d91040a35fd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136147099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.2136147099
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1965599048
Short name T45
Test name
Test status
Simulation time 1174020981 ps
CPU time 5.35 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 216180 kb
Host smart-4932f20d-a485-44af-91ae-007feaa725df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965599048 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1965599048
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3507432704
Short name T356
Test name
Test status
Simulation time 58975131 ps
CPU time 1.32 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:32:34 PM PST 24
Peak memory 204204 kb
Host smart-e1b6a753-6c67-4ca3-880c-b587376902f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3507432704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3507432704
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2564089818
Short name T226
Test name
Test status
Simulation time 5611059314 ps
CPU time 22.24 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:33:00 PM PST 24
Peak memory 204108 kb
Host smart-13f4f399-6562-4915-924b-9e2efe079826
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564089818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2564089818
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1693912425
Short name T327
Test name
Test status
Simulation time 13534817825 ps
CPU time 52.86 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:33:29 PM PST 24
Peak memory 204392 kb
Host smart-3c6dabdd-1f97-43c2-857d-c3cf830b960c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693912425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1693912425
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.1734626986
Short name T95
Test name
Test status
Simulation time 1710426350 ps
CPU time 5.82 seconds
Started Feb 25 12:32:19 PM PST 24
Finished Feb 25 12:32:25 PM PST 24
Peak memory 204208 kb
Host smart-677cc9e6-c074-409d-ba52-a0e1c484d6dd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734626986 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_hw_reset.1734626986
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.843766601
Short name T357
Test name
Test status
Simulation time 482691125 ps
CPU time 1.75 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 204124 kb
Host smart-7c15d0c1-ef12-4bd2-a0e0-c2bd6db3cc7c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843766601 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.843766601
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.261935965
Short name T369
Test name
Test status
Simulation time 73776957 ps
CPU time 0.73 seconds
Started Feb 25 12:32:27 PM PST 24
Finished Feb 25 12:32:29 PM PST 24
Peak memory 203904 kb
Host smart-89122ef6-d496-4edb-b1d1-910545bbe864
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261935965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_aliasing.261935965
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1742175344
Short name T287
Test name
Test status
Simulation time 633339875 ps
CPU time 1.7 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204160 kb
Host smart-098d4724-47e2-4fe4-a503-5ed87cc37a81
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742175344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1742175344
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2240422027
Short name T285
Test name
Test status
Simulation time 88876708 ps
CPU time 0.67 seconds
Started Feb 25 12:32:29 PM PST 24
Finished Feb 25 12:32:30 PM PST 24
Peak memory 203992 kb
Host smart-6c1365c1-118a-42ca-a836-71f7cc513522
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240422027 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2240422027
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3036513482
Short name T351
Test name
Test status
Simulation time 93111674 ps
CPU time 0.66 seconds
Started Feb 25 12:32:18 PM PST 24
Finished Feb 25 12:32:18 PM PST 24
Peak memory 203928 kb
Host smart-e0e50431-f130-448d-86b6-97a659d7ef08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036513482 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
036513482
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.638351247
Short name T342
Test name
Test status
Simulation time 28850112 ps
CPU time 0.63 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 203860 kb
Host smart-b95c6985-1fd3-4d70-8fb7-8804aa97f499
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638351247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_part
ial_access.638351247
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.741558876
Short name T367
Test name
Test status
Simulation time 49443767 ps
CPU time 0.62 seconds
Started Feb 25 12:32:26 PM PST 24
Finished Feb 25 12:32:28 PM PST 24
Peak memory 203920 kb
Host smart-980e1928-8734-4773-a2cd-6d95da348098
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741558876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.741558876
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2156040690
Short name T114
Test name
Test status
Simulation time 397635465 ps
CPU time 3.86 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 204228 kb
Host smart-4281fcdc-ef15-4aa3-a5fa-ae5169c82e60
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156040690 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2156040690
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tap_fsm_rand_reset.1566595296
Short name T77
Test name
Test status
Simulation time 10561481360 ps
CPU time 35.54 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:33:18 PM PST 24
Peak memory 220640 kb
Host smart-ab4375ae-3276-4b19-9b70-f2d73166a300
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566595296 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rv_dm_tap_fsm_rand_reset.1566595296
Directory /workspace/2.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.57279202
Short name T310
Test name
Test status
Simulation time 731052950 ps
CPU time 5.67 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 212476 kb
Host smart-2fd3f2f9-b416-447a-ba38-eb9185f060a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57279202 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.57279202
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.2572579906
Short name T300
Test name
Test status
Simulation time 1627863297 ps
CPU time 10.08 seconds
Started Feb 25 12:32:20 PM PST 24
Finished Feb 25 12:32:30 PM PST 24
Peak memory 212584 kb
Host smart-827cf8cc-0af9-4a4a-a9e5-5378b902e1a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572579906 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.2572579906
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/22.rv_dm_tap_fsm_rand_reset.391029015
Short name T319
Test name
Test status
Simulation time 28087271384 ps
CPU time 27.19 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:33:04 PM PST 24
Peak memory 220660 kb
Host smart-198d0074-82f3-423b-aff8-4e373e42bcad
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391029015 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 22.rv_dm_tap_fsm_rand_reset.391029015
Directory /workspace/22.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.505662003
Short name T332
Test name
Test status
Simulation time 20708512123 ps
CPU time 27.11 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:33:17 PM PST 24
Peak memory 220276 kb
Host smart-5ba2ee10-422d-4173-89e4-e92db845e68f
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505662003 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.505662003
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/27.rv_dm_tap_fsm_rand_reset.2930171733
Short name T278
Test name
Test status
Simulation time 14734103139 ps
CPU time 12.55 seconds
Started Feb 25 12:32:46 PM PST 24
Finished Feb 25 12:32:58 PM PST 24
Peak memory 212480 kb
Host smart-88333603-2f12-4192-a8d5-ec4610898dd3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930171733 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 27.rv_dm_tap_fsm_rand_reset.2930171733
Directory /workspace/27.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.2540264334
Short name T308
Test name
Test status
Simulation time 28937714402 ps
CPU time 75.66 seconds
Started Feb 25 12:32:32 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 204244 kb
Host smart-e19d5dc8-9c99-4f2d-9b2f-1aad560c2bea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540264334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.2540264334
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.3095444400
Short name T107
Test name
Test status
Simulation time 98218677 ps
CPU time 2.42 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 212432 kb
Host smart-b665e746-9fb7-40a7-a964-e60aa3b34a2b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3095444400 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.3095444400
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.295481818
Short name T74
Test name
Test status
Simulation time 119983455 ps
CPU time 2.27 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 214032 kb
Host smart-b321c8d5-d8f4-49f3-8282-41a5bea9f676
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295481818 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.295481818
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2475946564
Short name T100
Test name
Test status
Simulation time 61689190 ps
CPU time 1.52 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 212448 kb
Host smart-83c6fce2-380c-4167-a77b-4d44ba0f27a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475946564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2475946564
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.521609774
Short name T290
Test name
Test status
Simulation time 21698365549 ps
CPU time 67.38 seconds
Started Feb 25 12:32:16 PM PST 24
Finished Feb 25 12:33:24 PM PST 24
Peak memory 204192 kb
Host smart-ea3c7512-5a04-41a5-ba19-fe236c1b1ab9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521609774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.521609774
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.1317553254
Short name T313
Test name
Test status
Simulation time 44737117890 ps
CPU time 74.04 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 204144 kb
Host smart-9319b611-aa9c-434f-a096-bfb127823bf7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317553254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_bit_bash.1317553254
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.3846249409
Short name T96
Test name
Test status
Simulation time 1099995826 ps
CPU time 2.61 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:46 PM PST 24
Peak memory 204180 kb
Host smart-3d6113a8-1259-4146-9f35-8ba476e5fb4f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846249409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_hw_reset.3846249409
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.367125936
Short name T262
Test name
Test status
Simulation time 814593258 ps
CPU time 1.28 seconds
Started Feb 25 12:32:19 PM PST 24
Finished Feb 25 12:32:20 PM PST 24
Peak memory 204084 kb
Host smart-efa235a4-f354-4dd8-a6f2-f73a7e0d8d1c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367125936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.367125936
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.4081861310
Short name T288
Test name
Test status
Simulation time 239730611 ps
CPU time 0.77 seconds
Started Feb 25 12:32:21 PM PST 24
Finished Feb 25 12:32:22 PM PST 24
Peak memory 203916 kb
Host smart-325ad388-40c2-4ba9-b3bf-34401dd74114
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081861310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.4081861310
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.315065895
Short name T354
Test name
Test status
Simulation time 3354625423 ps
CPU time 11.16 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 204072 kb
Host smart-40a23f4d-1091-480a-a4ac-729a536dc64c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315065895 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_bit_bash.315065895
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.93830250
Short name T314
Test name
Test status
Simulation time 99941905 ps
CPU time 0.88 seconds
Started Feb 25 12:32:30 PM PST 24
Finished Feb 25 12:32:31 PM PST 24
Peak memory 203952 kb
Host smart-b565532d-8107-40d7-be4b-cba2269ac7e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93830250 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_
hw_reset.93830250
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.4094779505
Short name T364
Test name
Test status
Simulation time 56267738 ps
CPU time 0.73 seconds
Started Feb 25 12:32:23 PM PST 24
Finished Feb 25 12:32:25 PM PST 24
Peak memory 203928 kb
Host smart-324569b8-505f-45a4-a2eb-4933f098fc30
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094779505 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.4
094779505
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2830501891
Short name T321
Test name
Test status
Simulation time 28092742 ps
CPU time 0.65 seconds
Started Feb 25 12:32:27 PM PST 24
Finished Feb 25 12:32:28 PM PST 24
Peak memory 203864 kb
Host smart-2dee1b36-9c9b-4a27-9f75-e977ef38063a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830501891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2830501891
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.1651349200
Short name T306
Test name
Test status
Simulation time 27112673 ps
CPU time 0.65 seconds
Started Feb 25 12:32:32 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 203928 kb
Host smart-4785855c-9f98-4c7a-b0fc-7bb6ee139110
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651349200 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.1651349200
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.710858668
Short name T350
Test name
Test status
Simulation time 77884877 ps
CPU time 3.58 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 204228 kb
Host smart-a2152f15-2a8e-4d96-b36f-926412ff0b40
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710858668 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.710858668
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.449996413
Short name T347
Test name
Test status
Simulation time 505113987 ps
CPU time 6.32 seconds
Started Feb 25 12:32:43 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 204368 kb
Host smart-2a2e1993-28d5-449c-b94f-543f19af9481
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449996413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.449996413
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1710266872
Short name T124
Test name
Test status
Simulation time 1644384230 ps
CPU time 19.09 seconds
Started Feb 25 12:32:30 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 214484 kb
Host smart-c0b6d833-9d1b-43c1-9625-aef10b641be8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710266872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1710266872
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1200294291
Short name T275
Test name
Test status
Simulation time 44938539578 ps
CPU time 24.27 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:24 PM PST 24
Peak memory 232912 kb
Host smart-d90955a1-2aae-47dd-b34f-73a123a84e89
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200294291 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1200294291
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.725894716
Short name T267
Test name
Test status
Simulation time 6399254005 ps
CPU time 20.01 seconds
Started Feb 25 12:32:39 PM PST 24
Finished Feb 25 12:32:59 PM PST 24
Peak memory 218160 kb
Host smart-19a16dc1-3d30-43f7-b0e2-7d389934be1e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725894716 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.725894716
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.2584056474
Short name T78
Test name
Test status
Simulation time 6129631641 ps
CPU time 20.49 seconds
Started Feb 25 12:33:01 PM PST 24
Finished Feb 25 12:33:21 PM PST 24
Peak memory 212480 kb
Host smart-bc215888-535f-4f80-8868-b5153dad1986
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584056474 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.2584056474
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/36.rv_dm_tap_fsm_rand_reset.3330147241
Short name T349
Test name
Test status
Simulation time 11576261576 ps
CPU time 15.44 seconds
Started Feb 25 12:32:58 PM PST 24
Finished Feb 25 12:33:13 PM PST 24
Peak memory 212480 kb
Host smart-2652b80e-f1fe-42e4-9580-3d71a5eb0bf4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330147241 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 36.rv_dm_tap_fsm_rand_reset.3330147241
Directory /workspace/36.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.3148797686
Short name T304
Test name
Test status
Simulation time 27320805864 ps
CPU time 79.99 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 204336 kb
Host smart-a6e5fdbb-c774-4379-98e6-9518f7c93624
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148797686 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.3148797686
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.1641999786
Short name T108
Test name
Test status
Simulation time 15148148681 ps
CPU time 36.46 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:33:29 PM PST 24
Peak memory 204284 kb
Host smart-45bf49be-302d-4dc8-8c06-8ff66629fc93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641999786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.1641999786
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2678002704
Short name T250
Test name
Test status
Simulation time 635943500 ps
CPU time 2.47 seconds
Started Feb 25 12:32:23 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204172 kb
Host smart-0a0d2580-e96c-4a01-80b3-7d70305f08da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678002704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2678002704
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.706008993
Short name T361
Test name
Test status
Simulation time 1976992830 ps
CPU time 4.49 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 216456 kb
Host smart-f13a9b96-efea-4ec4-a039-cb6ed2eef7b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706008993 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.706008993
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.3439845346
Short name T113
Test name
Test status
Simulation time 50580603 ps
CPU time 1.48 seconds
Started Feb 25 12:32:27 PM PST 24
Finished Feb 25 12:32:30 PM PST 24
Peak memory 204196 kb
Host smart-9232dc14-e3d0-4cfd-9687-087cd0df82cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439845346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.3439845346
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.2637115263
Short name T365
Test name
Test status
Simulation time 19539588090 ps
CPU time 21.48 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:33:00 PM PST 24
Peak memory 204080 kb
Host smart-f3c67a90-9114-4967-bcef-3e301b4544e9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637115263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.2637115263
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3492238714
Short name T237
Test name
Test status
Simulation time 8521923944 ps
CPU time 38.95 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:33:31 PM PST 24
Peak memory 204144 kb
Host smart-de2a0d13-1dec-4557-9e6e-aa1d6e34361a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492238714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3492238714
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.2801367386
Short name T97
Test name
Test status
Simulation time 483418917 ps
CPU time 1.24 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 204152 kb
Host smart-37b21b26-87f1-42b8-b2cb-21cde5fdba5d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801367386 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.2801367386
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.529647554
Short name T299
Test name
Test status
Simulation time 321921306 ps
CPU time 1.71 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:32 PM PST 24
Peak memory 204068 kb
Host smart-c0dbe168-5106-4c1d-a84e-b06a0189879f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529647554 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.529647554
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.737426405
Short name T276
Test name
Test status
Simulation time 101125008 ps
CPU time 0.88 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 203912 kb
Host smart-e93e58ff-1478-45fb-8952-d97da017b0e5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737426405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.737426405
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.2551809221
Short name T348
Test name
Test status
Simulation time 925862134 ps
CPU time 2.99 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 204180 kb
Host smart-9f9bb23b-0e38-4768-9a39-8630d5dca8d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551809221 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.2551809221
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3409998344
Short name T280
Test name
Test status
Simulation time 135268052 ps
CPU time 0.71 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 203976 kb
Host smart-05b7b5df-f297-4c44-b107-41cedfec07cf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409998344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3409998344
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2518690154
Short name T245
Test name
Test status
Simulation time 91334431 ps
CPU time 0.73 seconds
Started Feb 25 12:32:26 PM PST 24
Finished Feb 25 12:32:28 PM PST 24
Peak memory 203928 kb
Host smart-86519c62-5b5e-43bc-8d42-46d993cdd1bd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518690154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
518690154
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1346617089
Short name T291
Test name
Test status
Simulation time 92237136 ps
CPU time 0.61 seconds
Started Feb 25 12:32:33 PM PST 24
Finished Feb 25 12:32:34 PM PST 24
Peak memory 203816 kb
Host smart-b04e9162-864d-4937-8ff7-6ae2da5a08d0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346617089 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1346617089
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1984578556
Short name T271
Test name
Test status
Simulation time 19770212 ps
CPU time 0.62 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:49 PM PST 24
Peak memory 203912 kb
Host smart-f47ad581-edea-4af7-8ff2-63a67008e830
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984578556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1984578556
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.1104048759
Short name T47
Test name
Test status
Simulation time 1279539184 ps
CPU time 7.8 seconds
Started Feb 25 12:32:27 PM PST 24
Finished Feb 25 12:32:35 PM PST 24
Peak memory 204284 kb
Host smart-e8aa60b1-35db-40ff-88fd-4ddbcc63ebff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104048759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.1104048759
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tap_fsm_rand_reset.1588814330
Short name T59
Test name
Test status
Simulation time 29174881640 ps
CPU time 9.16 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:57 PM PST 24
Peak memory 216812 kb
Host smart-3b18f0ac-67e2-4e51-93b5-1d044e2b1517
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588814330 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rv_dm_tap_fsm_rand_reset.1588814330
Directory /workspace/4.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2514329767
Short name T76
Test name
Test status
Simulation time 881691866 ps
CPU time 4.96 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 212480 kb
Host smart-7f1a791e-42fa-498a-b7aa-1dd5d9cfd4b4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514329767 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2514329767
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.517824479
Short name T94
Test name
Test status
Simulation time 1929038289 ps
CPU time 10.12 seconds
Started Feb 25 12:32:45 PM PST 24
Finished Feb 25 12:32:55 PM PST 24
Peak memory 212588 kb
Host smart-5ef65661-f493-40da-a65f-cb8e93bf441c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=517824479 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.517824479
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.883324380
Short name T263
Test name
Test status
Simulation time 65154033 ps
CPU time 2.05 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 214036 kb
Host smart-63d0c952-629f-4be2-acbb-7c196c738ec3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883324380 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.883324380
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.3237660033
Short name T87
Test name
Test status
Simulation time 119893984 ps
CPU time 2.12 seconds
Started Feb 25 12:32:32 PM PST 24
Finished Feb 25 12:32:34 PM PST 24
Peak memory 212476 kb
Host smart-4172c250-0c82-4ca9-a011-851c75058147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237660033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.3237660033
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.2233557
Short name T345
Test name
Test status
Simulation time 1192889045 ps
CPU time 1.52 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204128 kb
Host smart-ab966825-910b-4810-84ec-f22577969dc2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.2233557
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.3826540930
Short name T264
Test name
Test status
Simulation time 65585921 ps
CPU time 0.67 seconds
Started Feb 25 12:32:27 PM PST 24
Finished Feb 25 12:32:28 PM PST 24
Peak memory 203924 kb
Host smart-7145f4b1-95dc-4610-965d-d9f067b966b7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826540930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.3
826540930
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.1378534557
Short name T338
Test name
Test status
Simulation time 283188377 ps
CPU time 4.37 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:41 PM PST 24
Peak memory 204284 kb
Host smart-6cd3df97-e979-4ca6-891f-1898e2fd6314
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378534557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.1378534557
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.1448875149
Short name T336
Test name
Test status
Simulation time 222377347 ps
CPU time 4.97 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:41 PM PST 24
Peak memory 204328 kb
Host smart-369d05a9-51f1-496d-8e47-f4f29496d679
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448875149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.1448875149
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.1071186045
Short name T352
Test name
Test status
Simulation time 14732610484 ps
CPU time 22.16 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:33:06 PM PST 24
Peak memory 217260 kb
Host smart-d6f4d163-dadd-497d-b795-19b9ce70d2f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071186045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.1071186045
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1999456135
Short name T259
Test name
Test status
Simulation time 1465954273 ps
CPU time 4.11 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 214148 kb
Host smart-84fee8c3-7e80-4aa1-b6b8-74bf77872f37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999456135 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1999456135
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.155142685
Short name T91
Test name
Test status
Simulation time 319389734 ps
CPU time 1.45 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204432 kb
Host smart-4f00df97-6ff2-4435-917b-de49d89df007
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155142685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.155142685
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.11076889
Short name T302
Test name
Test status
Simulation time 198958006 ps
CPU time 1.33 seconds
Started Feb 25 12:32:21 PM PST 24
Finished Feb 25 12:32:23 PM PST 24
Peak memory 204100 kb
Host smart-65a32757-15fc-4fbb-968f-01cec2e37ac3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.11076889
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2490141547
Short name T269
Test name
Test status
Simulation time 128692014 ps
CPU time 0.8 seconds
Started Feb 25 12:32:49 PM PST 24
Finished Feb 25 12:32:50 PM PST 24
Peak memory 203928 kb
Host smart-dee2446f-cdfa-40ba-a101-98b29dff4f6e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490141547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
490141547
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2719676407
Short name T297
Test name
Test status
Simulation time 797236652 ps
CPU time 4.11 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 204256 kb
Host smart-72ef3e64-955c-46e8-946b-28836766a6dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719676407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2719676407
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3250190685
Short name T298
Test name
Test status
Simulation time 1829587972 ps
CPU time 6.41 seconds
Started Feb 25 12:32:29 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 212476 kb
Host smart-b54e3cc0-49d0-48c3-90ff-cb4d6d367dbc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3250190685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3250190685
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3729778734
Short name T129
Test name
Test status
Simulation time 890512366 ps
CPU time 15.54 seconds
Started Feb 25 12:32:59 PM PST 24
Finished Feb 25 12:33:15 PM PST 24
Peak memory 212416 kb
Host smart-d66a64af-2820-4695-8df8-219752ad1a9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729778734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3729778734
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2875465401
Short name T284
Test name
Test status
Simulation time 4384182412 ps
CPU time 6.98 seconds
Started Feb 25 12:32:41 PM PST 24
Finished Feb 25 12:32:48 PM PST 24
Peak memory 216836 kb
Host smart-a947ae00-0522-4eb6-8a60-ca2879c199d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875465401 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2875465401
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.783908071
Short name T90
Test name
Test status
Simulation time 129002694 ps
CPU time 2.41 seconds
Started Feb 25 12:32:52 PM PST 24
Finished Feb 25 12:33:00 PM PST 24
Peak memory 212416 kb
Host smart-539528a2-b185-4771-a342-9f859aa4eb8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783908071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.783908071
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.902241888
Short name T256
Test name
Test status
Simulation time 438870460 ps
CPU time 1.19 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 204124 kb
Host smart-f823e493-c0d6-4fb2-9897-724bd8ef2b92
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902241888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.902241888
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.437963129
Short name T70
Test name
Test status
Simulation time 50690397 ps
CPU time 0.68 seconds
Started Feb 25 12:32:25 PM PST 24
Finished Feb 25 12:32:26 PM PST 24
Peak memory 203916 kb
Host smart-40dc6bd3-2515-435b-ad3d-29305d342f9a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=437963129 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.437963129
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.577740595
Short name T104
Test name
Test status
Simulation time 414734637 ps
CPU time 7.67 seconds
Started Feb 25 12:32:19 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 204248 kb
Host smart-93fd3d91-377f-495f-80e9-cb854d508c8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577740595 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_c
sr_outstanding.577740595
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tap_fsm_rand_reset.1330374855
Short name T331
Test name
Test status
Simulation time 2742584298 ps
CPU time 12.13 seconds
Started Feb 25 12:32:49 PM PST 24
Finished Feb 25 12:33:02 PM PST 24
Peak memory 212512 kb
Host smart-31b34e11-def0-4326-aa53-6e5d828d99be
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330374855 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rv_dm_tap_fsm_rand_reset.1330374855
Directory /workspace/7.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.2584350600
Short name T353
Test name
Test status
Simulation time 172808068 ps
CPU time 4.35 seconds
Started Feb 25 12:32:22 PM PST 24
Finished Feb 25 12:32:27 PM PST 24
Peak memory 212484 kb
Host smart-a7156120-9b47-42ee-9004-e6d6ae07d1e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584350600 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.2584350600
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.2103984768
Short name T246
Test name
Test status
Simulation time 4107992637 ps
CPU time 7.9 seconds
Started Feb 25 12:32:44 PM PST 24
Finished Feb 25 12:32:52 PM PST 24
Peak memory 220652 kb
Host smart-1bd63cbd-c92a-411b-93ae-20eeb1b347c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103984768 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.2103984768
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.447831891
Short name T266
Test name
Test status
Simulation time 75128228 ps
CPU time 2.05 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:36 PM PST 24
Peak memory 204152 kb
Host smart-00f8d23b-2cb4-4493-801b-fd73c94c2b78
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447831891 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.447831891
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1689227950
Short name T366
Test name
Test status
Simulation time 1679683184 ps
CPU time 3.62 seconds
Started Feb 25 12:33:01 PM PST 24
Finished Feb 25 12:33:05 PM PST 24
Peak memory 204088 kb
Host smart-352b3c05-7c49-4e60-8b42-d8952e81afa0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689227950 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
689227950
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.420093867
Short name T228
Test name
Test status
Simulation time 68918345 ps
CPU time 0.81 seconds
Started Feb 25 12:32:38 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 203908 kb
Host smart-487eb2a6-0675-4233-9ce4-c707c30e2ed1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420093867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.420093867
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.1679472864
Short name T105
Test name
Test status
Simulation time 3667714064 ps
CPU time 4.05 seconds
Started Feb 25 12:32:35 PM PST 24
Finished Feb 25 12:32:39 PM PST 24
Peak memory 204280 kb
Host smart-6c67fc81-92fb-4a9d-81f7-5f03afe7e4f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679472864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.1679472864
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.2483387166
Short name T286
Test name
Test status
Simulation time 166341830 ps
CPU time 3.9 seconds
Started Feb 25 12:32:34 PM PST 24
Finished Feb 25 12:32:38 PM PST 24
Peak memory 212484 kb
Host smart-79d642e0-d233-49b8-ab94-fcfc2b5e7c61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483387166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.2483387166
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.2955846006
Short name T346
Test name
Test status
Simulation time 739875711 ps
CPU time 15 seconds
Started Feb 25 12:32:31 PM PST 24
Finished Feb 25 12:32:47 PM PST 24
Peak memory 212492 kb
Host smart-c48ec9ad-9277-40a5-bc70-0e4e1501331f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955846006 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.2955846006
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3359797008
Short name T362
Test name
Test status
Simulation time 565427592 ps
CPU time 3.37 seconds
Started Feb 25 12:32:37 PM PST 24
Finished Feb 25 12:32:40 PM PST 24
Peak memory 213544 kb
Host smart-fdaf9d07-0c28-444e-a4bd-eb0bf5c30e15
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359797008 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3359797008
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.1427478904
Short name T283
Test name
Test status
Simulation time 80286940 ps
CPU time 1.37 seconds
Started Feb 25 12:33:00 PM PST 24
Finished Feb 25 12:33:01 PM PST 24
Peak memory 204160 kb
Host smart-5acf63b4-b840-43a5-8d20-43f7acd7ce8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427478904 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.1427478904
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.2505413696
Short name T225
Test name
Test status
Simulation time 510490104 ps
CPU time 1.4 seconds
Started Feb 25 12:32:42 PM PST 24
Finished Feb 25 12:32:43 PM PST 24
Peak memory 204176 kb
Host smart-0c483054-74f4-4a42-a514-71ebbc571f55
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505413696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.2
505413696
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.769189969
Short name T251
Test name
Test status
Simulation time 64091453 ps
CPU time 0.65 seconds
Started Feb 25 12:32:36 PM PST 24
Finished Feb 25 12:32:37 PM PST 24
Peak memory 203900 kb
Host smart-4e30ef30-e8ac-4e74-a7ed-c23a82e125c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=769189969 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.769189969
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.3463224355
Short name T101
Test name
Test status
Simulation time 628635050 ps
CPU time 3.63 seconds
Started Feb 25 12:32:46 PM PST 24
Finished Feb 25 12:32:54 PM PST 24
Peak memory 204220 kb
Host smart-256216ea-d29c-4a20-acf5-767917db9503
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463224355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.3463224355
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.711773401
Short name T318
Test name
Test status
Simulation time 8451242073 ps
CPU time 16.23 seconds
Started Feb 25 12:32:50 PM PST 24
Finished Feb 25 12:33:07 PM PST 24
Peak memory 211196 kb
Host smart-7f14f580-b114-4061-8a41-6f7ebda57f6d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711773401 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.711773401
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2430307617
Short name T249
Test name
Test status
Simulation time 42615388 ps
CPU time 2.42 seconds
Started Feb 25 12:32:48 PM PST 24
Finished Feb 25 12:32:51 PM PST 24
Peak memory 212480 kb
Host smart-0cfcebbb-7f70-4e62-a199-7f85c3e68188
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430307617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2430307617
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.2156226423
Short name T152
Test name
Test status
Simulation time 65824976 ps
CPU time 0.64 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203220 kb
Host smart-5366332d-86b4-4dfc-8347-efd1bf83d854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156226423 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.2156226423
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1017768050
Short name T201
Test name
Test status
Simulation time 5373471751 ps
CPU time 19.61 seconds
Started Feb 25 12:33:18 PM PST 24
Finished Feb 25 12:33:38 PM PST 24
Peak memory 203808 kb
Host smart-9a894ac7-50df-43e3-a1f1-2322733e6ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017768050 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1017768050
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.3547508694
Short name T27
Test name
Test status
Simulation time 2523493848 ps
CPU time 2.28 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:40 PM PST 24
Peak memory 203636 kb
Host smart-5839d8cf-3e14-4039-8642-209a8ae077ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547508694 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.3547508694
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1278715506
Short name T133
Test name
Test status
Simulation time 91063514 ps
CPU time 0.72 seconds
Started Feb 25 12:33:29 PM PST 24
Finished Feb 25 12:33:30 PM PST 24
Peak memory 203368 kb
Host smart-df928072-96a9-4802-a199-f31c6ddf90c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278715506 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1278715506
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.3457473899
Short name T221
Test name
Test status
Simulation time 399881818 ps
CPU time 1.4 seconds
Started Feb 25 12:33:39 PM PST 24
Finished Feb 25 12:33:41 PM PST 24
Peak memory 203668 kb
Host smart-ee6928cb-f662-4fd0-8995-ae90d74cd41d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3457473899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.3457473899
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1099439317
Short name T83
Test name
Test status
Simulation time 151948113 ps
CPU time 1.22 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:33:58 PM PST 24
Peak memory 203520 kb
Host smart-02c37460-7830-466a-b161-1dc0a9119e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099439317 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1099439317
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.1288788359
Short name T212
Test name
Test status
Simulation time 164653143 ps
CPU time 0.84 seconds
Started Feb 25 12:33:34 PM PST 24
Finished Feb 25 12:33:40 PM PST 24
Peak memory 202976 kb
Host smart-5007fa06-28b6-4342-8564-fb237bc859b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288788359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.1288788359
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.1681819540
Short name T208
Test name
Test status
Simulation time 159387968 ps
CPU time 0.94 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:33:55 PM PST 24
Peak memory 203248 kb
Host smart-241a2dfa-3fc0-4c7e-b85d-2cd54fc1a894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681819540 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.1681819540
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.1198492152
Short name T20
Test name
Test status
Simulation time 167684800 ps
CPU time 0.77 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203304 kb
Host smart-d4cfb690-217e-45fb-8aa2-7c27e0ae3d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198492152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.1198492152
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.222402776
Short name T31
Test name
Test status
Simulation time 30156251 ps
CPU time 0.73 seconds
Started Feb 25 12:33:36 PM PST 24
Finished Feb 25 12:33:37 PM PST 24
Peak memory 203060 kb
Host smart-dfdad11c-abad-4fc0-bb9e-b45b14d5fac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222402776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.222402776
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2613132917
Short name T73
Test name
Test status
Simulation time 1087778433 ps
CPU time 0.97 seconds
Started Feb 25 12:33:35 PM PST 24
Finished Feb 25 12:33:36 PM PST 24
Peak memory 203380 kb
Host smart-9f40052c-6cd4-4114-9a17-958fbc9b20b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613132917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2613132917
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.3049049471
Short name T132
Test name
Test status
Simulation time 103519187 ps
CPU time 0.91 seconds
Started Feb 25 12:33:42 PM PST 24
Finished Feb 25 12:33:43 PM PST 24
Peak memory 203340 kb
Host smart-6a7bda5b-4ec0-42bb-853d-4d59b848afbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049049471 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.3049049471
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.4014756784
Short name T84
Test name
Test status
Simulation time 218507241 ps
CPU time 1.38 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203384 kb
Host smart-608b5fee-a0ae-434f-9d47-8cdea62491c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014756784 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.4014756784
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3031849487
Short name T183
Test name
Test status
Simulation time 534559859 ps
CPU time 1.58 seconds
Started Feb 25 12:33:37 PM PST 24
Finished Feb 25 12:33:39 PM PST 24
Peak memory 203392 kb
Host smart-1cf98b67-95a1-45a3-98d2-fbebc8eff9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031849487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3031849487
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.1125408518
Short name T61
Test name
Test status
Simulation time 3563074849 ps
CPU time 3.45 seconds
Started Feb 25 12:33:24 PM PST 24
Finished Feb 25 12:33:27 PM PST 24
Peak memory 203500 kb
Host smart-310dbac0-443e-4d29-9727-a764e5f209af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125408518 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.1125408518
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.1324627372
Short name T143
Test name
Test status
Simulation time 36318547 ps
CPU time 0.71 seconds
Started Feb 25 12:33:32 PM PST 24
Finished Feb 25 12:33:33 PM PST 24
Peak memory 203500 kb
Host smart-3ae75ee5-41a3-47db-b610-2abac5f76aff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324627372 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.1324627372
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.4079005283
Short name T193
Test name
Test status
Simulation time 671085287 ps
CPU time 2.11 seconds
Started Feb 25 12:33:46 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203656 kb
Host smart-81bd5938-cd39-4d54-9508-19cebc59c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079005283 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.4079005283
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.295023344
Short name T11
Test name
Test status
Simulation time 1574698419 ps
CPU time 5.63 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 203456 kb
Host smart-31d614fe-04ff-4534-990e-1b704294f9de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295023344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.295023344
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.3309553744
Short name T4
Test name
Test status
Simulation time 423469580 ps
CPU time 1.34 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:40 PM PST 24
Peak memory 202056 kb
Host smart-4fccce9f-28f4-40f0-a6e7-6b6899dc70fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309553744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.3309553744
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.1525370926
Short name T29
Test name
Test status
Simulation time 344325938 ps
CPU time 1.6 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:46 PM PST 24
Peak memory 203164 kb
Host smart-e39a8171-bfdc-4909-8323-419e0a5c7349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525370926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.1525370926
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.402679929
Short name T207
Test name
Test status
Simulation time 4470532932 ps
CPU time 3.77 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:04 PM PST 24
Peak memory 203632 kb
Host smart-d499900a-adb9-4a14-8fd7-38408ff36e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402679929 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.402679929
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1059642102
Short name T134
Test name
Test status
Simulation time 51306893 ps
CPU time 0.74 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:39 PM PST 24
Peak memory 201912 kb
Host smart-43cb802b-cc25-46a6-88bd-fbc7c550d01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059642102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1059642102
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3985562730
Short name T166
Test name
Test status
Simulation time 2789905141 ps
CPU time 10.71 seconds
Started Feb 25 12:33:34 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203744 kb
Host smart-9058330a-5974-42b4-abd3-90c0de782a7a
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3985562730 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3985562730
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.642983277
Short name T23
Test name
Test status
Simulation time 85115217 ps
CPU time 0.7 seconds
Started Feb 25 12:33:39 PM PST 24
Finished Feb 25 12:33:40 PM PST 24
Peak memory 203300 kb
Host smart-2a792015-19b2-46f5-910f-31ecc4ecec12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642983277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.642983277
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.2072266441
Short name T174
Test name
Test status
Simulation time 454841827 ps
CPU time 0.8 seconds
Started Feb 25 12:33:44 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203304 kb
Host smart-d85cc3cc-b68e-448c-8038-a5497502feb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072266441 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.2072266441
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1025787382
Short name T21
Test name
Test status
Simulation time 266451974 ps
CPU time 1.4 seconds
Started Feb 25 12:33:46 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203276 kb
Host smart-1501b012-2b95-4868-bb38-4b9ddad9e6cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025787382 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1025787382
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.3311565033
Short name T8
Test name
Test status
Simulation time 58427153 ps
CPU time 0.77 seconds
Started Feb 25 12:34:10 PM PST 24
Finished Feb 25 12:34:11 PM PST 24
Peak memory 203252 kb
Host smart-416439c5-50a5-4af6-b356-1a43ba79dec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311565033 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.3311565033
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2113169819
Short name T122
Test name
Test status
Simulation time 781836609 ps
CPU time 1.2 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203196 kb
Host smart-0203880d-9dd3-43bc-89fb-28268beb4247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113169819 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2113169819
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.164971908
Short name T30
Test name
Test status
Simulation time 990720003 ps
CPU time 1.7 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203508 kb
Host smart-a1cec5f4-abeb-4065-bd44-cfd2a5a7ffa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164971908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.164971908
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.134841448
Short name T86
Test name
Test status
Simulation time 441365569 ps
CPU time 1.04 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:39 PM PST 24
Peak memory 203460 kb
Host smart-6ee89888-b8bc-457c-8b84-ab401446c888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134841448 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.134841448
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2717675851
Short name T15
Test name
Test status
Simulation time 497639296 ps
CPU time 0.97 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203420 kb
Host smart-3406ba4a-b2d7-4a5a-8ed8-409a7e5aaea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717675851 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2717675851
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2052431689
Short name T168
Test name
Test status
Simulation time 9848239677 ps
CPU time 30.81 seconds
Started Feb 25 12:33:44 PM PST 24
Finished Feb 25 12:34:16 PM PST 24
Peak memory 203760 kb
Host smart-5ea8ae5b-68fe-420a-bc24-47145040b5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052431689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2052431689
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2307851282
Short name T67
Test name
Test status
Simulation time 62346203 ps
CPU time 1.06 seconds
Started Feb 25 12:33:40 PM PST 24
Finished Feb 25 12:33:41 PM PST 24
Peak memory 218396 kb
Host smart-169bc8fe-9be2-4068-94d5-4fb1d805cb97
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307851282 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2307851282
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.1395894790
Short name T185
Test name
Test status
Simulation time 314614971 ps
CPU time 1.24 seconds
Started Feb 25 12:33:42 PM PST 24
Finished Feb 25 12:33:44 PM PST 24
Peak memory 203308 kb
Host smart-de6fccce-ab26-4ccb-9847-6dd6dea8ba7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395894790 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.1395894790
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.898004016
Short name T148
Test name
Test status
Simulation time 17156781 ps
CPU time 0.65 seconds
Started Feb 25 12:33:47 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203468 kb
Host smart-5bb827c0-0782-4bea-acec-b91e1ac3394c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898004016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.898004016
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1502252971
Short name T215
Test name
Test status
Simulation time 3745700486 ps
CPU time 15.95 seconds
Started Feb 25 12:34:02 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 203808 kb
Host smart-369e7a6f-a053-4a02-816b-656e30e04fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502252971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1502252971
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.3508674714
Short name T213
Test name
Test status
Simulation time 1394403174 ps
CPU time 6.37 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:07 PM PST 24
Peak memory 203616 kb
Host smart-ab705cae-a0ba-4f29-8a55-9e2cdc4a6ca9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3508674714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.3508674714
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.1726392933
Short name T217
Test name
Test status
Simulation time 6875153283 ps
CPU time 14.03 seconds
Started Feb 25 12:33:58 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203808 kb
Host smart-9631b550-f44a-4ee0-bee2-18f0c3a32d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726392933 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.1726392933
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2681355916
Short name T51
Test name
Test status
Simulation time 24813686 ps
CPU time 0.65 seconds
Started Feb 25 12:33:39 PM PST 24
Finished Feb 25 12:33:40 PM PST 24
Peak memory 203500 kb
Host smart-78a5a1ef-d5d0-4d49-aad7-3fc5c8a2d2f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681355916 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2681355916
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4257728152
Short name T180
Test name
Test status
Simulation time 2358227037 ps
CPU time 5.63 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:34:08 PM PST 24
Peak memory 203752 kb
Host smart-3faeac48-2658-4326-a727-3ebc7ed28f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257728152 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4257728152
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.2514094953
Short name T200
Test name
Test status
Simulation time 7455278318 ps
CPU time 8.99 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:34:05 PM PST 24
Peak memory 203788 kb
Host smart-8b85381a-87c9-4318-9048-89900510521f
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2514094953 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.2514094953
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.1947903125
Short name T192
Test name
Test status
Simulation time 2749121010 ps
CPU time 6.08 seconds
Started Feb 25 12:33:49 PM PST 24
Finished Feb 25 12:33:55 PM PST 24
Peak memory 203728 kb
Host smart-04e4a89a-f316-433f-81a6-91cc93450375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947903125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.1947903125
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.51001740
Short name T81
Test name
Test status
Simulation time 41770855 ps
CPU time 0.64 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203488 kb
Host smart-42e0acf0-a236-4046-a3fe-bab489ab15c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51001740 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.51001740
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1700158776
Short name T220
Test name
Test status
Simulation time 7147721369 ps
CPU time 8.73 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:34:03 PM PST 24
Peak memory 203732 kb
Host smart-b65ef3e1-f649-43fd-aff8-1a97b018a36c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700158776 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1700158776
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.326293578
Short name T197
Test name
Test status
Simulation time 4031277384 ps
CPU time 7.07 seconds
Started Feb 25 12:34:03 PM PST 24
Finished Feb 25 12:34:10 PM PST 24
Peak memory 203740 kb
Host smart-489e223c-e0e1-4d9c-b59e-d561849fbd15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326293578 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.326293578
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.1701440409
Short name T164
Test name
Test status
Simulation time 26503872 ps
CPU time 0.64 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203496 kb
Host smart-93d69c1b-8ed6-4e61-be18-8e64c7d9c023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701440409 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.1701440409
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.3879438580
Short name T24
Test name
Test status
Simulation time 45257993551 ps
CPU time 139.89 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:36:11 PM PST 24
Peak memory 211968 kb
Host smart-868a19df-f3d0-4a26-a37b-93537ed85f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879438580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.3879438580
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2950580693
Short name T172
Test name
Test status
Simulation time 1282962596 ps
CPU time 5.69 seconds
Started Feb 25 12:33:49 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203612 kb
Host smart-831df719-9a4a-49cd-85a7-917fd1a1a9db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950580693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2950580693
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.3142680267
Short name T1
Test name
Test status
Simulation time 1182696060 ps
CPU time 5.13 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:33:55 PM PST 24
Peak memory 203696 kb
Host smart-7481f778-11d9-48e9-af7e-ab1a820a93a8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3142680267 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.3142680267
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3746816477
Short name T209
Test name
Test status
Simulation time 3829422110 ps
CPU time 5.73 seconds
Started Feb 25 12:33:47 PM PST 24
Finished Feb 25 12:33:53 PM PST 24
Peak memory 203744 kb
Host smart-a5e91fd3-fd1e-40ef-b0ce-bfc86dc33166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746816477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3746816477
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.884914277
Short name T141
Test name
Test status
Simulation time 49754306 ps
CPU time 0.67 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203500 kb
Host smart-66f92de5-8bb8-4f88-bd1c-b4bd7fa83ada
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884914277 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.884914277
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_autoincr_sba_tl_access.279174361
Short name T26
Test name
Test status
Simulation time 15787797370 ps
CPU time 42.99 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:34:38 PM PST 24
Peak memory 203724 kb
Host smart-40700b86-6fed-4261-899c-1cebbde53304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279174361 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_autoincr_sba_tl_access.279174361
Directory /workspace/14.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.2954797406
Short name T182
Test name
Test status
Simulation time 1279703381 ps
CPU time 2.28 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:33:58 PM PST 24
Peak memory 203692 kb
Host smart-aa483ec1-3f2f-44c6-bebe-c564bbe93f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954797406 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.2954797406
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.1626378884
Short name T188
Test name
Test status
Simulation time 1307047667 ps
CPU time 3.06 seconds
Started Feb 25 12:34:16 PM PST 24
Finished Feb 25 12:34:20 PM PST 24
Peak memory 203612 kb
Host smart-48e7c8af-b28d-40d8-8c88-e03bbe64d8dc
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1626378884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.1626378884
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.2601428064
Short name T224
Test name
Test status
Simulation time 2168567793 ps
CPU time 7.16 seconds
Started Feb 25 12:33:53 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203640 kb
Host smart-b31688fc-cc50-49de-8695-c420a661fd9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601428064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.2601428064
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1236936194
Short name T149
Test name
Test status
Simulation time 66893524 ps
CPU time 0.61 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203464 kb
Host smart-4141a577-7926-45b9-a535-83f2c95a23c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236936194 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1236936194
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_autoincr_sba_tl_access.2255044654
Short name T25
Test name
Test status
Simulation time 6266354267 ps
CPU time 19.91 seconds
Started Feb 25 12:34:06 PM PST 24
Finished Feb 25 12:34:26 PM PST 24
Peak memory 203808 kb
Host smart-3499aaba-8b7c-4429-8a19-4f0a1cb9540c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255044654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_autoincr_sba_tl_access.2255044654
Directory /workspace/15.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1152099658
Short name T170
Test name
Test status
Simulation time 1063147071 ps
CPU time 3.9 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:09 PM PST 24
Peak memory 203680 kb
Host smart-fabad3ed-c345-4db5-b92e-9517c9e5bc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152099658 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1152099658
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.1540172831
Short name T199
Test name
Test status
Simulation time 8342645427 ps
CPU time 27.47 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:34:19 PM PST 24
Peak memory 203744 kb
Host smart-9c5743dd-c0cf-47e3-9de5-446c5b99d46e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1540172831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.1540172831
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.3003621771
Short name T206
Test name
Test status
Simulation time 1698974369 ps
CPU time 5.35 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203772 kb
Host smart-0b73ef4a-cea7-4c63-9a39-a386349c4c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003621771 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.3003621771
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3598113225
Short name T154
Test name
Test status
Simulation time 47172773 ps
CPU time 0.64 seconds
Started Feb 25 12:34:17 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 203500 kb
Host smart-f37b3718-eedd-4023-856a-e75b1ca2f23c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598113225 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3598113225
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.31175472
Short name T223
Test name
Test status
Simulation time 2944739614 ps
CPU time 5.02 seconds
Started Feb 25 12:34:16 PM PST 24
Finished Feb 25 12:34:22 PM PST 24
Peak memory 203744 kb
Host smart-12ed27a6-e107-4c34-b08b-f8f9cd4af775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31175472 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.31175472
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.3947765982
Short name T175
Test name
Test status
Simulation time 2474971108 ps
CPU time 5.43 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:04 PM PST 24
Peak memory 203720 kb
Host smart-20fc4793-1ba8-4e01-adea-1c68bfd636b4
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3947765982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.3947765982
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2093885640
Short name T196
Test name
Test status
Simulation time 7959385924 ps
CPU time 9.41 seconds
Started Feb 25 12:34:08 PM PST 24
Finished Feb 25 12:34:17 PM PST 24
Peak memory 203780 kb
Host smart-fc5699ff-2aab-40dd-b032-ede35a293e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093885640 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2093885640
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3422983801
Short name T159
Test name
Test status
Simulation time 92152921 ps
CPU time 0.64 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203492 kb
Host smart-75490874-edee-4479-8d0a-8d427692dfd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422983801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3422983801
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_autoincr_sba_tl_access.1808094884
Short name T218
Test name
Test status
Simulation time 7736500850 ps
CPU time 18.92 seconds
Started Feb 25 12:34:14 PM PST 24
Finished Feb 25 12:34:33 PM PST 24
Peak memory 203996 kb
Host smart-1aec78a5-f30c-4544-904e-8d90d35a8f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808094884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_autoincr_sba_tl_access.1808094884
Directory /workspace/17.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1793917738
Short name T190
Test name
Test status
Simulation time 3191236837 ps
CPU time 6.93 seconds
Started Feb 25 12:34:06 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203760 kb
Host smart-86cbc79a-b672-4acf-97fe-231a47b6e6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793917738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1793917738
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.1723030469
Short name T195
Test name
Test status
Simulation time 1774014845 ps
CPU time 4.29 seconds
Started Feb 25 12:34:01 PM PST 24
Finished Feb 25 12:34:05 PM PST 24
Peak memory 203680 kb
Host smart-57144735-fed7-44b9-80e6-29be446c4931
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1723030469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_
tl_access.1723030469
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_stress_all.2074878296
Short name T3
Test name
Test status
Simulation time 4611331656 ps
CPU time 4.63 seconds
Started Feb 25 12:33:53 PM PST 24
Finished Feb 25 12:33:58 PM PST 24
Peak memory 203588 kb
Host smart-98e7ff55-5402-472c-a2b9-78fe843fe7cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074878296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_stress_all.2074878296
Directory /workspace/17.rv_dm_stress_all/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.786353825
Short name T150
Test name
Test status
Simulation time 25177291 ps
CPU time 0.69 seconds
Started Feb 25 12:34:11 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203484 kb
Host smart-8c2cdaeb-eccc-4d27-8b5c-482b1c2c7a94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786353825 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.786353825
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.2315272115
Short name T92
Test name
Test status
Simulation time 894321528 ps
CPU time 1.9 seconds
Started Feb 25 12:34:08 PM PST 24
Finished Feb 25 12:34:10 PM PST 24
Peak memory 203680 kb
Host smart-b1decf5b-5541-438f-90fe-aa645f04dd64
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2315272115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.2315272115
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3039670553
Short name T48
Test name
Test status
Simulation time 1604213405 ps
CPU time 7.25 seconds
Started Feb 25 12:33:54 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203608 kb
Host smart-40550096-4d0f-40d8-9deb-eb4ce0fdaaba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039670553 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3039670553
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1353050751
Short name T156
Test name
Test status
Simulation time 82674832 ps
CPU time 0.64 seconds
Started Feb 25 12:33:58 PM PST 24
Finished Feb 25 12:33:59 PM PST 24
Peak memory 203548 kb
Host smart-990e2ae2-d56e-4117-b565-c96f404dd834
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353050751 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1353050751
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.2544020281
Short name T167
Test name
Test status
Simulation time 739704233 ps
CPU time 1.95 seconds
Started Feb 25 12:34:00 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203648 kb
Host smart-f3fdc64e-96f2-4bcf-8806-83c00edf46fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544020281 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.2544020281
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3515096345
Short name T202
Test name
Test status
Simulation time 1440872803 ps
CPU time 2.36 seconds
Started Feb 25 12:34:11 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203676 kb
Host smart-9fbe0cc8-29c8-4882-9a4c-d8c579bc0c73
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3515096345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3515096345
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.2862362197
Short name T179
Test name
Test status
Simulation time 2030313317 ps
CPU time 4.72 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:04 PM PST 24
Peak memory 203684 kb
Host smart-1e9b80c1-2a3c-4888-9734-17dd2b434961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862362197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.2862362197
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.3026259696
Short name T2
Test name
Test status
Simulation time 53152573 ps
CPU time 0.63 seconds
Started Feb 25 12:33:48 PM PST 24
Finished Feb 25 12:33:49 PM PST 24
Peak memory 203500 kb
Host smart-ba5c52b2-2bf5-488e-8eb5-39893bd2bbef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026259696 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.3026259696
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.171406073
Short name T171
Test name
Test status
Simulation time 7207379562 ps
CPU time 25.5 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:34:04 PM PST 24
Peak memory 203752 kb
Host smart-17310b25-2990-4137-b320-e14b06c1f45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171406073 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.171406073
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.929301349
Short name T219
Test name
Test status
Simulation time 1493259360 ps
CPU time 7.03 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:34:03 PM PST 24
Peak memory 203704 kb
Host smart-6a4d475b-6ab3-4767-baf0-22e6ef306b58
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=929301349 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_tl
_access.929301349
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.71149228
Short name T178
Test name
Test status
Simulation time 65238311 ps
CPU time 0.82 seconds
Started Feb 25 12:33:36 PM PST 24
Finished Feb 25 12:33:37 PM PST 24
Peak memory 203288 kb
Host smart-22c38d19-c0ba-4462-ad4e-cf06958de284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71149228 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.71149228
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4071766529
Short name T204
Test name
Test status
Simulation time 6528606749 ps
CPU time 13.78 seconds
Started Feb 25 12:33:42 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203792 kb
Host smart-d35b0f19-3133-4f31-94f6-7e26c43f31c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071766529 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4071766529
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.2261436003
Short name T38
Test name
Test status
Simulation time 208014361 ps
CPU time 1.16 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 219896 kb
Host smart-7561861b-acb1-427e-835e-3683a3145334
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261436003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.2261436003
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.60510747
Short name T155
Test name
Test status
Simulation time 29326891 ps
CPU time 0.65 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:00 PM PST 24
Peak memory 203504 kb
Host smart-81e7558d-94b7-45dd-a3e2-ae2fc50f886d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60510747 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.60510747
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.478096689
Short name T52
Test name
Test status
Simulation time 24991680 ps
CPU time 0.69 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203548 kb
Host smart-d4b6eafc-fce6-4d0b-ba00-4d6410aaa09d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478096689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.478096689
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.1432716787
Short name T173
Test name
Test status
Simulation time 29702242 ps
CPU time 0.74 seconds
Started Feb 25 12:34:09 PM PST 24
Finished Feb 25 12:34:10 PM PST 24
Peak memory 203500 kb
Host smart-1e4ea904-73b8-4575-8276-6ab1906830bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432716787 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.1432716787
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.263327249
Short name T121
Test name
Test status
Simulation time 31938366 ps
CPU time 0.68 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 203492 kb
Host smart-a9b48092-6909-4fa0-bb3d-08a1495f22bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263327249 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.263327249
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3505494291
Short name T32
Test name
Test status
Simulation time 51712266 ps
CPU time 0.64 seconds
Started Feb 25 12:33:52 PM PST 24
Finished Feb 25 12:33:53 PM PST 24
Peak memory 203368 kb
Host smart-b80e2344-b39b-4360-ab15-b1bb67b28ff5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505494291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3505494291
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1101220734
Short name T187
Test name
Test status
Simulation time 51530047 ps
CPU time 0.65 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:00 PM PST 24
Peak memory 203484 kb
Host smart-80245101-724e-4ef0-936c-bb9ae0d377b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101220734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1101220734
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.3026904335
Short name T186
Test name
Test status
Simulation time 18054355 ps
CPU time 0.66 seconds
Started Feb 25 12:34:08 PM PST 24
Finished Feb 25 12:34:09 PM PST 24
Peak memory 203492 kb
Host smart-a1a1ef38-b7a3-401b-b310-20e308e6efd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026904335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.3026904335
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.1809472846
Short name T135
Test name
Test status
Simulation time 39430011 ps
CPU time 0.64 seconds
Started Feb 25 12:34:21 PM PST 24
Finished Feb 25 12:34:21 PM PST 24
Peak memory 203500 kb
Host smart-9b6cd4a4-a37b-4e03-a6b5-8bf591cd5f99
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809472846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.1809472846
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.3236924425
Short name T49
Test name
Test status
Simulation time 18153396 ps
CPU time 0.69 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203488 kb
Host smart-062240dc-4dba-484c-87f2-14c7adad7e48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236924425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.3236924425
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.488146711
Short name T161
Test name
Test status
Simulation time 33976360 ps
CPU time 0.68 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:39 PM PST 24
Peak memory 203560 kb
Host smart-3090de3c-85b1-4ed6-80e7-e67a58b16e30
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488146711 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.488146711
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.1716809575
Short name T66
Test name
Test status
Simulation time 1281794353 ps
CPU time 3.51 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203744 kb
Host smart-7e3c3c02-cae5-40c6-b024-dac245211cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716809575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.1716809575
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3842243149
Short name T63
Test name
Test status
Simulation time 698592033 ps
CPU time 2.79 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:47 PM PST 24
Peak memory 203452 kb
Host smart-3b4eaa05-c6be-4e5e-ab92-9de990ff46fd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3842243149 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3842243149
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.699032656
Short name T9
Test name
Test status
Simulation time 26875769 ps
CPU time 0.68 seconds
Started Feb 25 12:33:44 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203300 kb
Host smart-f7fd8e2d-dda6-414e-b3bb-b5039ad20835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699032656 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.699032656
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1376976604
Short name T93
Test name
Test status
Simulation time 10975465484 ps
CPU time 32.52 seconds
Started Feb 25 12:33:45 PM PST 24
Finished Feb 25 12:34:23 PM PST 24
Peak memory 203736 kb
Host smart-07ecea74-000a-445b-8c4b-bd3835ab6b46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376976604 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1376976604
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3266028299
Short name T33
Test name
Test status
Simulation time 113120020 ps
CPU time 1.19 seconds
Started Feb 25 12:33:53 PM PST 24
Finished Feb 25 12:33:54 PM PST 24
Peak memory 220016 kb
Host smart-2233379f-278e-4bb2-ac66-ccff816c08c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266028299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3266028299
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.4128394997
Short name T136
Test name
Test status
Simulation time 51268888 ps
CPU time 0.68 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203496 kb
Host smart-510d97d4-9443-45dc-9037-a70dd9624396
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128394997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.4128394997
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/30.rv_dm_stress_all.4100501304
Short name T85
Test name
Test status
Simulation time 5184505932 ps
CPU time 4.97 seconds
Started Feb 25 12:34:05 PM PST 24
Finished Feb 25 12:34:10 PM PST 24
Peak memory 203588 kb
Host smart-d9412117-5d6c-4f91-ad3c-5a3f7b1aef8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100501304 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_stress_all.4100501304
Directory /workspace/30.rv_dm_stress_all/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.1675891499
Short name T139
Test name
Test status
Simulation time 61212399 ps
CPU time 0.66 seconds
Started Feb 25 12:34:02 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203496 kb
Host smart-38303518-f109-442e-8d32-f3177ceb1c43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675891499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.1675891499
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2916685755
Short name T120
Test name
Test status
Simulation time 71651005 ps
CPU time 0.67 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203504 kb
Host smart-c74d0d6f-8f2c-46ad-92b0-6ffb6642c9e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916685755 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2916685755
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.914540083
Short name T151
Test name
Test status
Simulation time 15933422 ps
CPU time 0.64 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:33:55 PM PST 24
Peak memory 203496 kb
Host smart-d9f47145-a5a4-430a-a7a3-b0f8737bac42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914540083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.914540083
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.3011737727
Short name T147
Test name
Test status
Simulation time 24941227 ps
CPU time 0.65 seconds
Started Feb 25 12:34:21 PM PST 24
Finished Feb 25 12:34:22 PM PST 24
Peak memory 203556 kb
Host smart-62535832-eb7a-4853-b554-d45c824c26d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011737727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.3011737727
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1530091444
Short name T19
Test name
Test status
Simulation time 2472128049 ps
CPU time 3.37 seconds
Started Feb 25 12:34:03 PM PST 24
Finished Feb 25 12:34:06 PM PST 24
Peak memory 203644 kb
Host smart-646f88e2-ef21-4a1b-a950-8f09582cd752
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530091444 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1530091444
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.255931344
Short name T184
Test name
Test status
Simulation time 22643303 ps
CPU time 0.61 seconds
Started Feb 25 12:34:15 PM PST 24
Finished Feb 25 12:34:15 PM PST 24
Peak memory 203500 kb
Host smart-cf80603b-c8a9-4ec6-8d4b-57fc50e8f1f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255931344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.255931344
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.1802126939
Short name T35
Test name
Test status
Simulation time 21549331 ps
CPU time 0.7 seconds
Started Feb 25 12:34:15 PM PST 24
Finished Feb 25 12:34:16 PM PST 24
Peak memory 203444 kb
Host smart-ae548558-f843-449d-8750-7c5d58e50c33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802126939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.1802126939
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_stress_all.1734800316
Short name T34
Test name
Test status
Simulation time 1071142105 ps
CPU time 3.89 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203528 kb
Host smart-2c983a8b-169d-4e3a-b27c-a200baca7733
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734800316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_stress_all.1734800316
Directory /workspace/36.rv_dm_stress_all/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.3027139528
Short name T222
Test name
Test status
Simulation time 28113901 ps
CPU time 0.69 seconds
Started Feb 25 12:33:55 PM PST 24
Finished Feb 25 12:33:56 PM PST 24
Peak memory 203528 kb
Host smart-edd0540d-15cc-41e4-82f0-2cd28ef75903
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027139528 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.3027139528
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3603339067
Short name T153
Test name
Test status
Simulation time 48745873 ps
CPU time 0.62 seconds
Started Feb 25 12:34:04 PM PST 24
Finished Feb 25 12:34:05 PM PST 24
Peak memory 203500 kb
Host smart-8198f897-2bcb-47b1-b180-1f4e35f3b4d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603339067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3603339067
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.3304551557
Short name T18
Test name
Test status
Simulation time 3266677186 ps
CPU time 3.42 seconds
Started Feb 25 12:33:45 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203752 kb
Host smart-3d40a764-9dd5-425b-b742-111b84affe9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304551557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.3304551557
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.328482427
Short name T189
Test name
Test status
Simulation time 2583788344 ps
CPU time 6.08 seconds
Started Feb 25 12:33:38 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203808 kb
Host smart-426c12f8-52f6-4598-ad54-67b1c0dd4f44
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328482427 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.328482427
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.1106214182
Short name T216
Test name
Test status
Simulation time 89535921 ps
CPU time 0.7 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203296 kb
Host smart-7bdb85fe-a756-4ef8-aac4-1b679ec19a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106214182 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.1106214182
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4221675498
Short name T211
Test name
Test status
Simulation time 3045518309 ps
CPU time 3.48 seconds
Started Feb 25 12:33:43 PM PST 24
Finished Feb 25 12:33:47 PM PST 24
Peak memory 203792 kb
Host smart-73748739-66ca-496e-9165-62661aaba1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221675498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4221675498
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.2311022642
Short name T62
Test name
Test status
Simulation time 1111568967 ps
CPU time 1.12 seconds
Started Feb 25 12:33:41 PM PST 24
Finished Feb 25 12:33:43 PM PST 24
Peak memory 219880 kb
Host smart-9eb65625-35af-4b64-ac90-66cf67f39016
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311022642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.2311022642
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.1477924134
Short name T138
Test name
Test status
Simulation time 62091822 ps
CPU time 0.64 seconds
Started Feb 25 12:34:16 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 203496 kb
Host smart-ee39c3a7-834c-41a7-8f8c-1ba3dff5ddc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477924134 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.1477924134
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.3953187358
Short name T142
Test name
Test status
Simulation time 55923740 ps
CPU time 0.64 seconds
Started Feb 25 12:34:22 PM PST 24
Finished Feb 25 12:34:23 PM PST 24
Peak memory 203492 kb
Host smart-986525fc-0b7a-4e54-8e86-d0f56b890949
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953187358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.3953187358
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1530868279
Short name T145
Test name
Test status
Simulation time 25789661 ps
CPU time 0.66 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203492 kb
Host smart-016e2982-9f88-49af-9150-03246899f6de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530868279 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1530868279
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1595770961
Short name T198
Test name
Test status
Simulation time 32306097 ps
CPU time 0.64 seconds
Started Feb 25 12:34:06 PM PST 24
Finished Feb 25 12:34:07 PM PST 24
Peak memory 203464 kb
Host smart-01ddf49a-8e8c-4d0a-899e-16e4687c56c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595770961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1595770961
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1119367139
Short name T137
Test name
Test status
Simulation time 61587664 ps
CPU time 0.62 seconds
Started Feb 25 12:33:59 PM PST 24
Finished Feb 25 12:34:00 PM PST 24
Peak memory 203484 kb
Host smart-891cecea-af08-4201-8f4b-58d5c6122a96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119367139 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1119367139
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.2276967794
Short name T53
Test name
Test status
Simulation time 19453278 ps
CPU time 0.72 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203496 kb
Host smart-9b9b2c33-a2a0-4d0a-8ec2-92367b7a986e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276967794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.2276967794
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2662449842
Short name T205
Test name
Test status
Simulation time 86236656 ps
CPU time 0.64 seconds
Started Feb 25 12:34:18 PM PST 24
Finished Feb 25 12:34:22 PM PST 24
Peak memory 203500 kb
Host smart-82bbb9e8-e795-42fa-b70a-9f4a68c64e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662449842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2662449842
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.1541009487
Short name T158
Test name
Test status
Simulation time 84898003 ps
CPU time 0.65 seconds
Started Feb 25 12:34:22 PM PST 24
Finished Feb 25 12:34:23 PM PST 24
Peak memory 203500 kb
Host smart-3bec4e2b-4570-41a5-93dd-1b056100a6c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541009487 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.1541009487
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.2092220495
Short name T203
Test name
Test status
Simulation time 21459056 ps
CPU time 0.71 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:13 PM PST 24
Peak memory 203528 kb
Host smart-ac5f108b-c405-4e0a-aec4-0b5129f3c4fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092220495 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.2092220495
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.3671096319
Short name T177
Test name
Test status
Simulation time 108928303 ps
CPU time 0.67 seconds
Started Feb 25 12:34:16 PM PST 24
Finished Feb 25 12:34:18 PM PST 24
Peak memory 203500 kb
Host smart-ca256a1a-7415-4cf1-bffa-379bbbf2c26f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671096319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.3671096319
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.2214816049
Short name T140
Test name
Test status
Simulation time 35863276 ps
CPU time 0.65 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 203540 kb
Host smart-8ff258d2-791a-4267-9576-515d79883508
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214816049 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.2214816049
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.19627265
Short name T169
Test name
Test status
Simulation time 1401007477 ps
CPU time 5.21 seconds
Started Feb 25 12:33:40 PM PST 24
Finished Feb 25 12:33:45 PM PST 24
Peak memory 203684 kb
Host smart-19ecd8c8-889c-486d-bfec-bae99098f357
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=19627265 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_tl_
access.19627265
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.2611746080
Short name T162
Test name
Test status
Simulation time 8992012702 ps
CPU time 6.38 seconds
Started Feb 25 12:33:47 PM PST 24
Finished Feb 25 12:33:54 PM PST 24
Peak memory 203708 kb
Host smart-fab88519-e53e-4c16-8bb9-ba55cdbf90f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611746080 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.2611746080
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_stress_all.150142211
Short name T7
Test name
Test status
Simulation time 1455221300 ps
CPU time 5.17 seconds
Started Feb 25 12:33:45 PM PST 24
Finished Feb 25 12:33:50 PM PST 24
Peak memory 203580 kb
Host smart-e2e7ab37-b3c9-49d0-8b7b-9a79f4a81041
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150142211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_stress_all.150142211
Directory /workspace/5.rv_dm_stress_all/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.3625065310
Short name T157
Test name
Test status
Simulation time 35800131 ps
CPU time 0.65 seconds
Started Feb 25 12:33:57 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 203484 kb
Host smart-0da74b07-a066-4a18-8624-b839d31a4b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625065310 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.3625065310
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.3166715256
Short name T17
Test name
Test status
Simulation time 931331810 ps
CPU time 2.62 seconds
Started Feb 25 12:33:48 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203620 kb
Host smart-e1d926e0-b8b5-4fc8-9cf8-0460eb7d8544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166715256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.3166715256
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.1674082403
Short name T210
Test name
Test status
Simulation time 4827854346 ps
CPU time 4.45 seconds
Started Feb 25 12:34:21 PM PST 24
Finished Feb 25 12:34:26 PM PST 24
Peak memory 203804 kb
Host smart-c6e0cde0-bb23-46b8-8649-9eef2afad2b6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1674082403 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.1674082403
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.2620459999
Short name T13
Test name
Test status
Simulation time 9877874019 ps
CPU time 7.76 seconds
Started Feb 25 12:33:49 PM PST 24
Finished Feb 25 12:33:57 PM PST 24
Peak memory 203736 kb
Host smart-a8fac945-cbeb-42b6-91d9-1ad49817aec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620459999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.2620459999
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.899348395
Short name T144
Test name
Test status
Simulation time 76446137 ps
CPU time 0.71 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:33:52 PM PST 24
Peak memory 203492 kb
Host smart-bf971965-88b8-464f-ab27-b53feff7d854
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899348395 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.899348395
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_autoincr_sba_tl_access.3767151752
Short name T194
Test name
Test status
Simulation time 49479282910 ps
CPU time 49.99 seconds
Started Feb 25 12:34:02 PM PST 24
Finished Feb 25 12:34:52 PM PST 24
Peak memory 203804 kb
Host smart-3c7b4e60-6a82-4ce5-beff-0289240534cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767151752 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_autoincr_sba_tl_access.3767151752
Directory /workspace/7.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.317610111
Short name T16
Test name
Test status
Simulation time 10137479739 ps
CPU time 13.9 seconds
Started Feb 25 12:34:12 PM PST 24
Finished Feb 25 12:34:26 PM PST 24
Peak memory 203740 kb
Host smart-49bc60d5-2117-4681-8f34-58787b73673d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317610111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.317610111
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.665017556
Short name T163
Test name
Test status
Simulation time 975475072 ps
CPU time 3.56 seconds
Started Feb 25 12:33:50 PM PST 24
Finished Feb 25 12:33:54 PM PST 24
Peak memory 203668 kb
Host smart-2a6ef4d5-d2ae-486c-bccf-d36a37ce9839
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=665017556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.665017556
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.1564359392
Short name T55
Test name
Test status
Simulation time 1640524809 ps
CPU time 7.43 seconds
Started Feb 25 12:33:36 PM PST 24
Finished Feb 25 12:33:44 PM PST 24
Peak memory 203672 kb
Host smart-e4fbc934-070d-47dd-a299-2ef2b0071bb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1564359392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.1564359392
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.2130979097
Short name T214
Test name
Test status
Simulation time 23738248 ps
CPU time 0.69 seconds
Started Feb 25 12:33:34 PM PST 24
Finished Feb 25 12:33:35 PM PST 24
Peak memory 203488 kb
Host smart-a4c5b3df-6e73-488e-ba9f-9ebfac7d1855
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130979097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.2130979097
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.58337007
Short name T10
Test name
Test status
Simulation time 8348303633 ps
CPU time 11.29 seconds
Started Feb 25 12:33:51 PM PST 24
Finished Feb 25 12:34:02 PM PST 24
Peak memory 203804 kb
Host smart-dd5b5675-8183-4d5d-aa9c-b9a85bcc82cb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=58337007 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_tl_
access.58337007
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.3353545122
Short name T181
Test name
Test status
Simulation time 2849131411 ps
CPU time 5.27 seconds
Started Feb 25 12:33:56 PM PST 24
Finished Feb 25 12:34:01 PM PST 24
Peak memory 203736 kb
Host smart-3f7f1a80-4174-42c1-abfd-28433e8e4d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3353545122 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.3353545122
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1136475162
Short name T82
Test name
Test status
Simulation time 33254890 ps
CPU time 0.65 seconds
Started Feb 25 12:33:47 PM PST 24
Finished Feb 25 12:33:48 PM PST 24
Peak memory 203464 kb
Host smart-7a14b0f4-29f5-48c6-9941-ee9d614fd0af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136475162 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1136475162
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.1186024541
Short name T165
Test name
Test status
Simulation time 1316455974 ps
CPU time 2.92 seconds
Started Feb 25 12:33:48 PM PST 24
Finished Feb 25 12:33:51 PM PST 24
Peak memory 203744 kb
Host smart-ea1d06c9-f725-4038-9cb5-26169c706535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186024541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.1186024541
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.1018943834
Short name T176
Test name
Test status
Simulation time 360642588 ps
CPU time 1.45 seconds
Started Feb 25 12:33:44 PM PST 24
Finished Feb 25 12:33:46 PM PST 24
Peak memory 203668 kb
Host smart-effe28b9-f9d6-42d0-bb88-a7a0bd59a391
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1018943834 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.1018943834
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3251189894
Short name T64
Test name
Test status
Simulation time 3851191920 ps
CPU time 11.44 seconds
Started Feb 25 12:33:36 PM PST 24
Finished Feb 25 12:33:47 PM PST 24
Peak memory 203796 kb
Host smart-c4542f74-3b95-4c7c-82c3-ac887deb7905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251189894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3251189894
Directory /workspace/9.rv_dm_sba_tl_access/latest
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