Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.77 92.87 79.06 89.36 76.92 83.07 97.75 95.34


Total test records in report: 363
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html
T125 /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.902279239 Feb 29 12:43:50 PM PST 24 Feb 29 12:44:09 PM PST 24 3492707514 ps
T95 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.607818318 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:41 PM PST 24 139216742 ps
T111 /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4159602586 Feb 29 12:43:39 PM PST 24 Feb 29 12:43:42 PM PST 24 77216032 ps
T270 /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.859371439 Feb 29 12:43:55 PM PST 24 Feb 29 12:43:57 PM PST 24 51120852 ps
T271 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4198805977 Feb 29 12:43:31 PM PST 24 Feb 29 12:44:01 PM PST 24 9272527542 ps
T272 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2962377766 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:35 PM PST 24 93934306 ps
T273 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1996739605 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:58 PM PST 24 179194869 ps
T274 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2689122622 Feb 29 12:43:51 PM PST 24 Feb 29 12:43:52 PM PST 24 188189636 ps
T112 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2410877222 Feb 29 12:43:55 PM PST 24 Feb 29 12:44:01 PM PST 24 440641652 ps
T102 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.490698659 Feb 29 12:43:55 PM PST 24 Feb 29 12:45:09 PM PST 24 7248196814 ps
T275 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.633537514 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:06 PM PST 24 1713149136 ps
T276 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3859562148 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:10 PM PST 24 178318080 ps
T277 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2691798539 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:08 PM PST 24 1119169969 ps
T278 /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1575098135 Feb 29 12:44:02 PM PST 24 Feb 29 12:44:16 PM PST 24 8355637837 ps
T279 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1304206266 Feb 29 12:43:26 PM PST 24 Feb 29 12:43:27 PM PST 24 125599339 ps
T280 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.978726117 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:39 PM PST 24 849414595 ps
T281 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4006756466 Feb 29 12:43:49 PM PST 24 Feb 29 12:43:52 PM PST 24 1538479977 ps
T126 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1217939291 Feb 29 12:43:51 PM PST 24 Feb 29 12:44:10 PM PST 24 1225839423 ps
T282 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4150246584 Feb 29 12:43:38 PM PST 24 Feb 29 12:43:46 PM PST 24 2802281880 ps
T283 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3162703346 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:28 PM PST 24 96280668 ps
T284 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.317837440 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:54 PM PST 24 61498856 ps
T285 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2855340210 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:54 PM PST 24 54055838 ps
T286 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.124594560 Feb 29 12:43:43 PM PST 24 Feb 29 12:43:44 PM PST 24 46746941 ps
T129 /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4242265861 Feb 29 12:43:40 PM PST 24 Feb 29 12:44:00 PM PST 24 1102536922 ps
T287 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3769222126 Feb 29 12:44:04 PM PST 24 Feb 29 12:44:10 PM PST 24 49002505 ps
T288 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2115263534 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:38 PM PST 24 95940436 ps
T289 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1054367833 Feb 29 12:44:10 PM PST 24 Feb 29 12:44:11 PM PST 24 711795095 ps
T290 /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2420352366 Feb 29 12:43:30 PM PST 24 Feb 29 12:43:32 PM PST 24 78352216 ps
T103 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3346231315 Feb 29 12:43:47 PM PST 24 Feb 29 12:43:50 PM PST 24 2062202679 ps
T291 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3810089155 Feb 29 12:43:44 PM PST 24 Feb 29 12:44:07 PM PST 24 7277317094 ps
T292 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2928774743 Feb 29 12:43:51 PM PST 24 Feb 29 12:43:55 PM PST 24 249333949 ps
T293 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3565838813 Feb 29 12:43:59 PM PST 24 Feb 29 12:44:01 PM PST 24 834071968 ps
T294 /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1348356172 Feb 29 12:43:51 PM PST 24 Feb 29 12:44:02 PM PST 24 4275885519 ps
T295 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3693212370 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:38 PM PST 24 64036851 ps
T296 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.799755789 Feb 29 12:43:35 PM PST 24 Feb 29 12:43:41 PM PST 24 68662947 ps
T297 /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2637784634 Feb 29 12:43:52 PM PST 24 Feb 29 12:43:55 PM PST 24 1848889669 ps
T298 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1776208698 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:14 PM PST 24 225392973 ps
T299 /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2484656647 Feb 29 12:43:41 PM PST 24 Feb 29 12:44:51 PM PST 24 19384733909 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.65053118 Feb 29 12:43:46 PM PST 24 Feb 29 12:43:47 PM PST 24 15215500 ps
T301 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3241428061 Feb 29 12:43:57 PM PST 24 Feb 29 12:43:58 PM PST 24 307501802 ps
T104 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4122277918 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:37 PM PST 24 250851404 ps
T302 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1791240481 Feb 29 12:43:32 PM PST 24 Feb 29 12:43:33 PM PST 24 31738059 ps
T303 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1106332624 Feb 29 12:43:33 PM PST 24 Feb 29 12:43:35 PM PST 24 94162458 ps
T304 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3068953705 Feb 29 12:43:23 PM PST 24 Feb 29 12:43:25 PM PST 24 114808185 ps
T305 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3529224102 Feb 29 12:43:36 PM PST 24 Feb 29 12:43:41 PM PST 24 746490000 ps
T306 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2796602695 Feb 29 12:43:57 PM PST 24 Feb 29 12:44:11 PM PST 24 12884688776 ps
T307 /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2551291898 Feb 29 12:43:53 PM PST 24 Feb 29 12:43:58 PM PST 24 19333064 ps
T92 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.643676786 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:37 PM PST 24 1226340443 ps
T308 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3588093311 Feb 29 12:43:27 PM PST 24 Feb 29 12:43:54 PM PST 24 2345947584 ps
T309 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4047133101 Feb 29 12:43:43 PM PST 24 Feb 29 12:43:48 PM PST 24 841364025 ps
T310 /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4130672836 Feb 29 12:43:56 PM PST 24 Feb 29 12:44:15 PM PST 24 2050000533 ps
T311 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2033484161 Feb 29 12:43:31 PM PST 24 Feb 29 12:43:32 PM PST 24 139626596 ps
T93 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3264949161 Feb 29 12:43:41 PM PST 24 Feb 29 12:43:44 PM PST 24 356123407 ps
T312 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3202349714 Feb 29 12:43:46 PM PST 24 Feb 29 12:43:50 PM PST 24 168134980 ps
T113 /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.430163062 Feb 29 12:43:38 PM PST 24 Feb 29 12:43:45 PM PST 24 396124846 ps
T313 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1705236461 Feb 29 12:44:18 PM PST 24 Feb 29 12:44:20 PM PST 24 359951009 ps
T96 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2432214887 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:12 PM PST 24 282276835 ps
T127 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3679784389 Feb 29 12:43:41 PM PST 24 Feb 29 12:43:52 PM PST 24 1035742624 ps
T314 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3736048450 Feb 29 12:43:33 PM PST 24 Feb 29 12:43:35 PM PST 24 832147836 ps
T315 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.90517992 Feb 29 12:43:48 PM PST 24 Feb 29 12:43:51 PM PST 24 103476605 ps
T316 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1228319397 Feb 29 12:43:40 PM PST 24 Feb 29 12:43:41 PM PST 24 295776232 ps
T317 /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2582696293 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:14 PM PST 24 52213724 ps
T318 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.525679144 Feb 29 12:43:47 PM PST 24 Feb 29 12:43:49 PM PST 24 343276090 ps
T319 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2182249036 Feb 29 12:43:31 PM PST 24 Feb 29 12:44:27 PM PST 24 2792067949 ps
T320 /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2793490218 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:30 PM PST 24 78048635 ps
T321 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4096210284 Feb 29 12:43:54 PM PST 24 Feb 29 12:43:56 PM PST 24 87986160 ps
T322 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1850035840 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:45 PM PST 24 4647192515 ps
T323 /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4156329013 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:11 PM PST 24 972309079 ps
T324 /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1601318537 Feb 29 12:43:51 PM PST 24 Feb 29 12:43:59 PM PST 24 1057946767 ps
T325 /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.4235835913 Feb 29 12:43:36 PM PST 24 Feb 29 12:43:59 PM PST 24 6606245695 ps
T326 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.957775203 Feb 29 12:43:54 PM PST 24 Feb 29 12:44:36 PM PST 24 11429197278 ps
T327 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.589484637 Feb 29 12:44:09 PM PST 24 Feb 29 12:44:14 PM PST 24 218512946 ps
T97 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1680544357 Feb 29 12:43:43 PM PST 24 Feb 29 12:43:50 PM PST 24 1351134895 ps
T328 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3296526872 Feb 29 12:43:46 PM PST 24 Feb 29 12:43:50 PM PST 24 337339136 ps
T329 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.770620291 Feb 29 12:43:32 PM PST 24 Feb 29 12:43:38 PM PST 24 103273146 ps
T330 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.943296022 Feb 29 12:44:00 PM PST 24 Feb 29 12:44:03 PM PST 24 2328554889 ps
T331 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3038690776 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:08 PM PST 24 297575883 ps
T332 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1964536840 Feb 29 12:43:54 PM PST 24 Feb 29 12:44:04 PM PST 24 968108748 ps
T333 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3240794176 Feb 29 12:43:56 PM PST 24 Feb 29 12:44:00 PM PST 24 492928721 ps
T334 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3816403394 Feb 29 12:44:03 PM PST 24 Feb 29 12:44:04 PM PST 24 41939811 ps
T335 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.79029310 Feb 29 12:44:11 PM PST 24 Feb 29 12:44:25 PM PST 24 6492727370 ps
T336 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3768163859 Feb 29 12:43:56 PM PST 24 Feb 29 12:44:00 PM PST 24 297986301 ps
T337 /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2676453266 Feb 29 12:43:54 PM PST 24 Feb 29 12:44:16 PM PST 24 6350355854 ps
T338 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.914450785 Feb 29 12:43:57 PM PST 24 Feb 29 12:44:07 PM PST 24 1649204780 ps
T98 /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.49791949 Feb 29 12:44:08 PM PST 24 Feb 29 12:44:12 PM PST 24 150253658 ps
T339 /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2877774231 Feb 29 12:43:54 PM PST 24 Feb 29 12:43:56 PM PST 24 44341508 ps
T340 /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2818918314 Feb 29 12:43:36 PM PST 24 Feb 29 12:43:38 PM PST 24 109904995 ps
T341 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2880332533 Feb 29 12:43:39 PM PST 24 Feb 29 12:43:40 PM PST 24 144975640 ps
T342 /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2759609132 Feb 29 12:43:54 PM PST 24 Feb 29 12:44:00 PM PST 24 101857984 ps
T343 /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2563747634 Feb 29 12:43:31 PM PST 24 Feb 29 12:43:32 PM PST 24 164309201 ps
T99 /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1353693589 Feb 29 12:43:37 PM PST 24 Feb 29 12:43:40 PM PST 24 301494833 ps
T344 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.264135931 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:09 PM PST 24 1096687819 ps
T345 /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3002495950 Feb 29 12:43:45 PM PST 24 Feb 29 12:43:59 PM PST 24 20198237990 ps
T346 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1506607823 Feb 29 12:43:42 PM PST 24 Feb 29 12:43:43 PM PST 24 718359788 ps
T347 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3704442882 Feb 29 12:43:35 PM PST 24 Feb 29 12:43:36 PM PST 24 188707574 ps
T128 /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3134180539 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:17 PM PST 24 566213235 ps
T348 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2591969236 Feb 29 12:43:53 PM PST 24 Feb 29 12:44:00 PM PST 24 656154088 ps
T349 /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.915642966 Feb 29 12:43:33 PM PST 24 Feb 29 12:44:01 PM PST 24 739378798 ps
T350 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3569098788 Feb 29 12:43:44 PM PST 24 Feb 29 12:44:38 PM PST 24 13229472892 ps
T351 /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1979089209 Feb 29 12:43:38 PM PST 24 Feb 29 12:43:41 PM PST 24 939738784 ps
T352 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1809159213 Feb 29 12:43:28 PM PST 24 Feb 29 12:43:30 PM PST 24 680006937 ps
T353 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3168603284 Feb 29 12:43:33 PM PST 24 Feb 29 12:43:35 PM PST 24 106558399 ps
T354 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3459093187 Feb 29 12:44:01 PM PST 24 Feb 29 12:44:04 PM PST 24 241752864 ps
T355 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2319929418 Feb 29 12:44:05 PM PST 24 Feb 29 12:44:08 PM PST 24 31009251 ps
T131 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1906335356 Feb 29 12:43:35 PM PST 24 Feb 29 12:43:46 PM PST 24 1538649307 ps
T356 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4036417738 Feb 29 12:43:32 PM PST 24 Feb 29 12:43:33 PM PST 24 37287635 ps
T357 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2934083688 Feb 29 12:43:36 PM PST 24 Feb 29 12:43:37 PM PST 24 56495555 ps
T358 /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2453839644 Feb 29 12:43:53 PM PST 24 Feb 29 12:45:00 PM PST 24 2294992642 ps
T359 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1100970403 Feb 29 12:43:34 PM PST 24 Feb 29 12:43:38 PM PST 24 473253269 ps
T360 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3323218602 Feb 29 12:43:29 PM PST 24 Feb 29 12:43:29 PM PST 24 119863843 ps
T361 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2370834984 Feb 29 12:43:58 PM PST 24 Feb 29 12:43:59 PM PST 24 324659833 ps
T362 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3795668234 Feb 29 12:43:36 PM PST 24 Feb 29 12:44:20 PM PST 24 30152805358 ps
T363 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.513088027 Feb 29 12:43:59 PM PST 24 Feb 29 12:44:25 PM PST 24 14737877386 ps

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.292511512
Short name T9
Test name
Test status
Simulation time 22829635989 ps
CPU time 45.44 seconds
Started Feb 29 12:45:20 PM PST 24
Finished Feb 29 12:46:06 PM PST 24
Peak memory 204156 kb
Host smart-b6df30dd-1063-4762-b134-b9737bfd6466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292511512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.292511512
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.110567170
Short name T43
Test name
Test status
Simulation time 1340192358 ps
CPU time 15.77 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 212112 kb
Host smart-c798d0cb-4bdd-4efc-890c-6fc47b6f508c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110567170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.110567170
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3647488878
Short name T6
Test name
Test status
Simulation time 2497224936 ps
CPU time 5.77 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 204088 kb
Host smart-ae392975-25ee-4845-b1d2-29b6012291e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647488878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3647488878
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.265226918
Short name T37
Test name
Test status
Simulation time 39576344 ps
CPU time 0.68 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 203724 kb
Host smart-7371a81d-15ac-4306-b685-5e5805fd87d4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265226918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.265226918
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.875356071
Short name T46
Test name
Test status
Simulation time 172647754 ps
CPU time 4.05 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 203728 kb
Host smart-c0c59a63-8ebb-495c-afb7-51afeec0f9f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875356071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.875356071
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.4123353939
Short name T25
Test name
Test status
Simulation time 2465198483 ps
CPU time 3.38 seconds
Started Feb 29 12:45:07 PM PST 24
Finished Feb 29 12:45:10 PM PST 24
Peak memory 204072 kb
Host smart-826a8941-e50e-4130-91f2-fb8bf8cb4967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123353939 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.4123353939
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/34.rv_dm_stress_all.1578733115
Short name T65
Test name
Test status
Simulation time 5363409691 ps
CPU time 5.43 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203928 kb
Host smart-69de8019-a16a-4a8f-bf8f-6792ac6da995
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578733115 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_stress_all.1578733115
Directory /workspace/34.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.3854714484
Short name T64
Test name
Test status
Simulation time 452335518 ps
CPU time 2.13 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 203864 kb
Host smart-370e671f-c761-4319-8580-ccd04444eece
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854714484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.3854714484
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.2762913698
Short name T14
Test name
Test status
Simulation time 2857974480 ps
CPU time 8.8 seconds
Started Feb 29 12:44:40 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 204132 kb
Host smart-4e9a5b4a-3702-4c74-8866-68b86711fca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762913698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.2762913698
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.2837457055
Short name T77
Test name
Test status
Simulation time 412728891 ps
CPU time 5.21 seconds
Started Feb 29 12:43:50 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 211952 kb
Host smart-baa04e50-f25f-48a5-bbcb-3236cc0ed3e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837457055 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.2837457055
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.631504418
Short name T58
Test name
Test status
Simulation time 107734692 ps
CPU time 2.41 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 211940 kb
Host smart-23b9f949-a2ba-46a4-9411-0634355eda6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631504418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.631504418
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.902279239
Short name T125
Test name
Test status
Simulation time 3492707514 ps
CPU time 18.48 seconds
Started Feb 29 12:43:50 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 215168 kb
Host smart-ff6ff1bf-2038-4c04-a728-ef00388876ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902279239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.902279239
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.3271659844
Short name T30
Test name
Test status
Simulation time 19666867 ps
CPU time 0.79 seconds
Started Feb 29 12:44:50 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 203776 kb
Host smart-e7fcebca-40cf-4d1f-9c65-b00bb169c5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271659844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.3271659844
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.2806885236
Short name T41
Test name
Test status
Simulation time 348843575 ps
CPU time 1.26 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 218608 kb
Host smart-9ecfeb94-a370-40f1-b754-2d1538ec30ab
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806885236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.2806885236
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.27115581
Short name T4
Test name
Test status
Simulation time 546903244 ps
CPU time 1.77 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 203776 kb
Host smart-480b0cc8-c541-440f-8140-a2b3803e608c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27115581 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.27115581
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.4283637543
Short name T62
Test name
Test status
Simulation time 7393814672 ps
CPU time 12.74 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 215800 kb
Host smart-0b0f867e-8473-4ba9-b4ab-5607c57b1ee2
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283637543 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.4283637543
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.3900223759
Short name T13
Test name
Test status
Simulation time 58276490 ps
CPU time 0.89 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:44:50 PM PST 24
Peak memory 203740 kb
Host smart-0c96ecb0-d501-4769-9da7-6cce9063a366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900223759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.3900223759
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.3679784389
Short name T127
Test name
Test status
Simulation time 1035742624 ps
CPU time 10.46 seconds
Started Feb 29 12:43:41 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 212068 kb
Host smart-e00b5826-34c1-4d3b-a768-b2fbd3149353
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3679784389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.3679784389
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.607818318
Short name T95
Test name
Test status
Simulation time 139216742 ps
CPU time 5.89 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 203612 kb
Host smart-784a9f3b-c790-423c-8833-3fee0990dc8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607818318 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same_
csr_outstanding.607818318
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.4056792657
Short name T184
Test name
Test status
Simulation time 2030649005 ps
CPU time 9.71 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:28 PM PST 24
Peak memory 203732 kb
Host smart-a9620f2e-893f-42f3-90f2-82cfeb5c7d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056792657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.4056792657
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.339578132
Short name T71
Test name
Test status
Simulation time 87761613 ps
CPU time 0.9 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:34 PM PST 24
Peak memory 203796 kb
Host smart-5abd418e-2c58-4962-b579-36220360a414
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339578132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_aliasing.339578132
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.2437572942
Short name T117
Test name
Test status
Simulation time 26993384 ps
CPU time 0.64 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 203756 kb
Host smart-819ddf18-a2f1-4330-a1a6-8cf88e78da41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437572942 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.2437572942
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.1184203883
Short name T130
Test name
Test status
Simulation time 2080806020 ps
CPU time 9.58 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 212448 kb
Host smart-04f1328b-3685-4ffa-8e54-9df781d955a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184203883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.1
184203883
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.2295270517
Short name T91
Test name
Test status
Simulation time 1518165342 ps
CPU time 2.48 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 203700 kb
Host smart-b4aa3e5e-18a7-47d9-8183-e69c27bcb068
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2295270517 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.2295270517
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.743030861
Short name T26
Test name
Test status
Simulation time 130924042 ps
CPU time 1.06 seconds
Started Feb 29 12:45:02 PM PST 24
Finished Feb 29 12:45:03 PM PST 24
Peak memory 203608 kb
Host smart-f0f195f1-e4fb-4a9c-975d-5d84b39ff35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743030861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.743030861
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/39.rv_dm_stress_all.732537024
Short name T28
Test name
Test status
Simulation time 8873588712 ps
CPU time 4.01 seconds
Started Feb 29 12:45:37 PM PST 24
Finished Feb 29 12:45:41 PM PST 24
Peak memory 204060 kb
Host smart-82103aff-0878-45a5-a5bf-9373352de203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732537024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_stress_all.732537024
Directory /workspace/39.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1864568936
Short name T245
Test name
Test status
Simulation time 6711520145 ps
CPU time 30.6 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:44:02 PM PST 24
Peak memory 203900 kb
Host smart-1b448178-60ab-4564-bd5a-5da73f6e37c3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864568936 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1864568936
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.2182249036
Short name T319
Test name
Test status
Simulation time 2792067949 ps
CPU time 55.59 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 203860 kb
Host smart-038f6fb5-58d2-49ae-beb2-f1a0339e168a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182249036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.2182249036
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.1694984387
Short name T100
Test name
Test status
Simulation time 253610385 ps
CPU time 1.56 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 203724 kb
Host smart-26c42881-1cea-4215-bec0-5c692f8ac69e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694984387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.1694984387
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.2420352366
Short name T290
Test name
Test status
Simulation time 78352216 ps
CPU time 2.01 seconds
Started Feb 29 12:43:30 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 211976 kb
Host smart-8b77cd4c-83ef-4121-8f29-9748e97ddf43
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420352366 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.2420352366
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.2855806369
Short name T59
Test name
Test status
Simulation time 334744108 ps
CPU time 2.18 seconds
Started Feb 29 12:43:21 PM PST 24
Finished Feb 29 12:43:23 PM PST 24
Peak memory 203812 kb
Host smart-69bba9ad-7bd7-4581-84c2-426ccbaa7595
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855806369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.2855806369
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.621386566
Short name T246
Test name
Test status
Simulation time 15908050934 ps
CPU time 10.58 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:45 PM PST 24
Peak memory 203708 kb
Host smart-b88ba0ce-402d-4779-8c9f-06df2f8b7b99
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=621386566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr
_aliasing.621386566
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.3704442882
Short name T347
Test name
Test status
Simulation time 188707574 ps
CPU time 0.92 seconds
Started Feb 29 12:43:35 PM PST 24
Finished Feb 29 12:43:36 PM PST 24
Peak memory 203568 kb
Host smart-d4a988ec-5725-4f97-895c-36abb616be47
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704442882 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.3
704442882
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.850455401
Short name T255
Test name
Test status
Simulation time 89855478 ps
CPU time 0.84 seconds
Started Feb 29 12:43:39 PM PST 24
Finished Feb 29 12:43:40 PM PST 24
Peak memory 203464 kb
Host smart-48ff43a8-4cb1-4745-99ca-6adad7f47251
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850455401 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr
_aliasing.850455401
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.1506607823
Short name T346
Test name
Test status
Simulation time 718359788 ps
CPU time 1.62 seconds
Started Feb 29 12:43:42 PM PST 24
Finished Feb 29 12:43:43 PM PST 24
Peak memory 203568 kb
Host smart-bc91794b-7b30-4a81-b773-ce4c1b092c4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506607823 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.1506607823
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.3162703346
Short name T283
Test name
Test status
Simulation time 96280668 ps
CPU time 0.73 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:28 PM PST 24
Peak memory 203588 kb
Host smart-7ce23943-6934-45d8-a3de-92ee647a6627
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162703346 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.3162703346
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3693212370
Short name T295
Test name
Test status
Simulation time 64036851 ps
CPU time 0.82 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 203572 kb
Host smart-b7687128-4819-4a3f-8d14-ec9c8436bb63
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693212370 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
693212370
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.2793490218
Short name T320
Test name
Test status
Simulation time 78048635 ps
CPU time 0.62 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 203560 kb
Host smart-daf03d0d-259d-4ffc-b230-6ec4266d1807
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793490218 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.2793490218
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.65053118
Short name T300
Test name
Test status
Simulation time 15215500 ps
CPU time 0.64 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:47 PM PST 24
Peak memory 203416 kb
Host smart-133e151f-369e-44a4-a25c-87fff73888ec
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65053118 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.65053118
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.1353693589
Short name T99
Test name
Test status
Simulation time 301494833 ps
CPU time 3.46 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:40 PM PST 24
Peak memory 203816 kb
Host smart-ff3f8b65-36c5-4923-a818-9a05ed3f56eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353693589 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.1353693589
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.4053705898
Short name T120
Test name
Test status
Simulation time 1657635491 ps
CPU time 9.96 seconds
Started Feb 29 12:43:47 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 211964 kb
Host smart-7b863dce-52b5-49c5-8e60-56e8f20c3aa0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053705898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.4053705898
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3588093311
Short name T308
Test name
Test status
Simulation time 2345947584 ps
CPU time 26.81 seconds
Started Feb 29 12:43:27 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 203924 kb
Host smart-bbc2b833-aaf8-48c3-b337-3bc5399c2149
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588093311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3588093311
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.2484656647
Short name T299
Test name
Test status
Simulation time 19384733909 ps
CPU time 69.94 seconds
Started Feb 29 12:43:41 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 203816 kb
Host smart-f5affd62-9307-4e14-afea-22c58d24bf0b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484656647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.2484656647
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.3068953705
Short name T304
Test name
Test status
Simulation time 114808185 ps
CPU time 2.44 seconds
Started Feb 29 12:43:23 PM PST 24
Finished Feb 29 12:43:25 PM PST 24
Peak memory 203760 kb
Host smart-8ae6d746-74bd-47f5-b502-5c842112011c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068953705 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.3068953705
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.3177904988
Short name T268
Test name
Test status
Simulation time 3329068502 ps
CPU time 2.61 seconds
Started Feb 29 12:43:47 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 212060 kb
Host smart-1c5e99d0-6e6b-42c3-9f28-d3ecc2724a48
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177904988 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.3177904988
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.2628454170
Short name T256
Test name
Test status
Simulation time 43187676 ps
CPU time 2.09 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 211872 kb
Host smart-a8369066-1526-408e-813d-0cc2080ba3a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628454170 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.2628454170
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.4198805977
Short name T271
Test name
Test status
Simulation time 9272527542 ps
CPU time 29.95 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203760 kb
Host smart-1ae28220-2f94-4072-bf71-15f6110eea48
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198805977 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.4198805977
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3810089155
Short name T291
Test name
Test status
Simulation time 7277317094 ps
CPU time 22.28 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:44:07 PM PST 24
Peak memory 203816 kb
Host smart-fdc61985-3b88-4553-8463-980741109e61
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810089155 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3810089155
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.3264949161
Short name T93
Test name
Test status
Simulation time 356123407 ps
CPU time 2.03 seconds
Started Feb 29 12:43:41 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 203700 kb
Host smart-8fb0ad7b-387f-4241-80e0-b093db62f57c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264949161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.3264949161
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.3719222868
Short name T233
Test name
Test status
Simulation time 273015574 ps
CPU time 1.42 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 203732 kb
Host smart-16133062-e3ec-4b31-a485-3a57605fd2ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719222868 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.3
719222868
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.3072868796
Short name T234
Test name
Test status
Simulation time 4352922544 ps
CPU time 9.1 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:43 PM PST 24
Peak memory 204008 kb
Host smart-5db9730f-baa7-4837-a2e7-2f183cc4e752
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072868796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_bit_bash.3072868796
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.124594560
Short name T286
Test name
Test status
Simulation time 46746941 ps
CPU time 0.73 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 203588 kb
Host smart-6846ef38-2534-4468-a941-11b2fc0d133b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124594560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_hw_reset.124594560
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.2130310145
Short name T250
Test name
Test status
Simulation time 53151085 ps
CPU time 0.66 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 203604 kb
Host smart-207f2a90-8bf3-4f32-ab2f-f00c3d9318ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130310145 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.2
130310145
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2551291898
Short name T307
Test name
Test status
Simulation time 19333064 ps
CPU time 0.68 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 203488 kb
Host smart-4e6c8051-81b4-4d04-a3ad-5afa98b28d98
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551291898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2551291898
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.4036417738
Short name T356
Test name
Test status
Simulation time 37287635 ps
CPU time 0.62 seconds
Started Feb 29 12:43:32 PM PST 24
Finished Feb 29 12:43:33 PM PST 24
Peak memory 203556 kb
Host smart-d5e2ecc0-cb66-45b8-b788-c9d8bcefade9
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036417738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.4036417738
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4159602586
Short name T111
Test name
Test status
Simulation time 77216032 ps
CPU time 3.25 seconds
Started Feb 29 12:43:39 PM PST 24
Finished Feb 29 12:43:42 PM PST 24
Peak memory 203720 kb
Host smart-c91fe81a-3ad1-4e97-ae32-30fcdaf29835
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159602586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4159602586
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3241678048
Short name T132
Test name
Test status
Simulation time 15942688610 ps
CPU time 12.45 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 212084 kb
Host smart-9bc69bf7-a54e-428f-b41f-f2263cc6ffe8
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241678048 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3241678048
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.630334568
Short name T75
Test name
Test status
Simulation time 64514818 ps
CPU time 2.73 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 212276 kb
Host smart-449a28f0-3de0-47eb-ac90-f0ec89c84c0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630334568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.630334568
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.347477814
Short name T124
Test name
Test status
Simulation time 4691707083 ps
CPU time 18.88 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 216172 kb
Host smart-c3f9f286-2150-4483-a27b-4e2822a0cd78
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347477814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.347477814
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.1312665461
Short name T60
Test name
Test status
Simulation time 1671813006 ps
CPU time 2.51 seconds
Started Feb 29 12:43:58 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 211948 kb
Host smart-4b6c4367-16a9-4d15-89d2-70b1704364fd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312665461 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.1312665461
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.2758545296
Short name T82
Test name
Test status
Simulation time 246138152 ps
CPU time 1.51 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 203712 kb
Host smart-cdf48dc5-08b0-4e51-858c-df8cfc99c4e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758545296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.2758545296
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.3063206048
Short name T242
Test name
Test status
Simulation time 427686770 ps
CPU time 0.97 seconds
Started Feb 29 12:43:35 PM PST 24
Finished Feb 29 12:43:36 PM PST 24
Peak memory 203556 kb
Host smart-e18ce506-fb43-4530-aaee-0a91033b4c9f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063206048 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.
3063206048
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.1105613777
Short name T248
Test name
Test status
Simulation time 36319544 ps
CPU time 0.68 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 203468 kb
Host smart-2a1108a0-febd-4920-b266-1d031b84ef8d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1105613777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.
1105613777
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.430163062
Short name T113
Test name
Test status
Simulation time 396124846 ps
CPU time 6.76 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:45 PM PST 24
Peak memory 203696 kb
Host smart-866ee377-2d56-4338-9d6f-76a64f223069
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430163062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same_
csr_outstanding.430163062
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tap_fsm_rand_reset.4235835913
Short name T325
Test name
Test status
Simulation time 6606245695 ps
CPU time 22.38 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 220280 kb
Host smart-6f3dfb00-4f44-4d4a-bbd0-eafd7f7ae172
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235835913 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rv_dm_tap_fsm_rand_reset.4235835913
Directory /workspace/10.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.1996739605
Short name T273
Test name
Test status
Simulation time 179194869 ps
CPU time 4.32 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 211956 kb
Host smart-2e5a71c6-1c91-424d-bcb7-1ee508854b60
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996739605 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.1996739605
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.3240794176
Short name T333
Test name
Test status
Simulation time 492928721 ps
CPU time 3.37 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 220176 kb
Host smart-ffe9dfd1-6819-4e17-ab10-f42144b38dc5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240794176 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.3240794176
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.4156329013
Short name T323
Test name
Test status
Simulation time 972309079 ps
CPU time 1.66 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 203740 kb
Host smart-19a24bf0-d39e-4e9e-9d58-ce7ae3815612
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156329013 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.4156329013
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.1054367833
Short name T289
Test name
Test status
Simulation time 711795095 ps
CPU time 1.05 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 203620 kb
Host smart-c735f9a8-07c1-4df7-8941-c8bea0bb0b0e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054367833 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
1054367833
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.1684700109
Short name T235
Test name
Test status
Simulation time 77116082 ps
CPU time 0.64 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:47 PM PST 24
Peak memory 203616 kb
Host smart-b9c8abc4-56e0-4582-918d-3ac68f1c0817
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684700109 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
1684700109
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.2047718564
Short name T109
Test name
Test status
Simulation time 1834938080 ps
CPU time 7.86 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 203752 kb
Host smart-166b5cfd-a1af-411f-80f0-109da2a1233d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047718564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same
_csr_outstanding.2047718564
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.90517992
Short name T315
Test name
Test status
Simulation time 103476605 ps
CPU time 2.69 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 203768 kb
Host smart-77112c23-5e8f-49f7-8fe2-d8ea31beacd4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90517992 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.90517992
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.1145567262
Short name T44
Test name
Test status
Simulation time 406559453 ps
CPU time 15.46 seconds
Started Feb 29 12:44:03 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 211976 kb
Host smart-0389540d-7caf-46cc-b1f1-58641301f991
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145567262 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.1
145567262
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.1979089209
Short name T351
Test name
Test status
Simulation time 939738784 ps
CPU time 2.29 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 211996 kb
Host smart-b5fe80c2-9e1d-4537-a7ab-ba4d7327f30d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979089209 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.1979089209
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.3168603284
Short name T353
Test name
Test status
Simulation time 106558399 ps
CPU time 1.47 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203732 kb
Host smart-2ba5750c-37ac-4b35-8403-3ec363c4e37e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168603284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.3168603284
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.525679144
Short name T318
Test name
Test status
Simulation time 343276090 ps
CPU time 1.6 seconds
Started Feb 29 12:43:47 PM PST 24
Finished Feb 29 12:43:49 PM PST 24
Peak memory 203656 kb
Host smart-0c261162-d845-4382-ab92-8a8a99736af5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525679144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.525679144
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.3859562148
Short name T276
Test name
Test status
Simulation time 178318080 ps
CPU time 0.78 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 203520 kb
Host smart-cb3bb5c8-36de-461d-a1d9-c6bc3581d1d2
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859562148 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.
3859562148
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.3283313376
Short name T108
Test name
Test status
Simulation time 294593097 ps
CPU time 6.35 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 203776 kb
Host smart-f9b3d5c8-725a-46cc-b38e-57e7696e7119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283313376 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.3283313376
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.589484637
Short name T327
Test name
Test status
Simulation time 218512946 ps
CPU time 4.64 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 211936 kb
Host smart-e9cc9bf4-e105-45da-a041-69abfa47368c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589484637 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.589484637
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.914450785
Short name T338
Test name
Test status
Simulation time 1649204780 ps
CPU time 9.43 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:44:07 PM PST 24
Peak memory 211948 kb
Host smart-fb1483f7-32ad-436c-acfb-1ed24941eb64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914450785 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.914450785
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.1348356172
Short name T294
Test name
Test status
Simulation time 4275885519 ps
CPU time 10.37 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:44:02 PM PST 24
Peak memory 217072 kb
Host smart-5f29c641-08f5-4ff2-976e-a4a9fdf55364
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348356172 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.1348356172
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.859371439
Short name T270
Test name
Test status
Simulation time 51120852 ps
CPU time 1.49 seconds
Started Feb 29 12:43:55 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 203732 kb
Host smart-1867b475-52d7-415a-865b-b32aa2876315
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859371439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.859371439
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.512498766
Short name T260
Test name
Test status
Simulation time 869920976 ps
CPU time 3.19 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 203636 kb
Host smart-4ac64cdd-bc76-49b8-85df-b3a9c0147c11
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512498766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.512498766
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.1228319397
Short name T316
Test name
Test status
Simulation time 295776232 ps
CPU time 0.66 seconds
Started Feb 29 12:43:40 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 203552 kb
Host smart-a674deae-bcb4-4dd6-9057-23a210063dd3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228319397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
1228319397
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2479295351
Short name T105
Test name
Test status
Simulation time 1531836726 ps
CPU time 6.93 seconds
Started Feb 29 12:43:42 PM PST 24
Finished Feb 29 12:43:49 PM PST 24
Peak memory 203732 kb
Host smart-0ba21cd5-2308-4a3c-b28e-41b6d3550e2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479295351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2479295351
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tap_fsm_rand_reset.3002495950
Short name T345
Test name
Test status
Simulation time 20198237990 ps
CPU time 13.72 seconds
Started Feb 29 12:43:45 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 203940 kb
Host smart-2ffca3e8-a410-4278-896d-e0581085c153
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002495950 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rv_dm_tap_fsm_rand_reset.3002495950
Directory /workspace/13.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.3499544879
Short name T45
Test name
Test status
Simulation time 96776265 ps
CPU time 5.36 seconds
Started Feb 29 12:43:47 PM PST 24
Finished Feb 29 12:43:53 PM PST 24
Peak memory 203820 kb
Host smart-bae3ef74-4ce6-4151-bfa5-acfc5045e266
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499544879 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.3499544879
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.4242265861
Short name T129
Test name
Test status
Simulation time 1102536922 ps
CPU time 19.92 seconds
Started Feb 29 12:43:40 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 215160 kb
Host smart-729c4658-c792-4c49-af44-8eaf8d6e9d0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242265861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.4
242265861
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.1100970403
Short name T359
Test name
Test status
Simulation time 473253269 ps
CPU time 3.54 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 220068 kb
Host smart-36215146-0842-4e21-87cb-57304c952ce3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100970403 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.1100970403
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.2963596585
Short name T81
Test name
Test status
Simulation time 334065539 ps
CPU time 2.41 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:40 PM PST 24
Peak memory 211888 kb
Host smart-bc727bd1-d220-4ae8-bf97-74cca4817d14
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963596585 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.2963596585
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3928564418
Short name T257
Test name
Test status
Simulation time 664214459 ps
CPU time 1.13 seconds
Started Feb 29 12:44:02 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 203636 kb
Host smart-a1f8169b-b12d-4ef2-bd4b-e7ec53bd77ff
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3928564418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3928564418
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.317837440
Short name T284
Test name
Test status
Simulation time 61498856 ps
CPU time 0.69 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 203816 kb
Host smart-3fd6172d-c861-4114-bcbd-82a5d5cd492e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317837440 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.317837440
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.245886438
Short name T80
Test name
Test status
Simulation time 3355693134 ps
CPU time 7.73 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 203784 kb
Host smart-4c515690-045a-493f-8663-d4f8898af61a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245886438 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same_
csr_outstanding.245886438
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.1575098135
Short name T278
Test name
Test status
Simulation time 8355637837 ps
CPU time 13.86 seconds
Started Feb 29 12:44:02 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 212244 kb
Host smart-280eb353-4cd5-40bb-9a1b-8b7ccc77eacb
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575098135 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.1575098135
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.3202349714
Short name T312
Test name
Test status
Simulation time 168134980 ps
CPU time 3.82 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 214712 kb
Host smart-2e0ed8a2-05f2-49da-beb7-b1647d214f95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202349714 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.3202349714
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.2628818413
Short name T94
Test name
Test status
Simulation time 147931534 ps
CPU time 2.04 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 203760 kb
Host smart-1bbd06a1-2e65-479a-b6cb-62070a894f2d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628818413 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.2628818413
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.729480085
Short name T265
Test name
Test status
Simulation time 911518173 ps
CPU time 2.15 seconds
Started Feb 29 12:43:40 PM PST 24
Finished Feb 29 12:43:42 PM PST 24
Peak memory 203684 kb
Host smart-ac0d6ee2-6aa3-459d-a55e-afd7c296f3ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729480085 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.729480085
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.4286766926
Short name T241
Test name
Test status
Simulation time 67881305 ps
CPU time 0.65 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 203536 kb
Host smart-defca5f5-2a07-454e-a974-2d99e55391d1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286766926 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
4286766926
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.2558871657
Short name T107
Test name
Test status
Simulation time 1548022438 ps
CPU time 7.49 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:02 PM PST 24
Peak memory 203716 kb
Host smart-430d7821-9316-42be-a0d5-0b0261e8f80d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558871657 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same
_csr_outstanding.2558871657
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.4006756466
Short name T281
Test name
Test status
Simulation time 1538479977 ps
CPU time 3.14 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 211968 kb
Host smart-d4619536-feef-4e36-ac9f-5b179b6e6d2f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006756466 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.4006756466
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1217939291
Short name T126
Test name
Test status
Simulation time 1225839423 ps
CPU time 18.99 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 214368 kb
Host smart-5d1bb66b-15d5-44ae-b5e0-67b454d02bed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217939291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
217939291
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.4150246584
Short name T282
Test name
Test status
Simulation time 2802281880 ps
CPU time 7.38 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 216032 kb
Host smart-8e2d5857-83ce-4923-a6bd-6cfeb840d74c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150246584 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.4150246584
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.3565838813
Short name T293
Test name
Test status
Simulation time 834071968 ps
CPU time 1.91 seconds
Started Feb 29 12:43:59 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203780 kb
Host smart-0e79b5bf-ec5f-4a7d-8c28-0f73edb1bdb7
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565838813 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
3565838813
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3136275392
Short name T70
Test name
Test status
Simulation time 86997795 ps
CPU time 0.73 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:44 PM PST 24
Peak memory 203552 kb
Host smart-580e8b74-7c46-427e-a4ca-640ce78391be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136275392 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3136275392
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.1964536840
Short name T332
Test name
Test status
Simulation time 968108748 ps
CPU time 9.56 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 211980 kb
Host smart-bc9c1939-d0d9-4bb4-8502-fd58e5145c76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964536840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.1
964536840
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.3038690776
Short name T331
Test name
Test status
Simulation time 297575883 ps
CPU time 2.5 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 214092 kb
Host smart-a3d75f5c-cac2-4aff-aa95-303ca9e6ba8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038690776 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.3038690776
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.2877774231
Short name T339
Test name
Test status
Simulation time 44341508 ps
CPU time 2.05 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 203692 kb
Host smart-3f4430c7-8c7b-43ff-a6db-bd9c772d8eb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877774231 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.2877774231
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3241428061
Short name T301
Test name
Test status
Simulation time 307501802 ps
CPU time 1.19 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 203584 kb
Host smart-8ac8556f-f9db-45cc-81f0-aaeb56b24ee6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241428061 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3241428061
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2880332533
Short name T341
Test name
Test status
Simulation time 144975640 ps
CPU time 0.7 seconds
Started Feb 29 12:43:39 PM PST 24
Finished Feb 29 12:43:40 PM PST 24
Peak memory 203556 kb
Host smart-bb67694e-e91b-4b04-addd-ba8761b60dc3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880332533 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2880332533
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.2591969236
Short name T348
Test name
Test status
Simulation time 656154088 ps
CPU time 7.22 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 203696 kb
Host smart-bdbc0882-8b92-4d38-8623-84be55d9d40b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591969236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.2591969236
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1254730559
Short name T47
Test name
Test status
Simulation time 106121842 ps
CPU time 3.4 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:47 PM PST 24
Peak memory 212052 kb
Host smart-25604d83-bcae-4fae-8685-42f329821547
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254730559 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1254730559
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.4130672836
Short name T310
Test name
Test status
Simulation time 2050000533 ps
CPU time 18.15 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:44:15 PM PST 24
Peak memory 212952 kb
Host smart-ce671f98-ebf9-4819-8712-7a02d0e82cc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130672836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.4
130672836
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.767752017
Short name T84
Test name
Test status
Simulation time 723319976 ps
CPU time 3.79 seconds
Started Feb 29 12:44:10 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 219604 kb
Host smart-d0e47282-8a75-449a-bff2-4b9963144adc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767752017 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.767752017
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.1142861248
Short name T57
Test name
Test status
Simulation time 52278846 ps
CPU time 2.04 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 211864 kb
Host smart-e0888258-fcec-4c0d-8dfd-e24d8d8803f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142861248 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.1142861248
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.828067028
Short name T243
Test name
Test status
Simulation time 353272537 ps
CPU time 1.45 seconds
Started Feb 29 12:44:12 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 203612 kb
Host smart-34c7eed7-8192-4005-908e-c694d37a63d3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828067028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.828067028
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.274004143
Short name T237
Test name
Test status
Simulation time 48015280 ps
CPU time 0.66 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:53 PM PST 24
Peak memory 203568 kb
Host smart-d40ec7e1-b425-4be2-b6cb-a510aa435940
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274004143 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.274004143
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.2432214887
Short name T96
Test name
Test status
Simulation time 282276835 ps
CPU time 3.37 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 203736 kb
Host smart-d74ee7bf-07c1-446b-b045-15eb66368d73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432214887 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same
_csr_outstanding.2432214887
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.1551129938
Short name T121
Test name
Test status
Simulation time 1330764009 ps
CPU time 18.05 seconds
Started Feb 29 12:43:50 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 215276 kb
Host smart-15a61410-8dc4-4beb-902a-95b708f25f27
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551129938 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.1
551129938
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.633537514
Short name T275
Test name
Test status
Simulation time 1713149136 ps
CPU time 4.6 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:06 PM PST 24
Peak memory 215092 kb
Host smart-a198a0a5-69c3-41a5-8378-a976c4626290
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633537514 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.633537514
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.3459093187
Short name T354
Test name
Test status
Simulation time 241752864 ps
CPU time 2.44 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 203736 kb
Host smart-a1b48709-d7ec-4180-8940-17cb4a2148aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459093187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.3459093187
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.1705236461
Short name T313
Test name
Test status
Simulation time 359951009 ps
CPU time 1.36 seconds
Started Feb 29 12:44:18 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 203652 kb
Host smart-894b3d34-dbe0-47c4-b5ac-b0a93222e62e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705236461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.
1705236461
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1120115738
Short name T254
Test name
Test status
Simulation time 32444926 ps
CPU time 0.69 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:06 PM PST 24
Peak memory 203508 kb
Host smart-d1e05a42-8193-4dec-ac3f-679f3ac62ac3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120115738 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1120115738
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.49791949
Short name T98
Test name
Test status
Simulation time 150253658 ps
CPU time 3.49 seconds
Started Feb 29 12:44:08 PM PST 24
Finished Feb 29 12:44:12 PM PST 24
Peak memory 203752 kb
Host smart-0f2e4778-7f7b-4e49-898c-070cfc6de1b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49791949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same_c
sr_outstanding.49791949
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2495694391
Short name T263
Test name
Test status
Simulation time 143194081 ps
CPU time 1.65 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 204080 kb
Host smart-5a3e9802-a2ae-4b85-9610-14b22413eacf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495694391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2495694391
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.54418016
Short name T123
Test name
Test status
Simulation time 1053571766 ps
CPU time 10.12 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:22 PM PST 24
Peak memory 212704 kb
Host smart-93ce2240-b98b-4ead-b24e-beeb093c4620
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54418016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.54418016
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.2292173921
Short name T101
Test name
Test status
Simulation time 1081952402 ps
CPU time 25.86 seconds
Started Feb 29 12:43:50 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 203660 kb
Host smart-fe4ccafb-372e-4edd-9803-4bf2bf70f36f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292173921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.2292173921
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.915642966
Short name T349
Test name
Test status
Simulation time 739378798 ps
CPU time 27 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203944 kb
Host smart-01b18a88-14ce-4b89-971e-cb2717cbf1e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915642966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.915642966
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.3346231315
Short name T103
Test name
Test status
Simulation time 2062202679 ps
CPU time 2.55 seconds
Started Feb 29 12:43:47 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 203720 kb
Host smart-0e4daf5a-f3bc-4ce7-8826-6a6d036cf274
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346231315 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.3346231315
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.337438058
Short name T147
Test name
Test status
Simulation time 2495663901 ps
CPU time 6.17 seconds
Started Feb 29 12:43:45 PM PST 24
Finished Feb 29 12:43:51 PM PST 24
Peak memory 212132 kb
Host smart-fb7137d4-648b-4b7c-a3bb-7360ba544cd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337438058 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.337438058
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.1441416368
Short name T83
Test name
Test status
Simulation time 225393295 ps
CPU time 2.29 seconds
Started Feb 29 12:43:59 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203756 kb
Host smart-18b09bed-8409-491e-bd4d-d8bccb227c6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441416368 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.1441416368
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2325595275
Short name T247
Test name
Test status
Simulation time 2104500354 ps
CPU time 10.02 seconds
Started Feb 29 12:43:32 PM PST 24
Finished Feb 29 12:43:42 PM PST 24
Peak memory 203676 kb
Host smart-6a9dbed7-0c03-4272-afbc-aa161b3fc834
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325595275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2325595275
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.3569098788
Short name T350
Test name
Test status
Simulation time 13229472892 ps
CPU time 53.58 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:44:38 PM PST 24
Peak memory 203800 kb
Host smart-ac0d00e6-b370-4525-9812-2a471b835f1b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569098788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.3569098788
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.570983816
Short name T89
Test name
Test status
Simulation time 393235894 ps
CPU time 2.02 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203728 kb
Host smart-dcb48231-ca14-4e67-974e-a1a0fc968974
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570983816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.570983816
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.1690453227
Short name T236
Test name
Test status
Simulation time 107008200 ps
CPU time 1.01 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:39 PM PST 24
Peak memory 203628 kb
Host smart-2bd61972-f627-4eb6-852e-e48296caa9d4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690453227 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.1
690453227
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.2571460659
Short name T261
Test name
Test status
Simulation time 35865260 ps
CPU time 0.72 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203192 kb
Host smart-a0d25adc-66cc-4f7c-91f7-5061514c773c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571460659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_aliasing.2571460659
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.1809159213
Short name T352
Test name
Test status
Simulation time 680006937 ps
CPU time 2.14 seconds
Started Feb 29 12:43:28 PM PST 24
Finished Feb 29 12:43:30 PM PST 24
Peak memory 203604 kb
Host smart-1803ec72-a8fe-484c-950b-b5aeae5dd56c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809159213 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.1809159213
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.770620291
Short name T329
Test name
Test status
Simulation time 103273146 ps
CPU time 0.65 seconds
Started Feb 29 12:43:32 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 203472 kb
Host smart-fb7821d6-975a-479a-9602-4ec2e473436b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770620291 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr
_hw_reset.770620291
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.3323218602
Short name T360
Test name
Test status
Simulation time 119863843 ps
CPU time 0.63 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:29 PM PST 24
Peak memory 203484 kb
Host smart-31d2ce8a-22fc-4667-8ca3-bb69e5cf2529
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323218602 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.3
323218602
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2875847513
Short name T249
Test name
Test status
Simulation time 22551013 ps
CPU time 0.63 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203616 kb
Host smart-b96e8fb4-806a-49a1-afd5-212069685be3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875847513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2875847513
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.73205923
Short name T251
Test name
Test status
Simulation time 27295294 ps
CPU time 0.67 seconds
Started Feb 29 12:43:29 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203536 kb
Host smart-0d83b892-fdd2-4248-80b0-dd8fa3890ba8
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73205923 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.73205923
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.3150313500
Short name T48
Test name
Test status
Simulation time 360933541 ps
CPU time 3.37 seconds
Started Feb 29 12:43:39 PM PST 24
Finished Feb 29 12:43:43 PM PST 24
Peak memory 203796 kb
Host smart-3ad4edae-4dd0-4f1d-99fd-6d0ed9aa7bc6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150313500 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.3150313500
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.58557405
Short name T78
Test name
Test status
Simulation time 142212214 ps
CPU time 3.35 seconds
Started Feb 29 12:43:40 PM PST 24
Finished Feb 29 12:43:43 PM PST 24
Peak memory 203704 kb
Host smart-84a9b281-6114-4f8a-ac87-0f8af6a39693
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58557405 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.58557405
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.834314263
Short name T42
Test name
Test status
Simulation time 1421774268 ps
CPU time 7.76 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 211964 kb
Host smart-7add246b-b90d-463d-8cb0-5a7c2c5600bf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834314263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.834314263
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.513088027
Short name T363
Test name
Test status
Simulation time 14737877386 ps
CPU time 25.76 seconds
Started Feb 29 12:43:59 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 220088 kb
Host smart-693490f0-d258-44d7-a9b2-b7731a4452c3
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513088027 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.513088027
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/25.rv_dm_tap_fsm_rand_reset.2676453266
Short name T337
Test name
Test status
Simulation time 6350355854 ps
CPU time 21.36 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:16 PM PST 24
Peak memory 212108 kb
Host smart-170ef2b2-40c7-48c6-8bfa-4a14917a14b6
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676453266 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 25.rv_dm_tap_fsm_rand_reset.2676453266
Directory /workspace/25.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.490698659
Short name T102
Test name
Test status
Simulation time 7248196814 ps
CPU time 73.91 seconds
Started Feb 29 12:43:55 PM PST 24
Finished Feb 29 12:45:09 PM PST 24
Peak memory 212028 kb
Host smart-17d6652f-d752-4f85-af38-7b567ca3e6de
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490698659 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.490698659
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.482052297
Short name T56
Test name
Test status
Simulation time 7237574738 ps
CPU time 36.11 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 203812 kb
Host smart-82429927-8aa5-48a3-bdf8-799353ec8fec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482052297 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.482052297
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1046377025
Short name T49
Test name
Test status
Simulation time 360924504 ps
CPU time 2.36 seconds
Started Feb 29 12:43:59 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203756 kb
Host smart-3809871d-f361-42ff-bbbd-84251feef6c4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046377025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1046377025
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.2691798539
Short name T277
Test name
Test status
Simulation time 1119169969 ps
CPU time 2.84 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 212836 kb
Host smart-f4092465-1695-4256-b887-df8243e2a234
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691798539 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.2691798539
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.4096210284
Short name T321
Test name
Test status
Simulation time 87986160 ps
CPU time 2.22 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 211916 kb
Host smart-931530b1-ba7c-4095-96c3-b7278fa78462
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4096210284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.4096210284
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.673085347
Short name T252
Test name
Test status
Simulation time 17019637835 ps
CPU time 13.29 seconds
Started Feb 29 12:43:49 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 203832 kb
Host smart-4a2aa9d7-29f6-4764-a87b-2c4d9ab50044
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673085347 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_aliasing.673085347
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_bit_bash.957775203
Short name T326
Test name
Test status
Simulation time 11429197278 ps
CPU time 41.69 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:36 PM PST 24
Peak memory 203776 kb
Host smart-685385c7-60fc-4e5c-b700-734ad3d8b371
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957775203 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_bit_bash.957775203
Directory /workspace/3.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.643676786
Short name T92
Test name
Test status
Simulation time 1226340443 ps
CPU time 2.9 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 203980 kb
Host smart-53d9652b-9a69-45b8-8ae5-0faedac654fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643676786 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.643676786
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.3736048450
Short name T314
Test name
Test status
Simulation time 832147836 ps
CPU time 1.88 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203672 kb
Host smart-0b487552-dc06-4107-99ea-8e735a412c4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736048450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.3
736048450
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.2370834984
Short name T361
Test name
Test status
Simulation time 324659833 ps
CPU time 0.79 seconds
Started Feb 29 12:43:58 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 203604 kb
Host smart-86f8999f-7c82-4f55-8c8f-e50f713b0e74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370834984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_aliasing.2370834984
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.3529224102
Short name T305
Test name
Test status
Simulation time 746490000 ps
CPU time 3.88 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 203888 kb
Host smart-28b3f3b9-cee2-40c8-b39e-c4e71b88bb3c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529224102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.3529224102
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.2115263534
Short name T288
Test name
Test status
Simulation time 95940436 ps
CPU time 0.87 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 203612 kb
Host smart-6f1ddf67-55a1-4398-9e77-d634cc3be659
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115263534 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.2115263534
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.1304206266
Short name T279
Test name
Test status
Simulation time 125599339 ps
CPU time 0.76 seconds
Started Feb 29 12:43:26 PM PST 24
Finished Feb 29 12:43:27 PM PST 24
Peak memory 203616 kb
Host smart-3feba97e-d157-410f-a841-1e144ea4b366
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304206266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.1
304206266
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.2934083688
Short name T357
Test name
Test status
Simulation time 56495555 ps
CPU time 0.64 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 203540 kb
Host smart-b0adc42c-4d20-40bd-956e-f140f36f3b42
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934083688 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.2934083688
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.3029879695
Short name T244
Test name
Test status
Simulation time 184817297 ps
CPU time 0.66 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 203452 kb
Host smart-3fafa877-907c-4414-8d79-271d9032f3cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029879695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.3029879695
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.264135931
Short name T344
Test name
Test status
Simulation time 1096687819 ps
CPU time 7.55 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:09 PM PST 24
Peak memory 203636 kb
Host smart-bcf148e7-786f-4b33-a5ce-a6ad9098d353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264135931 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.264135931
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4047133101
Short name T309
Test name
Test status
Simulation time 841364025 ps
CPU time 5.3 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:48 PM PST 24
Peak memory 212108 kb
Host smart-f477c4b9-e03c-4768-8cf5-bb266d3e4d47
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047133101 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4047133101
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.2796602695
Short name T306
Test name
Test status
Simulation time 12884688776 ps
CPU time 13.36 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 212156 kb
Host smart-8e2c96dc-c252-494b-9c6a-6a3fd16d1974
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796602695 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.2796602695
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.79029310
Short name T335
Test name
Test status
Simulation time 6492727370 ps
CPU time 12.81 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:25 PM PST 24
Peak memory 214472 kb
Host smart-2bebfe86-33b4-4b43-bef6-b75cf92b0ab5
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79029310 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.79029310
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/33.rv_dm_tap_fsm_rand_reset.1274537384
Short name T63
Test name
Test status
Simulation time 6564287124 ps
CPU time 22.29 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:44:19 PM PST 24
Peak memory 212096 kb
Host smart-d99f1c54-2c58-4921-89b0-9c316e0b5562
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274537384 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 33.rv_dm_tap_fsm_rand_reset.1274537384
Directory /workspace/33.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.2453839644
Short name T358
Test name
Test status
Simulation time 2294992642 ps
CPU time 66.77 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:45:00 PM PST 24
Peak memory 212044 kb
Host smart-c893c62b-47b8-4621-819f-9611235eb926
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453839644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 4.rv_dm_csr_aliasing.2453839644
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.4200556029
Short name T259
Test name
Test status
Simulation time 2912464315 ps
CPU time 53.05 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:44:27 PM PST 24
Peak memory 203832 kb
Host smart-80ebaf2f-598f-47f5-aae6-7117da94aaf9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200556029 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.4200556029
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.2563747634
Short name T343
Test name
Test status
Simulation time 164309201 ps
CPU time 1.63 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 203724 kb
Host smart-4192b7b2-3be5-4d76-82b4-abe0fdbb7ad5
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563747634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.2563747634
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1175700478
Short name T267
Test name
Test status
Simulation time 4357043691 ps
CPU time 8.64 seconds
Started Feb 29 12:43:48 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 214068 kb
Host smart-ded77892-f483-4bdd-9b0c-54bdc4d7ae10
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175700478 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1175700478
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.613685984
Short name T269
Test name
Test status
Simulation time 92949008 ps
CPU time 1.37 seconds
Started Feb 29 12:43:30 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 203756 kb
Host smart-2f68e5ff-71ad-433e-98b2-267a62280640
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=613685984 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.613685984
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1850035840
Short name T322
Test name
Test status
Simulation time 4647192515 ps
CPU time 10.9 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:45 PM PST 24
Peak memory 203736 kb
Host smart-01d84f78-814e-4441-a964-fe554a42fd8b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850035840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1850035840
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3795668234
Short name T362
Test name
Test status
Simulation time 30152805358 ps
CPU time 44.33 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:44:20 PM PST 24
Peak memory 203752 kb
Host smart-ae09fbd0-01d4-476c-ae08-12479083d1eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795668234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3795668234
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1749329577
Short name T90
Test name
Test status
Simulation time 744129514 ps
CPU time 1.65 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 203724 kb
Host smart-38a2f707-4e49-4e45-95d3-191e0f122b68
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749329577 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1749329577
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.779758286
Short name T69
Test name
Test status
Simulation time 128713857 ps
CPU time 0.97 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:45 PM PST 24
Peak memory 203600 kb
Host smart-54fb151f-253f-4974-a306-bf6e658b3282
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779758286 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_aliasing.779758286
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.943296022
Short name T330
Test name
Test status
Simulation time 2328554889 ps
CPU time 2.64 seconds
Started Feb 29 12:44:00 PM PST 24
Finished Feb 29 12:44:03 PM PST 24
Peak memory 203768 kb
Host smart-9555eb64-ac47-4e3d-b4e8-e5148de163ba
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943296022 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr
_bit_bash.943296022
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3769222126
Short name T287
Test name
Test status
Simulation time 49002505 ps
CPU time 0.7 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:10 PM PST 24
Peak memory 203536 kb
Host smart-a49d28df-7ffd-4c9a-a636-10a0b6d81e15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769222126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3769222126
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.1106332624
Short name T303
Test name
Test status
Simulation time 94162458 ps
CPU time 0.88 seconds
Started Feb 29 12:43:33 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203856 kb
Host smart-05ed638f-0bae-46c2-bacf-45fb2438ff17
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106332624 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.1
106332624
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.799755789
Short name T296
Test name
Test status
Simulation time 68662947 ps
CPU time 0.59 seconds
Started Feb 29 12:43:35 PM PST 24
Finished Feb 29 12:43:41 PM PST 24
Peak memory 203500 kb
Host smart-fd3f8d98-8848-46ea-a441-c922db7e93d5
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799755789 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_part
ial_access.799755789
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.3761541889
Short name T262
Test name
Test status
Simulation time 34373204 ps
CPU time 0.61 seconds
Started Feb 29 12:43:45 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 203460 kb
Host smart-665cac09-32f9-48fb-9b65-06fb5222180e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761541889 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.3761541889
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3768163859
Short name T336
Test name
Test status
Simulation time 297986301 ps
CPU time 4.21 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 203708 kb
Host smart-10fe9b4d-650a-47ba-bbc7-0b9c8ff0110c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768163859 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3768163859
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.2582696293
Short name T317
Test name
Test status
Simulation time 52213724 ps
CPU time 2.48 seconds
Started Feb 29 12:44:11 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 212088 kb
Host smart-7cbcb1cf-2a1d-4ce3-aa0d-623d9e899b21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582696293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.2582696293
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.1906335356
Short name T131
Test name
Test status
Simulation time 1538649307 ps
CPU time 10.26 seconds
Started Feb 29 12:43:35 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 212040 kb
Host smart-88e9ecb6-78c0-45f8-8614-707962450e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906335356 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.1906335356
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.800550740
Short name T143
Test name
Test status
Simulation time 1700987954 ps
CPU time 5.16 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:57 PM PST 24
Peak memory 213780 kb
Host smart-d84847d3-d801-4529-bdb4-d06977aeb4db
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800550740 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.800550740
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.545486526
Short name T239
Test name
Test status
Simulation time 609176054 ps
CPU time 2.1 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:36 PM PST 24
Peak memory 211976 kb
Host smart-85cd26cc-bacf-4a3a-831c-4fbfa8938fe1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545486526 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.545486526
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1826953925
Short name T238
Test name
Test status
Simulation time 226872356 ps
CPU time 1.57 seconds
Started Feb 29 12:43:38 PM PST 24
Finished Feb 29 12:43:39 PM PST 24
Peak memory 203632 kb
Host smart-ad2c3fad-c8a5-4757-9a19-c62f717f243f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826953925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
826953925
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.1791240481
Short name T302
Test name
Test status
Simulation time 31738059 ps
CPU time 0.63 seconds
Started Feb 29 12:43:32 PM PST 24
Finished Feb 29 12:43:33 PM PST 24
Peak memory 203504 kb
Host smart-7e3ea807-754e-4c6d-85b6-0375af8e4726
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791240481 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.1
791240481
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.3296526872
Short name T328
Test name
Test status
Simulation time 337339136 ps
CPU time 3.73 seconds
Started Feb 29 12:43:46 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 203792 kb
Host smart-2198ee86-2101-43e8-9411-af108975555d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296526872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_
csr_outstanding.3296526872
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.2818918314
Short name T340
Test name
Test status
Simulation time 109904995 ps
CPU time 1.87 seconds
Started Feb 29 12:43:36 PM PST 24
Finished Feb 29 12:43:38 PM PST 24
Peak memory 203776 kb
Host smart-24386c81-060b-41cd-b74e-b1f4167ebe63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818918314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.2818918314
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.537646431
Short name T122
Test name
Test status
Simulation time 2456693110 ps
CPU time 9.49 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:46 PM PST 24
Peak memory 212736 kb
Host smart-39ef9fe3-ef18-4d92-a969-805b75868395
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537646431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.537646431
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.1601318537
Short name T324
Test name
Test status
Simulation time 1057946767 ps
CPU time 2.69 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:43:59 PM PST 24
Peak memory 212184 kb
Host smart-4a5420e2-81d7-440e-8584-c7267758e7af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1601318537 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.1601318537
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.4122277918
Short name T104
Test name
Test status
Simulation time 250851404 ps
CPU time 2.4 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:37 PM PST 24
Peak memory 203800 kb
Host smart-7c0d2250-3cff-4970-8cbb-663504a286e9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122277918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.4122277918
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2033484161
Short name T311
Test name
Test status
Simulation time 139626596 ps
CPU time 0.91 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:32 PM PST 24
Peak memory 203676 kb
Host smart-e11c18ed-3fbd-478f-8343-4090859b0d75
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033484161 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
033484161
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.2962377766
Short name T272
Test name
Test status
Simulation time 93934306 ps
CPU time 0.78 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203488 kb
Host smart-5d65495c-7e5b-44a3-8a87-f7c50138b6be
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962377766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.2
962377766
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.2506477900
Short name T106
Test name
Test status
Simulation time 1044258207 ps
CPU time 3.71 seconds
Started Feb 29 12:43:31 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203772 kb
Host smart-98949df3-2cc7-439a-a105-7ccec4c8f319
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506477900 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.2506477900
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.1621734898
Short name T266
Test name
Test status
Simulation time 72326036 ps
CPU time 1.97 seconds
Started Feb 29 12:44:09 PM PST 24
Finished Feb 29 12:44:11 PM PST 24
Peak memory 212012 kb
Host smart-8d2b64cc-7a28-4760-bad7-ce5c9f95e678
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621734898 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.1621734898
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.978726117
Short name T280
Test name
Test status
Simulation time 849414595 ps
CPU time 2.27 seconds
Started Feb 29 12:43:37 PM PST 24
Finished Feb 29 12:43:39 PM PST 24
Peak memory 211992 kb
Host smart-ab638f28-d10f-4c67-b425-e37a8de75d56
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978726117 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.978726117
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.2319929418
Short name T355
Test name
Test status
Simulation time 31009251 ps
CPU time 1.43 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:08 PM PST 24
Peak memory 211960 kb
Host smart-72785be7-2674-40d0-8650-47d8bfce1f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319929418 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.2319929418
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.2689122622
Short name T274
Test name
Test status
Simulation time 188189636 ps
CPU time 0.88 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 203636 kb
Host smart-80330ab0-64c1-4ff6-a0b2-6def723ae95c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689122622 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.2
689122622
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.377878003
Short name T240
Test name
Test status
Simulation time 27867855 ps
CPU time 0.71 seconds
Started Feb 29 12:44:04 PM PST 24
Finished Feb 29 12:44:05 PM PST 24
Peak memory 203500 kb
Host smart-85c4d784-7f6f-4bc8-825c-010889fa53ed
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377878003 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.377878003
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1680544357
Short name T97
Test name
Test status
Simulation time 1351134895 ps
CPU time 6.81 seconds
Started Feb 29 12:43:43 PM PST 24
Finished Feb 29 12:43:50 PM PST 24
Peak memory 203836 kb
Host smart-5e0adf14-2e02-41c3-8aa8-f7ed669dacf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680544357 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1680544357
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.1761513204
Short name T157
Test name
Test status
Simulation time 514337771 ps
CPU time 4.52 seconds
Started Feb 29 12:43:57 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 211992 kb
Host smart-0b1c0364-375b-42ca-9cd5-0322c0f5eb81
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761513204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.1761513204
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.1776208698
Short name T298
Test name
Test status
Simulation time 225392973 ps
CPU time 7.86 seconds
Started Feb 29 12:44:05 PM PST 24
Finished Feb 29 12:44:14 PM PST 24
Peak memory 211968 kb
Host smart-49967275-03a0-4d44-94ce-af75344223b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776208698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.1776208698
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.3103459917
Short name T264
Test name
Test status
Simulation time 2015269849 ps
CPU time 2.37 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:43:56 PM PST 24
Peak memory 220152 kb
Host smart-53e3b208-f520-4629-bf89-9d7400aec3ea
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3103459917 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.3103459917
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2759609132
Short name T342
Test name
Test status
Simulation time 101857984 ps
CPU time 1.32 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:00 PM PST 24
Peak memory 203788 kb
Host smart-5b31447a-5a4f-4497-b87d-1c0f11190e31
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759609132 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2759609132
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.2637784634
Short name T297
Test name
Test status
Simulation time 1848889669 ps
CPU time 2.38 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 203888 kb
Host smart-53f192a7-73ef-4d83-9ed9-20a1933312f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637784634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.2
637784634
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.2855340210
Short name T285
Test name
Test status
Simulation time 54055838 ps
CPU time 0.72 seconds
Started Feb 29 12:43:53 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 203812 kb
Host smart-10365496-e018-4f68-9ff6-bc8edcb9ae7d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2855340210 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.2
855340210
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.2410877222
Short name T112
Test name
Test status
Simulation time 440641652 ps
CPU time 6.5 seconds
Started Feb 29 12:43:55 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 203748 kb
Host smart-ae68a75d-9134-4f34-8bd7-0fbf49d63eaa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410877222 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_
csr_outstanding.2410877222
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.233045266
Short name T76
Test name
Test status
Simulation time 118153709 ps
CPU time 3.25 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 203764 kb
Host smart-eebfc42f-1087-4d64-a622-9b1bf8fc4ae0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233045266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.233045266
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.3134180539
Short name T128
Test name
Test status
Simulation time 566213235 ps
CPU time 15.02 seconds
Started Feb 29 12:44:01 PM PST 24
Finished Feb 29 12:44:17 PM PST 24
Peak memory 211852 kb
Host smart-862349e2-62a8-4fbf-ac0b-dde9250b2e9d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134180539 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.3134180539
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.3540860543
Short name T55
Test name
Test status
Simulation time 1504282126 ps
CPU time 2.23 seconds
Started Feb 29 12:43:56 PM PST 24
Finished Feb 29 12:43:58 PM PST 24
Peak memory 212048 kb
Host smart-9202043e-8f77-46be-8d61-d131302c724b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540860543 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.3540860543
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4166323133
Short name T253
Test name
Test status
Simulation time 40272300 ps
CPU time 1.32 seconds
Started Feb 29 12:43:34 PM PST 24
Finished Feb 29 12:43:35 PM PST 24
Peak memory 203656 kb
Host smart-dc6b2c00-e4db-4490-b14f-bb125afa09a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166323133 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4166323133
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.3718417363
Short name T258
Test name
Test status
Simulation time 549665533 ps
CPU time 2.48 seconds
Started Feb 29 12:43:52 PM PST 24
Finished Feb 29 12:43:54 PM PST 24
Peak memory 203484 kb
Host smart-7c016f02-3015-492d-ad91-0b63ad2f13e8
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718417363 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.3
718417363
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.3816403394
Short name T334
Test name
Test status
Simulation time 41939811 ps
CPU time 0.7 seconds
Started Feb 29 12:44:03 PM PST 24
Finished Feb 29 12:44:04 PM PST 24
Peak memory 203556 kb
Host smart-2bda8839-37be-4e39-a9b0-ebb400ef6c3d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816403394 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.3
816403394
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.2364817925
Short name T110
Test name
Test status
Simulation time 1532347287 ps
CPU time 7.21 seconds
Started Feb 29 12:43:44 PM PST 24
Finished Feb 29 12:43:52 PM PST 24
Peak memory 203700 kb
Host smart-ce257515-d713-4af5-b1af-e5eb174482c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364817925 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_
csr_outstanding.2364817925
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.2928774743
Short name T292
Test name
Test status
Simulation time 249333949 ps
CPU time 4.19 seconds
Started Feb 29 12:43:51 PM PST 24
Finished Feb 29 12:43:55 PM PST 24
Peak memory 212280 kb
Host smart-46ba06c2-3ae0-4ec1-82c2-319f62c98258
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928774743 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.2928774743
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1001633094
Short name T72
Test name
Test status
Simulation time 419796384 ps
CPU time 7.64 seconds
Started Feb 29 12:43:54 PM PST 24
Finished Feb 29 12:44:01 PM PST 24
Peak memory 211972 kb
Host smart-d01bee9f-4806-4613-91a5-58c3af5cb77e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001633094 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1001633094
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.3759176493
Short name T151
Test name
Test status
Simulation time 72516773 ps
CPU time 0.69 seconds
Started Feb 29 12:44:52 PM PST 24
Finished Feb 29 12:44:52 PM PST 24
Peak memory 203788 kb
Host smart-f5150b5b-254f-4b23-8225-c810aa2435e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759176493 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.3759176493
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.2106839945
Short name T197
Test name
Test status
Simulation time 615675817 ps
CPU time 2.54 seconds
Started Feb 29 12:45:02 PM PST 24
Finished Feb 29 12:45:05 PM PST 24
Peak memory 204144 kb
Host smart-cb30f839-c900-4138-99ad-53ba726cbf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106839945 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.2106839945
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.2505382254
Short name T21
Test name
Test status
Simulation time 5179921196 ps
CPU time 3.19 seconds
Started Feb 29 12:45:03 PM PST 24
Finished Feb 29 12:45:06 PM PST 24
Peak memory 204112 kb
Host smart-71f953a1-fb59-4d48-9e76-ca0ba8507246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505382254 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.2505382254
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.1934745460
Short name T133
Test name
Test status
Simulation time 75639602 ps
CPU time 0.74 seconds
Started Feb 29 12:45:00 PM PST 24
Finished Feb 29 12:45:01 PM PST 24
Peak memory 203836 kb
Host smart-86fa3537-bdba-49a5-a65e-b3b8c1940f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934745460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.1934745460
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2672376053
Short name T214
Test name
Test status
Simulation time 7811313326 ps
CPU time 27.48 seconds
Started Feb 29 12:44:50 PM PST 24
Finished Feb 29 12:45:18 PM PST 24
Peak memory 204164 kb
Host smart-8d8b0ab0-4bb3-40ce-b62a-12639f6586c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672376053 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2672376053
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.2406511739
Short name T34
Test name
Test status
Simulation time 75826804 ps
CPU time 0.92 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 203764 kb
Host smart-ee6fdaad-5787-4889-bbbd-b46c25035bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406511739 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.2406511739
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3079743521
Short name T222
Test name
Test status
Simulation time 67034854 ps
CPU time 0.67 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:45 PM PST 24
Peak memory 203412 kb
Host smart-09f0988e-0261-4775-9611-28565f836eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079743521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3079743521
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_debug_disabled.1137615065
Short name T35
Test name
Test status
Simulation time 222374299 ps
CPU time 0.97 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 203500 kb
Host smart-b48fbb66-988d-4204-85c2-3fddf5495f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137615065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_debug_disabled.1137615065
Directory /workspace/0.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2281493623
Short name T15
Test name
Test status
Simulation time 79487835 ps
CPU time 0.91 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 203628 kb
Host smart-f688104c-f9b9-4958-a485-219f153e3a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281493623 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2281493623
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2813307814
Short name T61
Test name
Test status
Simulation time 368068642 ps
CPU time 0.97 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 203652 kb
Host smart-163533de-8dd5-42aa-a3aa-2790dc6e9e02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813307814 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2813307814
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.3272507561
Short name T23
Test name
Test status
Simulation time 60001743 ps
CPU time 0.65 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 203424 kb
Host smart-0f240898-ad21-4576-a8b2-7241040324e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272507561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.3272507561
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.3453330057
Short name T74
Test name
Test status
Simulation time 62559525 ps
CPU time 0.82 seconds
Started Feb 29 12:44:55 PM PST 24
Finished Feb 29 12:44:56 PM PST 24
Peak memory 203752 kb
Host smart-1345266e-5bdf-48f7-ba81-6896fd1b7fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453330057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.3453330057
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2314740684
Short name T7
Test name
Test status
Simulation time 160592722 ps
CPU time 0.65 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 203684 kb
Host smart-9b61f18e-cc5f-48dc-95a2-d1bbd54bef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314740684 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2314740684
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.3547273369
Short name T17
Test name
Test status
Simulation time 613362004 ps
CPU time 1.65 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 203932 kb
Host smart-24469eef-cc82-423d-962e-3a6a4a291b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547273369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.3547273369
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.114940204
Short name T210
Test name
Test status
Simulation time 6961285792 ps
CPU time 7.69 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 204172 kb
Host smart-07898b31-c8e5-4980-b89e-8bec4c22ec56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114940204 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.114940204
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.3199713566
Short name T226
Test name
Test status
Simulation time 619839910 ps
CPU time 1.11 seconds
Started Feb 29 12:44:42 PM PST 24
Finished Feb 29 12:44:44 PM PST 24
Peak memory 203748 kb
Host smart-8d95d6cb-b3dd-4e88-b40d-45a9e902cf58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199713566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.3199713566
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.3026024230
Short name T142
Test name
Test status
Simulation time 21620513 ps
CPU time 0.69 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 203776 kb
Host smart-200f7867-c9a7-45d4-b8ae-56f9207d9d0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026024230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.3026024230
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.2441865884
Short name T217
Test name
Test status
Simulation time 669530599 ps
CPU time 3.5 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 204080 kb
Host smart-4b3b99ae-7216-473a-9270-9dfa1a911914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441865884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.2441865884
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.1276156960
Short name T10
Test name
Test status
Simulation time 616120959 ps
CPU time 2.92 seconds
Started Feb 29 12:45:05 PM PST 24
Finished Feb 29 12:45:08 PM PST 24
Peak memory 204028 kb
Host smart-59404c2d-a3d8-490b-b221-06157a0f63d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276156960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.1276156960
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.4185860350
Short name T33
Test name
Test status
Simulation time 410814609 ps
CPU time 1.34 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 203844 kb
Host smart-453ada1c-a193-4181-85d6-16e6c89fb079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185860350 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.4185860350
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.4285811685
Short name T27
Test name
Test status
Simulation time 196769389 ps
CPU time 0.77 seconds
Started Feb 29 12:44:59 PM PST 24
Finished Feb 29 12:45:00 PM PST 24
Peak memory 203624 kb
Host smart-96a8bb97-8064-4b50-b920-8fbb6614fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285811685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.4285811685
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.1470417521
Short name T22
Test name
Test status
Simulation time 1273995737 ps
CPU time 4.29 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 203980 kb
Host smart-97e1ad91-c7d5-41b0-bb6b-ea0b47deec1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470417521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.1470417521
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.3142123298
Short name T24
Test name
Test status
Simulation time 85438424 ps
CPU time 0.82 seconds
Started Feb 29 12:45:02 PM PST 24
Finished Feb 29 12:45:03 PM PST 24
Peak memory 203792 kb
Host smart-a401d3de-4c52-4093-be3e-bfcbb326bf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142123298 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.3142123298
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.3042503745
Short name T176
Test name
Test status
Simulation time 9984323001 ps
CPU time 12.14 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:56 PM PST 24
Peak memory 204208 kb
Host smart-4bd17cc2-3306-4a5f-bfea-38676c8dfe93
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3042503745 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.3042503745
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.2759260070
Short name T8
Test name
Test status
Simulation time 128450876 ps
CPU time 1.17 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:50 PM PST 24
Peak memory 203992 kb
Host smart-2fe0b12d-ca9e-469b-a102-36aa515d6c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759260070 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.2759260070
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.3720665704
Short name T212
Test name
Test status
Simulation time 299952317 ps
CPU time 0.73 seconds
Started Feb 29 12:44:41 PM PST 24
Finished Feb 29 12:44:42 PM PST 24
Peak memory 203584 kb
Host smart-dfdd88ee-3716-4611-8e97-cec8cb64706f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720665704 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.3720665704
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.411224123
Short name T16
Test name
Test status
Simulation time 950940670 ps
CPU time 3.54 seconds
Started Feb 29 12:44:42 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 203704 kb
Host smart-5e69e9fe-70e0-4c81-b64f-e40ca51435b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411224123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.411224123
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.930403446
Short name T29
Test name
Test status
Simulation time 61235292 ps
CPU time 0.71 seconds
Started Feb 29 12:45:08 PM PST 24
Finished Feb 29 12:45:09 PM PST 24
Peak memory 203388 kb
Host smart-3e230821-5a09-456c-b31a-048599f9ab3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930403446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.930403446
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.640587071
Short name T224
Test name
Test status
Simulation time 68097146 ps
CPU time 0.8 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 203760 kb
Host smart-8ee2bf28-4f36-49a7-bb35-2cf7f0f8ab8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=640587071 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.640587071
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.772932613
Short name T73
Test name
Test status
Simulation time 120160082 ps
CPU time 0.7 seconds
Started Feb 29 12:45:00 PM PST 24
Finished Feb 29 12:45:01 PM PST 24
Peak memory 203828 kb
Host smart-e03ec762-4486-4942-a077-911f5e1429e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772932613 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.772932613
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.2059163263
Short name T18
Test name
Test status
Simulation time 618293617 ps
CPU time 1.61 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 203956 kb
Host smart-279cb461-e2dd-46eb-ac72-090f43159ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059163263 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.2059163263
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.2887072141
Short name T32
Test name
Test status
Simulation time 90492326 ps
CPU time 1.04 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:46 PM PST 24
Peak memory 203960 kb
Host smart-b4262ee2-9c7a-4860-9d25-65b51ccbc877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887072141 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.2887072141
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.1165774025
Short name T31
Test name
Test status
Simulation time 65423099 ps
CPU time 0.72 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:45 PM PST 24
Peak memory 203832 kb
Host smart-fc1f7388-9f0f-45da-b1a7-583414a44703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165774025 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.1165774025
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.1902798384
Short name T211
Test name
Test status
Simulation time 17560360879 ps
CPU time 58.92 seconds
Started Feb 29 12:44:43 PM PST 24
Finished Feb 29 12:45:42 PM PST 24
Peak memory 204148 kb
Host smart-9355663a-6849-4eda-a9e1-73c680a82620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902798384 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.1902798384
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.788081287
Short name T40
Test name
Test status
Simulation time 72931187 ps
CPU time 1.16 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 219964 kb
Host smart-42ef6d15-5d6b-4f11-aa83-b618856f6098
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788081287 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.788081287
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2721112636
Short name T231
Test name
Test status
Simulation time 192066589 ps
CPU time 1.19 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 203328 kb
Host smart-636cce57-b873-4d21-97c2-7405ac51885e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721112636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2721112636
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.16094106
Short name T206
Test name
Test status
Simulation time 47328974 ps
CPU time 0.66 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:19 PM PST 24
Peak memory 203788 kb
Host smart-fbf17edb-c16e-4093-843b-85f85d0cd1b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16094106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.16094106
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.3168820260
Short name T230
Test name
Test status
Simulation time 12547529605 ps
CPU time 9.69 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203628 kb
Host smart-945e593a-e172-4871-98e8-48def3bcf2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168820260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.3168820260
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.1127219112
Short name T221
Test name
Test status
Simulation time 7430460356 ps
CPU time 24.82 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:45:47 PM PST 24
Peak memory 204240 kb
Host smart-6b8f32a1-3ced-4376-85c9-a44538b4f6a8
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1127219112 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_
tl_access.1127219112
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.4112051857
Short name T216
Test name
Test status
Simulation time 3686149084 ps
CPU time 6.92 seconds
Started Feb 29 12:45:15 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 204256 kb
Host smart-2036b5cd-df76-47fd-9068-fa213d3336f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4112051857 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.4112051857
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.3005421714
Short name T141
Test name
Test status
Simulation time 25127695 ps
CPU time 0.69 seconds
Started Feb 29 12:45:23 PM PST 24
Finished Feb 29 12:45:24 PM PST 24
Peak memory 203772 kb
Host smart-2d4d1b46-3386-4b0b-ab64-f8a13df8dbd9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005421714 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.3005421714
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_autoincr_sba_tl_access.1412359431
Short name T187
Test name
Test status
Simulation time 4553208609 ps
CPU time 22.11 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:46 PM PST 24
Peak memory 204216 kb
Host smart-d7b6dddc-1f69-4abb-af1d-f9f5f6c81ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412359431 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_autoincr_sba_tl_access.1412359431
Directory /workspace/11.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.352502045
Short name T203
Test name
Test status
Simulation time 5857560992 ps
CPU time 8.4 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:45:30 PM PST 24
Peak memory 204144 kb
Host smart-6971c743-f96c-44c5-8c18-a764b5d16151
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=352502045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_t
l_access.352502045
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.878224918
Short name T213
Test name
Test status
Simulation time 692654259 ps
CPU time 2.81 seconds
Started Feb 29 12:45:33 PM PST 24
Finished Feb 29 12:45:36 PM PST 24
Peak memory 204080 kb
Host smart-0c8e336d-b2d5-483e-be9e-13dfd1b8b208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878224918 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.878224918
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.3475574028
Short name T140
Test name
Test status
Simulation time 18721757 ps
CPU time 0.65 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 203808 kb
Host smart-ac6d62d1-bc95-42d5-888e-726bbbd243d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475574028 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.3475574028
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.433089631
Short name T66
Test name
Test status
Simulation time 2929370855 ps
CPU time 10.52 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:34 PM PST 24
Peak memory 203960 kb
Host smart-f92fdf4e-92b8-422d-aee3-1c1eca11879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433089631 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.433089631
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.3050739280
Short name T86
Test name
Test status
Simulation time 6837446817 ps
CPU time 8.84 seconds
Started Feb 29 12:45:29 PM PST 24
Finished Feb 29 12:45:39 PM PST 24
Peak memory 204188 kb
Host smart-a9738802-35bc-480b-a71f-b4120471f1c6
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3050739280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.3050739280
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.2344026982
Short name T208
Test name
Test status
Simulation time 15663006858 ps
CPU time 52.06 seconds
Started Feb 29 12:45:16 PM PST 24
Finished Feb 29 12:46:08 PM PST 24
Peak memory 204176 kb
Host smart-8f898a40-beb2-4f24-81fe-ab86a6bf4466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344026982 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.2344026982
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.4003977097
Short name T150
Test name
Test status
Simulation time 25928982 ps
CPU time 0.68 seconds
Started Feb 29 12:45:23 PM PST 24
Finished Feb 29 12:45:23 PM PST 24
Peak memory 203716 kb
Host smart-10fe7e92-893b-4544-8fc3-fccf8603cdaa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003977097 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.4003977097
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2385467178
Short name T175
Test name
Test status
Simulation time 1852920724 ps
CPU time 5.02 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:30 PM PST 24
Peak memory 204128 kb
Host smart-efb88dcc-e166-48dd-b1b2-373774eca9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385467178 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2385467178
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.2624879168
Short name T193
Test name
Test status
Simulation time 1818865611 ps
CPU time 3.12 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:28 PM PST 24
Peak memory 204156 kb
Host smart-cf95f559-ee2d-44ec-8768-40a8a07fc811
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624879168 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_
tl_access.2624879168
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3613273805
Short name T39
Test name
Test status
Simulation time 4650680317 ps
CPU time 8.93 seconds
Started Feb 29 12:45:28 PM PST 24
Finished Feb 29 12:45:38 PM PST 24
Peak memory 204104 kb
Host smart-7af43a29-2554-4e71-bb32-17aca1cfd3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613273805 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3613273805
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.3685328713
Short name T145
Test name
Test status
Simulation time 54880101 ps
CPU time 0.69 seconds
Started Feb 29 12:45:28 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203688 kb
Host smart-67125bb9-3096-46ff-8228-884b676f9bde
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685328713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.3685328713
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_bad_sba_tl_access.3566218062
Short name T12
Test name
Test status
Simulation time 4797068050 ps
CPU time 14.05 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:36 PM PST 24
Peak memory 204128 kb
Host smart-488a27a2-2c18-4811-802d-f5d918ec233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566218062 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_bad_sba_tl_access.3566218062
Directory /workspace/14.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_delayed_resp_sba_tl_access.3812960169
Short name T194
Test name
Test status
Simulation time 1349858874 ps
CPU time 3.36 seconds
Started Feb 29 12:45:38 PM PST 24
Finished Feb 29 12:45:42 PM PST 24
Peak memory 204076 kb
Host smart-2b3d4d95-bb61-42e0-8dc4-4b823adb34a2
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812960169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_delayed_resp_sba_
tl_access.3812960169
Directory /workspace/14.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.482497535
Short name T227
Test name
Test status
Simulation time 5368280263 ps
CPU time 18.17 seconds
Started Feb 29 12:45:25 PM PST 24
Finished Feb 29 12:45:44 PM PST 24
Peak memory 204208 kb
Host smart-b5504f1d-5f9f-4aad-88ea-c3ccf395307a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482497535 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.482497535
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.1251274769
Short name T174
Test name
Test status
Simulation time 63063218 ps
CPU time 0.74 seconds
Started Feb 29 12:45:01 PM PST 24
Finished Feb 29 12:45:01 PM PST 24
Peak memory 203812 kb
Host smart-c0f5e2a2-d2e2-4dad-b6a2-caa37521f840
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251274769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.1251274769
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_bad_sba_tl_access.1877008960
Short name T202
Test name
Test status
Simulation time 1241108011 ps
CPU time 2.63 seconds
Started Feb 29 12:45:35 PM PST 24
Finished Feb 29 12:45:37 PM PST 24
Peak memory 204076 kb
Host smart-f9c5bcd5-2dd3-441e-be9b-4f975ad18997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877008960 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_bad_sba_tl_access.1877008960
Directory /workspace/15.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.2579790496
Short name T87
Test name
Test status
Simulation time 2038721161 ps
CPU time 4.78 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:45 PM PST 24
Peak memory 204104 kb
Host smart-2774df92-47b6-43fa-9ee7-3156e8cdbc95
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2579790496 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.2579790496
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.3395179708
Short name T54
Test name
Test status
Simulation time 17389667 ps
CPU time 0.7 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 203776 kb
Host smart-24671bce-6a30-4047-9b14-1eb31d310375
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395179708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.3395179708
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_autoincr_sba_tl_access.1513478547
Short name T185
Test name
Test status
Simulation time 11509708141 ps
CPU time 20.37 seconds
Started Feb 29 12:45:16 PM PST 24
Finished Feb 29 12:45:42 PM PST 24
Peak memory 204172 kb
Host smart-0debf4ca-e14a-41b7-a8a7-1feadc9f3b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513478547 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_autoincr_sba_tl_access.1513478547
Directory /workspace/16.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_bad_sba_tl_access.2873690319
Short name T207
Test name
Test status
Simulation time 9996430451 ps
CPU time 29.28 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:49 PM PST 24
Peak memory 203528 kb
Host smart-f26bd778-1743-49ca-b2fc-c5bb39301fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873690319 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_bad_sba_tl_access.2873690319
Directory /workspace/16.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2572926445
Short name T179
Test name
Test status
Simulation time 2042509653 ps
CPU time 5.87 seconds
Started Feb 29 12:45:23 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 204136 kb
Host smart-95305f33-72a2-4fc1-9594-04348bfeca4b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2572926445 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2572926445
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2689775644
Short name T186
Test name
Test status
Simulation time 2710134815 ps
CPU time 5.59 seconds
Started Feb 29 12:45:16 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 204216 kb
Host smart-aa4151d8-eaa8-4562-8ca9-41d312800511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689775644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2689775644
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3153406845
Short name T155
Test name
Test status
Simulation time 17827609 ps
CPU time 0.67 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 203756 kb
Host smart-5ab6f19b-7faf-4a20-9300-2881daa1765e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153406845 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3153406845
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.1073341565
Short name T218
Test name
Test status
Simulation time 393344811 ps
CPU time 2.66 seconds
Started Feb 29 12:45:17 PM PST 24
Finished Feb 29 12:45:21 PM PST 24
Peak memory 204136 kb
Host smart-b7bf2a52-b0b3-4147-992f-2e5b3a72045f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073341565 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.1073341565
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_delayed_resp_sba_tl_access.258573802
Short name T171
Test name
Test status
Simulation time 1131263096 ps
CPU time 2.93 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 204096 kb
Host smart-62b61d93-b452-49d3-88d0-d54bd9dd4216
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=258573802 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_delayed_resp_sba_t
l_access.258573802
Directory /workspace/17.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3890279999
Short name T180
Test name
Test status
Simulation time 3214445096 ps
CPU time 11.85 seconds
Started Feb 29 12:45:47 PM PST 24
Finished Feb 29 12:45:59 PM PST 24
Peak memory 204280 kb
Host smart-93e2fa7d-af0e-4a06-acec-945830218f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890279999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3890279999
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.1950613556
Short name T2
Test name
Test status
Simulation time 18123981 ps
CPU time 0.65 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:45:23 PM PST 24
Peak memory 203776 kb
Host smart-4c421453-dee1-4191-b8c5-5415a3c0ca37
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950613556 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.1950613556
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.2572102174
Short name T204
Test name
Test status
Simulation time 1398169866 ps
CPU time 7.08 seconds
Started Feb 29 12:45:23 PM PST 24
Finished Feb 29 12:45:30 PM PST 24
Peak memory 204084 kb
Host smart-628da5d0-bfe6-4f06-bda7-4a41904d431b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572102174 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.2572102174
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.1668297681
Short name T198
Test name
Test status
Simulation time 3541919690 ps
CPU time 5.89 seconds
Started Feb 29 12:45:22 PM PST 24
Finished Feb 29 12:45:33 PM PST 24
Peak memory 204144 kb
Host smart-bd241fe0-c9f6-41ef-999f-6fc7a8e978fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668297681 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.1668297681
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.1107031000
Short name T169
Test name
Test status
Simulation time 3669888141 ps
CPU time 4.24 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 204136 kb
Host smart-35bb61be-ef94-43a2-8448-47c5728419cb
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1107031000 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_
tl_access.1107031000
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.195304524
Short name T167
Test name
Test status
Simulation time 1558777787 ps
CPU time 3.91 seconds
Started Feb 29 12:45:20 PM PST 24
Finished Feb 29 12:45:24 PM PST 24
Peak memory 204080 kb
Host smart-5d98665a-d20a-41ce-b44d-2afa4a67766c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195304524 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.195304524
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.1665258008
Short name T149
Test name
Test status
Simulation time 23411671 ps
CPU time 0.67 seconds
Started Feb 29 12:45:40 PM PST 24
Finished Feb 29 12:45:41 PM PST 24
Peak memory 203764 kb
Host smart-9daf6894-638b-4a7e-bd6a-4e79b423acf3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665258008 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.1665258008
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.4011464592
Short name T195
Test name
Test status
Simulation time 10834628873 ps
CPU time 6.01 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:31 PM PST 24
Peak memory 203796 kb
Host smart-63b362af-f3ba-4b15-9b72-6e87d9309b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011464592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.4011464592
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.251396905
Short name T168
Test name
Test status
Simulation time 4517870355 ps
CPU time 10.02 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 204180 kb
Host smart-812e29e2-8056-4630-8ed9-6a663608b787
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=251396905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_t
l_access.251396905
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.772678999
Short name T165
Test name
Test status
Simulation time 1576184214 ps
CPU time 3.64 seconds
Started Feb 29 12:45:23 PM PST 24
Finished Feb 29 12:45:27 PM PST 24
Peak memory 204128 kb
Host smart-e1ab508d-ee90-44b2-aecd-6ad7650832b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772678999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.772678999
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3443353333
Short name T178
Test name
Test status
Simulation time 3786924694 ps
CPU time 14.94 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 204128 kb
Host smart-7d10f180-8150-4c70-9bef-353957e7cfbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443353333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3443353333
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.3248579106
Short name T232
Test name
Test status
Simulation time 700778409 ps
CPU time 3.59 seconds
Started Feb 29 12:44:45 PM PST 24
Finished Feb 29 12:44:48 PM PST 24
Peak memory 204060 kb
Host smart-dedec587-23c5-4352-9ff8-2a4856f45736
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3248579106 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.3248579106
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.4266254476
Short name T190
Test name
Test status
Simulation time 89626227 ps
CPU time 0.8 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:49 PM PST 24
Peak memory 203440 kb
Host smart-23903886-c317-494e-87c4-7920afbe22ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266254476 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.4266254476
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.787343618
Short name T170
Test name
Test status
Simulation time 1362282964 ps
CPU time 2.75 seconds
Started Feb 29 12:45:03 PM PST 24
Finished Feb 29 12:45:06 PM PST 24
Peak memory 204156 kb
Host smart-f149828d-6ba9-4e05-bc6d-162be9a50230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787343618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.787343618
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.1985965921
Short name T38
Test name
Test status
Simulation time 270151180 ps
CPU time 1.18 seconds
Started Feb 29 12:45:04 PM PST 24
Finished Feb 29 12:45:06 PM PST 24
Peak memory 220004 kb
Host smart-a1dc4148-ad5d-4d96-810d-94ee8827a0b5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985965921 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.1985965921
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.2025959065
Short name T139
Test name
Test status
Simulation time 48616044 ps
CPU time 0.65 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 203876 kb
Host smart-b89049e4-0add-42e5-b8da-2d3088e41ba2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025959065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.2025959065
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/20.rv_dm_stress_all.3279475718
Short name T5
Test name
Test status
Simulation time 4908925833 ps
CPU time 3.44 seconds
Started Feb 29 12:45:25 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203944 kb
Host smart-0a799bb8-7e98-465c-a364-79e4c50dada0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279475718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_stress_all.3279475718
Directory /workspace/20.rv_dm_stress_all/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1592346654
Short name T135
Test name
Test status
Simulation time 105519851 ps
CPU time 0.66 seconds
Started Feb 29 12:45:40 PM PST 24
Finished Feb 29 12:45:41 PM PST 24
Peak memory 203752 kb
Host smart-9764031b-c519-4820-a481-52f2b3f31fd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592346654 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1592346654
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.910887266
Short name T3
Test name
Test status
Simulation time 222701123 ps
CPU time 0.7 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 203856 kb
Host smart-d71d68cc-9497-43b6-807e-1c45388d492c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910887266 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.910887266
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.2879717123
Short name T79
Test name
Test status
Simulation time 28347089 ps
CPU time 0.63 seconds
Started Feb 29 12:45:28 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203688 kb
Host smart-e6c8d0e7-8753-4155-8747-186e1af37106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879717123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.2879717123
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.300470344
Short name T225
Test name
Test status
Simulation time 17689672 ps
CPU time 0.62 seconds
Started Feb 29 12:45:39 PM PST 24
Finished Feb 29 12:45:41 PM PST 24
Peak memory 203748 kb
Host smart-df131fc7-358c-4fe3-bdf5-4e51dff52a36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300470344 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.300470344
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.3192765937
Short name T116
Test name
Test status
Simulation time 20393816 ps
CPU time 0.68 seconds
Started Feb 29 12:45:50 PM PST 24
Finished Feb 29 12:45:51 PM PST 24
Peak memory 203836 kb
Host smart-375e987b-2bc3-4846-bd92-fda35f06e4cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192765937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.3192765937
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.2412413358
Short name T164
Test name
Test status
Simulation time 18097712 ps
CPU time 0.66 seconds
Started Feb 29 12:45:41 PM PST 24
Finished Feb 29 12:45:43 PM PST 24
Peak memory 203832 kb
Host smart-05ef04f1-475e-426a-8d46-f7b774726219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412413358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.2412413358
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.4092090981
Short name T36
Test name
Test status
Simulation time 28810078 ps
CPU time 0.66 seconds
Started Feb 29 12:45:14 PM PST 24
Finished Feb 29 12:45:15 PM PST 24
Peak memory 203784 kb
Host smart-aeed8e2e-1635-4975-a8f3-f156551b8069
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092090981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.4092090981
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.449413364
Short name T51
Test name
Test status
Simulation time 17113549 ps
CPU time 0.66 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:19 PM PST 24
Peak memory 203808 kb
Host smart-f1613ae8-9b58-4bce-aedf-a7c067038037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449413364 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.449413364
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.693071086
Short name T153
Test name
Test status
Simulation time 51090036 ps
CPU time 0.64 seconds
Started Feb 29 12:45:14 PM PST 24
Finished Feb 29 12:45:15 PM PST 24
Peak memory 203776 kb
Host smart-8fef61b1-7be8-44f8-ab12-45fc8facd44c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693071086 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.693071086
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.1514820580
Short name T52
Test name
Test status
Simulation time 24273041 ps
CPU time 0.68 seconds
Started Feb 29 12:45:02 PM PST 24
Finished Feb 29 12:45:03 PM PST 24
Peak memory 203852 kb
Host smart-1fb45a45-2ac2-4b98-a11a-4a53c13ac907
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514820580 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.1514820580
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_autoincr_sba_tl_access.1104338111
Short name T20
Test name
Test status
Simulation time 41055726575 ps
CPU time 127.76 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:46:55 PM PST 24
Peak memory 204148 kb
Host smart-a9d96303-c462-4c9d-942f-2f1bc24a6c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104338111 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_autoincr_sba_tl_access.1104338111
Directory /workspace/3.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_bad_sba_tl_access.2824513160
Short name T119
Test name
Test status
Simulation time 1763674959 ps
CPU time 6.2 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:50 PM PST 24
Peak memory 204116 kb
Host smart-143abafb-472b-4fd7-82fe-4381f54c8444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824513160 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_bad_sba_tl_access.2824513160
Directory /workspace/3.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.1395940371
Short name T196
Test name
Test status
Simulation time 5930716990 ps
CPU time 6.14 seconds
Started Feb 29 12:44:49 PM PST 24
Finished Feb 29 12:44:56 PM PST 24
Peak memory 204144 kb
Host smart-cfc2d14d-0792-47fb-9e8b-7e3c791229d9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1395940371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.1395940371
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.1037044169
Short name T181
Test name
Test status
Simulation time 24850422 ps
CPU time 0.66 seconds
Started Feb 29 12:45:03 PM PST 24
Finished Feb 29 12:45:04 PM PST 24
Peak memory 203508 kb
Host smart-8ba31b73-be56-4230-97d8-dc26d2e0fc86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037044169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.1037044169
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.1407935788
Short name T11
Test name
Test status
Simulation time 2708666409 ps
CPU time 4.55 seconds
Started Feb 29 12:45:06 PM PST 24
Finished Feb 29 12:45:11 PM PST 24
Peak memory 204144 kb
Host smart-59a8c478-928c-4cfa-a9c3-69643c6cb92d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407935788 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.1407935788
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3218930334
Short name T68
Test name
Test status
Simulation time 331399202 ps
CPU time 1.31 seconds
Started Feb 29 12:45:04 PM PST 24
Finished Feb 29 12:45:05 PM PST 24
Peak memory 220028 kb
Host smart-7cd7568a-2696-4f3c-b63e-f4b335657d30
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218930334 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3218930334
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.3562756817
Short name T136
Test name
Test status
Simulation time 24833555 ps
CPU time 0.67 seconds
Started Feb 29 12:45:15 PM PST 24
Finished Feb 29 12:45:17 PM PST 24
Peak memory 203784 kb
Host smart-674a34df-7d35-4cc5-a3e9-dbadc2d7d0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562756817 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.3562756817
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.559181102
Short name T115
Test name
Test status
Simulation time 24843260 ps
CPU time 0.68 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:21 PM PST 24
Peak memory 203856 kb
Host smart-ac1dfbdd-9190-44c0-8c11-5f7a91061ed5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559181102 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.559181102
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.134427996
Short name T134
Test name
Test status
Simulation time 28135176 ps
CPU time 0.7 seconds
Started Feb 29 12:45:20 PM PST 24
Finished Feb 29 12:45:21 PM PST 24
Peak memory 203768 kb
Host smart-1906f15a-c2e4-42ac-9cbb-3edfab68cf06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134427996 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.134427996
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3245265924
Short name T152
Test name
Test status
Simulation time 53549073 ps
CPU time 0.65 seconds
Started Feb 29 12:46:10 PM PST 24
Finished Feb 29 12:46:11 PM PST 24
Peak memory 203752 kb
Host smart-312855bb-5d8a-4bcc-ba33-8c7736dbbe6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245265924 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3245265924
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1959070067
Short name T162
Test name
Test status
Simulation time 17966877 ps
CPU time 0.69 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 203812 kb
Host smart-6a26d38e-376e-47f8-abad-d7072d264a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959070067 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1959070067
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.1719387660
Short name T159
Test name
Test status
Simulation time 25949876 ps
CPU time 0.67 seconds
Started Feb 29 12:45:35 PM PST 24
Finished Feb 29 12:45:36 PM PST 24
Peak memory 203764 kb
Host smart-5e1a304e-44ba-471f-8796-575dc5823dca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719387660 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.1719387660
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.878598691
Short name T189
Test name
Test status
Simulation time 22745146 ps
CPU time 0.71 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 203804 kb
Host smart-6f199974-dd2b-4b93-bf7e-84c7d45589cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878598691 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.878598691
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.1587721128
Short name T161
Test name
Test status
Simulation time 175087488 ps
CPU time 0.67 seconds
Started Feb 29 12:45:26 PM PST 24
Finished Feb 29 12:45:27 PM PST 24
Peak memory 203784 kb
Host smart-7caec482-9f10-4612-be78-15de1a33d5f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587721128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.1587721128
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.944570636
Short name T137
Test name
Test status
Simulation time 55035941 ps
CPU time 0.69 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 203856 kb
Host smart-b2ba6f28-9a96-4ea4-8f9e-f2ed689478b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944570636 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.944570636
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2479495169
Short name T53
Test name
Test status
Simulation time 66416751 ps
CPU time 0.63 seconds
Started Feb 29 12:45:01 PM PST 24
Finished Feb 29 12:45:02 PM PST 24
Peak memory 203796 kb
Host smart-0a6a1e95-4ab9-4121-b867-b2a74ab3ef25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479495169 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2479495169
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_autoincr_sba_tl_access.3087385396
Short name T192
Test name
Test status
Simulation time 14463565439 ps
CPU time 47.28 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:45:31 PM PST 24
Peak memory 204208 kb
Host smart-4004c136-b634-4b16-a693-41fcff33ffa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087385396 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_autoincr_sba_tl_access.3087385396
Directory /workspace/4.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1324553299
Short name T229
Test name
Test status
Simulation time 6910452933 ps
CPU time 17.34 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:45:15 PM PST 24
Peak memory 204124 kb
Host smart-03eafec9-034f-4c74-b80c-e1a3e09a82b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324553299 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1324553299
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.970629574
Short name T191
Test name
Test status
Simulation time 7174515017 ps
CPU time 13.2 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:45:00 PM PST 24
Peak memory 204112 kb
Host smart-b885f69b-74ee-4608-b5e5-1419f48b41c1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=970629574 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_tl
_access.970629574
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.566487716
Short name T223
Test name
Test status
Simulation time 71649987 ps
CPU time 0.7 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 203364 kb
Host smart-91c93c2f-a05f-466e-bb70-86e119d59f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566487716 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.566487716
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.4154116296
Short name T85
Test name
Test status
Simulation time 292188196 ps
CPU time 0.96 seconds
Started Feb 29 12:44:44 PM PST 24
Finished Feb 29 12:44:45 PM PST 24
Peak memory 204096 kb
Host smart-29fcf0d0-d5e5-40ad-bb9f-a219256f316f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154116296 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.4154116296
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3622617876
Short name T67
Test name
Test status
Simulation time 341135343 ps
CPU time 1.32 seconds
Started Feb 29 12:45:08 PM PST 24
Finished Feb 29 12:45:09 PM PST 24
Peak memory 219848 kb
Host smart-6bc33a52-c5ee-40fb-9ff1-e38d2a5bec50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622617876 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3622617876
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2043049672
Short name T163
Test name
Test status
Simulation time 45075108 ps
CPU time 0.69 seconds
Started Feb 29 12:45:28 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203692 kb
Host smart-596ade9c-7af0-419f-ba17-e1e5476ac049
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2043049672 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2043049672
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.1814047245
Short name T146
Test name
Test status
Simulation time 29890694 ps
CPU time 0.68 seconds
Started Feb 29 12:45:27 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203792 kb
Host smart-0833de8f-d7fa-4588-8fd9-19813f518588
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814047245 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.1814047245
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.347737781
Short name T148
Test name
Test status
Simulation time 25425047 ps
CPU time 0.69 seconds
Started Feb 29 12:45:27 PM PST 24
Finished Feb 29 12:45:29 PM PST 24
Peak memory 203800 kb
Host smart-42df27f0-d2aa-4f6c-8eb8-9eb966bae1ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347737781 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.347737781
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.53980083
Short name T1
Test name
Test status
Simulation time 57195929 ps
CPU time 0.67 seconds
Started Feb 29 12:45:26 PM PST 24
Finished Feb 29 12:45:28 PM PST 24
Peak memory 203740 kb
Host smart-778948ee-a154-4ca0-bdf0-be933e31dee3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53980083 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.53980083
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.351542131
Short name T215
Test name
Test status
Simulation time 20630642 ps
CPU time 0.67 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:19 PM PST 24
Peak memory 203792 kb
Host smart-3fe9792c-9a84-4456-825f-0536910c2572
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351542131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.351542131
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_stress_all.4139425774
Short name T19
Test name
Test status
Simulation time 1891327807 ps
CPU time 6.79 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:25 PM PST 24
Peak memory 203996 kb
Host smart-0fc7c193-bedf-4f74-82f8-3e93d69b0c29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139425774 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_stress_all.4139425774
Directory /workspace/44.rv_dm_stress_all/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.604497166
Short name T138
Test name
Test status
Simulation time 44021761 ps
CPU time 0.64 seconds
Started Feb 29 12:45:16 PM PST 24
Finished Feb 29 12:45:17 PM PST 24
Peak memory 203856 kb
Host smart-a24e49a5-c952-47e3-9ee6-9b9cdf3046a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=604497166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.604497166
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2566962099
Short name T160
Test name
Test status
Simulation time 51048289 ps
CPU time 0.73 seconds
Started Feb 29 12:45:17 PM PST 24
Finished Feb 29 12:45:18 PM PST 24
Peak memory 203812 kb
Host smart-fb63bca7-f25b-4038-bce6-f35d1777ac38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566962099 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2566962099
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.211987057
Short name T154
Test name
Test status
Simulation time 38946558 ps
CPU time 0.64 seconds
Started Feb 29 12:45:21 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 203856 kb
Host smart-12247238-8149-4a26-80bf-943dd5c67c56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211987057 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.211987057
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.3887993355
Short name T200
Test name
Test status
Simulation time 40719900 ps
CPU time 0.63 seconds
Started Feb 29 12:45:29 PM PST 24
Finished Feb 29 12:45:30 PM PST 24
Peak memory 203772 kb
Host smart-15b92b96-3153-4abd-a7f8-9ecad7bd00d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887993355 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.3887993355
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.2919658566
Short name T166
Test name
Test status
Simulation time 55634352 ps
CPU time 0.67 seconds
Started Feb 29 12:45:24 PM PST 24
Finished Feb 29 12:45:24 PM PST 24
Peak memory 203836 kb
Host smart-f8153084-c530-4e0a-ba1e-ae6dbc65a2ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919658566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.2919658566
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.1131963340
Short name T50
Test name
Test status
Simulation time 17129353 ps
CPU time 0.78 seconds
Started Feb 29 12:45:02 PM PST 24
Finished Feb 29 12:45:03 PM PST 24
Peak memory 203792 kb
Host smart-c7647ed7-32d0-4f4c-896d-fc40a15a76db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131963340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.1131963340
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_autoincr_sba_tl_access.2229564557
Short name T220
Test name
Test status
Simulation time 15724984332 ps
CPU time 61.17 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:45:49 PM PST 24
Peak memory 204240 kb
Host smart-3c817939-c033-42f0-aba5-feb97a32dc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229564557 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_autoincr_sba_tl_access.2229564557
Directory /workspace/5.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.1534400692
Short name T118
Test name
Test status
Simulation time 3612481137 ps
CPU time 12.27 seconds
Started Feb 29 12:44:58 PM PST 24
Finished Feb 29 12:45:10 PM PST 24
Peak memory 204196 kb
Host smart-ae3554a7-9ee7-4cad-8816-da3817cf49b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534400692 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.1534400692
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.3604045520
Short name T199
Test name
Test status
Simulation time 7255702794 ps
CPU time 24.84 seconds
Started Feb 29 12:45:05 PM PST 24
Finished Feb 29 12:45:30 PM PST 24
Peak memory 204256 kb
Host smart-f188ec3c-155c-4b7d-bc9e-4bee55155882
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604045520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.3604045520
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.17803758
Short name T201
Test name
Test status
Simulation time 1418122345 ps
CPU time 3.39 seconds
Started Feb 29 12:44:55 PM PST 24
Finished Feb 29 12:44:59 PM PST 24
Peak memory 204072 kb
Host smart-93e459c6-b01d-4bf0-b7d2-831ecc746d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17803758 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.17803758
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.1409074732
Short name T156
Test name
Test status
Simulation time 61222418 ps
CPU time 0.65 seconds
Started Feb 29 12:44:53 PM PST 24
Finished Feb 29 12:44:53 PM PST 24
Peak memory 203752 kb
Host smart-fed1cf14-62a1-43c4-b48e-bdef66d4cd33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409074732 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.1409074732
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.648027894
Short name T205
Test name
Test status
Simulation time 1453119093 ps
CPU time 4.7 seconds
Started Feb 29 12:44:46 PM PST 24
Finished Feb 29 12:44:51 PM PST 24
Peak memory 204036 kb
Host smart-142d109b-8cb4-4675-870d-9c9a97ba0117
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=648027894 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_tl
_access.648027894
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.4236071036
Short name T188
Test name
Test status
Simulation time 3545454126 ps
CPU time 7.99 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:55 PM PST 24
Peak memory 204084 kb
Host smart-53f1c5b7-1145-4967-95fc-024bfeda6607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236071036 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.4236071036
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.2411028693
Short name T144
Test name
Test status
Simulation time 18109278 ps
CPU time 0.68 seconds
Started Feb 29 12:45:19 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 203752 kb
Host smart-e1086dd7-beb5-4267-82ce-648dd50158b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411028693 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.2411028693
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.1881362201
Short name T209
Test name
Test status
Simulation time 6019220739 ps
CPU time 7.48 seconds
Started Feb 29 12:44:47 PM PST 24
Finished Feb 29 12:44:55 PM PST 24
Peak memory 204160 kb
Host smart-4af465f7-ff6e-4c39-9aea-0ac4723ddf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881362201 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.1881362201
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.564663810
Short name T219
Test name
Test status
Simulation time 4942372649 ps
CPU time 16.23 seconds
Started Feb 29 12:44:51 PM PST 24
Finished Feb 29 12:45:08 PM PST 24
Peak memory 204088 kb
Host smart-ba700cda-f12f-4d01-8039-9363dd16a52d
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564663810 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_tl
_access.564663810
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.148709641
Short name T177
Test name
Test status
Simulation time 4937304694 ps
CPU time 16.46 seconds
Started Feb 29 12:44:48 PM PST 24
Finished Feb 29 12:45:05 PM PST 24
Peak memory 204152 kb
Host smart-0e46f8f2-624d-4c75-9f74-24867d8ec2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148709641 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.148709641
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.1442686407
Short name T114
Test name
Test status
Simulation time 31225367 ps
CPU time 0.65 seconds
Started Feb 29 12:45:17 PM PST 24
Finished Feb 29 12:45:19 PM PST 24
Peak memory 203784 kb
Host smart-f84fa5cc-448b-4a78-8882-4b7f9665d9d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442686407 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.1442686407
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.464392284
Short name T228
Test name
Test status
Simulation time 3694884252 ps
CPU time 7.15 seconds
Started Feb 29 12:45:13 PM PST 24
Finished Feb 29 12:45:20 PM PST 24
Peak memory 204136 kb
Host smart-43ad4487-8a92-48f2-83c7-f57a864c796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464392284 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.464392284
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.2908749072
Short name T173
Test name
Test status
Simulation time 1306523396 ps
CPU time 1.93 seconds
Started Feb 29 12:45:13 PM PST 24
Finished Feb 29 12:45:15 PM PST 24
Peak memory 204216 kb
Host smart-7df1f4fd-301e-4c0f-b4fe-10e3913c1a62
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2908749072 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.2908749072
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.1787029826
Short name T172
Test name
Test status
Simulation time 1760843531 ps
CPU time 4.28 seconds
Started Feb 29 12:45:11 PM PST 24
Finished Feb 29 12:45:15 PM PST 24
Peak memory 204044 kb
Host smart-a3024bfc-a027-47f6-b17d-5d6234c41d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787029826 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.1787029826
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.1124973358
Short name T158
Test name
Test status
Simulation time 42944035 ps
CPU time 0.67 seconds
Started Feb 29 12:45:18 PM PST 24
Finished Feb 29 12:45:19 PM PST 24
Peak memory 203872 kb
Host smart-5f73ad95-7b55-4719-87cb-91c8ce33ea11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124973358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.1124973358
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.651260039
Short name T88
Test name
Test status
Simulation time 1127774477 ps
CPU time 4.34 seconds
Started Feb 29 12:45:17 PM PST 24
Finished Feb 29 12:45:21 PM PST 24
Peak memory 204204 kb
Host smart-445d45e9-0c82-4d53-a862-b70d78586446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651260039 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.651260039
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3969411955
Short name T183
Test name
Test status
Simulation time 3726702533 ps
CPU time 5.74 seconds
Started Feb 29 12:45:16 PM PST 24
Finished Feb 29 12:45:22 PM PST 24
Peak memory 204140 kb
Host smart-f32600ef-7250-4382-80b1-567da3552656
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3969411955 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3969411955
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3883932389
Short name T182
Test name
Test status
Simulation time 1183184893 ps
CPU time 2.07 seconds
Started Feb 29 12:45:11 PM PST 24
Finished Feb 29 12:45:13 PM PST 24
Peak memory 204076 kb
Host smart-903bd0c0-8144-4c2d-a55e-072f265f6f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3883932389 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3883932389
Directory /workspace/9.rv_dm_sba_tl_access/latest
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