Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
87.93 93.06 79.65 89.36 76.92 83.42 97.75 95.34


Total test records in report: 376
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html
T95 /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.483685997 Mar 03 12:38:17 PM PST 24 Mar 03 12:38:21 PM PST 24 314072896 ps
T274 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3779912521 Mar 03 12:38:43 PM PST 24 Mar 03 12:38:44 PM PST 24 929735267 ps
T97 /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3314612626 Mar 03 12:38:15 PM PST 24 Mar 03 12:38:18 PM PST 24 113342686 ps
T275 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4183146256 Mar 03 12:38:18 PM PST 24 Mar 03 12:38:21 PM PST 24 844686957 ps
T276 /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.535072809 Mar 03 12:38:31 PM PST 24 Mar 03 12:38:34 PM PST 24 725769240 ps
T98 /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.278474965 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:44 PM PST 24 321157304 ps
T277 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2079870552 Mar 03 12:38:19 PM PST 24 Mar 03 12:38:20 PM PST 24 50527976 ps
T126 /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2757702477 Mar 03 12:38:18 PM PST 24 Mar 03 12:38:33 PM PST 24 726049747 ps
T278 /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2669669759 Mar 03 12:38:51 PM PST 24 Mar 03 12:38:52 PM PST 24 104122472 ps
T105 /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.365088439 Mar 03 12:38:52 PM PST 24 Mar 03 12:39:00 PM PST 24 1696636451 ps
T118 /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.537379280 Mar 03 12:38:53 PM PST 24 Mar 03 12:39:15 PM PST 24 7396173084 ps
T279 /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.675839963 Mar 03 12:38:43 PM PST 24 Mar 03 12:38:43 PM PST 24 52473842 ps
T280 /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4075866270 Mar 03 12:38:14 PM PST 24 Mar 03 12:38:17 PM PST 24 1261730291 ps
T99 /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1966839598 Mar 03 12:38:17 PM PST 24 Mar 03 12:38:19 PM PST 24 1519113116 ps
T106 /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.590034866 Mar 03 12:38:32 PM PST 24 Mar 03 12:38:40 PM PST 24 2719426798 ps
T281 /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2009360293 Mar 03 12:38:26 PM PST 24 Mar 03 12:38:30 PM PST 24 1542609014 ps
T282 /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2606236990 Mar 03 12:38:32 PM PST 24 Mar 03 12:38:33 PM PST 24 28104520 ps
T100 /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1794855560 Mar 03 12:38:19 PM PST 24 Mar 03 12:39:26 PM PST 24 1138029949 ps
T283 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3765088167 Mar 03 12:38:35 PM PST 24 Mar 03 12:38:37 PM PST 24 428801913 ps
T284 /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4292178189 Mar 03 12:38:53 PM PST 24 Mar 03 12:38:57 PM PST 24 756171182 ps
T285 /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.151873171 Mar 03 12:38:52 PM PST 24 Mar 03 12:39:16 PM PST 24 22073794729 ps
T122 /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1163493897 Mar 03 12:38:40 PM PST 24 Mar 03 12:39:00 PM PST 24 1572317286 ps
T101 /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.843838477 Mar 03 12:38:15 PM PST 24 Mar 03 12:39:24 PM PST 24 1290739526 ps
T286 /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1619919864 Mar 03 12:38:17 PM PST 24 Mar 03 12:38:20 PM PST 24 60576127 ps
T287 /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3055691520 Mar 03 12:38:43 PM PST 24 Mar 03 12:38:44 PM PST 24 294102053 ps
T288 /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3108977301 Mar 03 12:38:50 PM PST 24 Mar 03 12:38:54 PM PST 24 61975263 ps
T289 /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1788247796 Mar 03 12:38:14 PM PST 24 Mar 03 12:38:17 PM PST 24 1253618712 ps
T102 /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.65175128 Mar 03 12:38:23 PM PST 24 Mar 03 12:38:25 PM PST 24 1582852810 ps
T290 /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3533113035 Mar 03 12:38:51 PM PST 24 Mar 03 12:38:54 PM PST 24 341946102 ps
T107 /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2521918293 Mar 03 12:38:16 PM PST 24 Mar 03 12:38:24 PM PST 24 812276080 ps
T291 /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3303725289 Mar 03 12:38:18 PM PST 24 Mar 03 12:38:19 PM PST 24 50851472 ps
T292 /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4050602343 Mar 03 12:38:31 PM PST 24 Mar 03 12:38:35 PM PST 24 153961881 ps
T108 /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.37999280 Mar 03 12:38:31 PM PST 24 Mar 03 12:38:35 PM PST 24 161540610 ps
T293 /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.326063909 Mar 03 12:38:51 PM PST 24 Mar 03 12:38:56 PM PST 24 126862168 ps
T109 /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3206327769 Mar 03 12:38:35 PM PST 24 Mar 03 12:38:42 PM PST 24 535261448 ps
T294 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1947224872 Mar 03 12:38:44 PM PST 24 Mar 03 12:38:47 PM PST 24 846477513 ps
T295 /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.1856545785 Mar 03 12:38:41 PM PST 24 Mar 03 12:39:21 PM PST 24 11930690626 ps
T296 /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3241872311 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:42 PM PST 24 50415737 ps
T297 /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1785300365 Mar 03 12:38:22 PM PST 24 Mar 03 12:38:22 PM PST 24 34303471 ps
T298 /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2103256702 Mar 03 12:38:18 PM PST 24 Mar 03 12:38:20 PM PST 24 185344814 ps
T299 /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1225727846 Mar 03 12:38:14 PM PST 24 Mar 03 12:38:20 PM PST 24 1096607605 ps
T300 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3655745777 Mar 03 12:38:15 PM PST 24 Mar 03 12:38:36 PM PST 24 9011913098 ps
T301 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2447506525 Mar 03 12:38:18 PM PST 24 Mar 03 12:38:20 PM PST 24 593617817 ps
T302 /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2315066642 Mar 03 12:38:44 PM PST 24 Mar 03 12:38:45 PM PST 24 32896362 ps
T303 /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1696169314 Mar 03 12:38:15 PM PST 24 Mar 03 12:38:42 PM PST 24 1177476599 ps
T304 /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2086689650 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:48 PM PST 24 1032346797 ps
T305 /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3600166541 Mar 03 12:38:29 PM PST 24 Mar 03 12:38:34 PM PST 24 242195906 ps
T123 /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2711065715 Mar 03 12:38:26 PM PST 24 Mar 03 12:38:41 PM PST 24 2731933537 ps
T127 /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1401076211 Mar 03 12:38:33 PM PST 24 Mar 03 12:38:51 PM PST 24 2128465003 ps
T103 /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3640177685 Mar 03 12:38:10 PM PST 24 Mar 03 12:38:42 PM PST 24 6864094287 ps
T306 /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.69078294 Mar 03 12:38:29 PM PST 24 Mar 03 12:38:37 PM PST 24 257867016 ps
T124 /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2460736220 Mar 03 12:38:35 PM PST 24 Mar 03 12:38:52 PM PST 24 570840630 ps
T307 /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.196558498 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:43 PM PST 24 89094017 ps
T308 /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.764030734 Mar 03 12:38:33 PM PST 24 Mar 03 12:38:34 PM PST 24 71658059 ps
T309 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2981307371 Mar 03 12:38:18 PM PST 24 Mar 03 12:39:01 PM PST 24 14573301851 ps
T310 /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2916536626 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:44 PM PST 24 51544054 ps
T311 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1065105352 Mar 03 12:38:54 PM PST 24 Mar 03 12:38:55 PM PST 24 191026563 ps
T312 /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1972847815 Mar 03 12:38:36 PM PST 24 Mar 03 12:38:42 PM PST 24 265631769 ps
T313 /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.226535078 Mar 03 12:38:34 PM PST 24 Mar 03 12:38:35 PM PST 24 85999036 ps
T314 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4063547582 Mar 03 12:37:44 PM PST 24 Mar 03 12:37:46 PM PST 24 367943962 ps
T315 /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.150978997 Mar 03 12:38:17 PM PST 24 Mar 03 12:38:40 PM PST 24 34902759382 ps
T316 /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.935423293 Mar 03 12:38:29 PM PST 24 Mar 03 12:38:37 PM PST 24 480341934 ps
T317 /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3414687583 Mar 03 12:38:54 PM PST 24 Mar 03 12:39:16 PM PST 24 20918596851 ps
T129 /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3023579564 Mar 03 12:38:35 PM PST 24 Mar 03 12:38:53 PM PST 24 3800621444 ps
T318 /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3847376122 Mar 03 12:38:14 PM PST 24 Mar 03 12:38:19 PM PST 24 1801074009 ps
T319 /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1726193449 Mar 03 12:38:35 PM PST 24 Mar 03 12:38:36 PM PST 24 17504593 ps
T320 /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.3912394141 Mar 03 12:38:51 PM PST 24 Mar 03 12:39:05 PM PST 24 15071591508 ps
T321 /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.26754798 Mar 03 12:38:50 PM PST 24 Mar 03 12:38:53 PM PST 24 1474020488 ps
T96 /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3738691483 Mar 03 12:38:53 PM PST 24 Mar 03 12:39:00 PM PST 24 1688508289 ps
T322 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3074257327 Mar 03 12:38:22 PM PST 24 Mar 03 12:38:50 PM PST 24 13655393182 ps
T323 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.158409488 Mar 03 12:38:22 PM PST 24 Mar 03 12:38:22 PM PST 24 89763450 ps
T324 /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2919891634 Mar 03 12:38:16 PM PST 24 Mar 03 12:38:18 PM PST 24 82499397 ps
T325 /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.396071208 Mar 03 12:37:57 PM PST 24 Mar 03 12:37:58 PM PST 24 110418219 ps
T326 /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1619591256 Mar 03 12:38:24 PM PST 24 Mar 03 12:38:26 PM PST 24 172261498 ps
T327 /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3409379172 Mar 03 12:38:09 PM PST 24 Mar 03 12:38:14 PM PST 24 474912856 ps
T328 /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.616663744 Mar 03 12:37:59 PM PST 24 Mar 03 12:38:27 PM PST 24 7014290088 ps
T329 /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3205826239 Mar 03 12:38:26 PM PST 24 Mar 03 12:38:31 PM PST 24 818498210 ps
T330 /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4003869544 Mar 03 12:38:19 PM PST 24 Mar 03 12:38:20 PM PST 24 20952786 ps
T331 /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.97089819 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:46 PM PST 24 1996874344 ps
T332 /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4003611456 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:47 PM PST 24 472745203 ps
T333 /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1136689544 Mar 03 12:37:59 PM PST 24 Mar 03 12:38:04 PM PST 24 50617666 ps
T334 /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.871879626 Mar 03 12:38:53 PM PST 24 Mar 03 12:39:17 PM PST 24 13444081779 ps
T335 /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.727967519 Mar 03 12:38:33 PM PST 24 Mar 03 12:38:37 PM PST 24 256367622 ps
T336 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.871511638 Mar 03 12:38:38 PM PST 24 Mar 03 12:38:40 PM PST 24 94245270 ps
T337 /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3228936217 Mar 03 12:38:02 PM PST 24 Mar 03 12:40:09 PM PST 24 38282782270 ps
T338 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1991722973 Mar 03 12:38:34 PM PST 24 Mar 03 12:38:36 PM PST 24 732492907 ps
T339 /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1970090697 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:44 PM PST 24 378295619 ps
T340 /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.120522136 Mar 03 12:38:21 PM PST 24 Mar 03 12:38:22 PM PST 24 502040573 ps
T341 /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3993047949 Mar 03 12:38:23 PM PST 24 Mar 03 12:38:28 PM PST 24 138203593 ps
T342 /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2132160733 Mar 03 12:38:40 PM PST 24 Mar 03 12:38:49 PM PST 24 1576964756 ps
T130 /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.382453877 Mar 03 12:38:40 PM PST 24 Mar 03 12:38:49 PM PST 24 1706756620 ps
T343 /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.191789849 Mar 03 12:38:06 PM PST 24 Mar 03 12:38:12 PM PST 24 826550522 ps
T344 /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1865008139 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:45 PM PST 24 1521290521 ps
T345 /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1965188987 Mar 03 12:38:50 PM PST 24 Mar 03 12:39:10 PM PST 24 6141361381 ps
T346 /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2931638461 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:46 PM PST 24 595552655 ps
T347 /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.266461794 Mar 03 12:38:22 PM PST 24 Mar 03 12:38:31 PM PST 24 872604034 ps
T348 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4217755237 Mar 03 12:38:36 PM PST 24 Mar 03 12:38:38 PM PST 24 68710473 ps
T349 /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4109873408 Mar 03 12:38:50 PM PST 24 Mar 03 12:39:01 PM PST 24 2080908844 ps
T350 /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.3419378249 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:59 PM PST 24 4861899650 ps
T119 /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.245453024 Mar 03 12:38:30 PM PST 24 Mar 03 12:38:36 PM PST 24 263616735 ps
T351 /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1603350404 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:45 PM PST 24 114871489 ps
T352 /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4012056507 Mar 03 12:38:32 PM PST 24 Mar 03 12:38:35 PM PST 24 135988340 ps
T353 /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2062298359 Mar 03 12:38:27 PM PST 24 Mar 03 12:38:30 PM PST 24 213687433 ps
T354 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1119179166 Mar 03 12:38:22 PM PST 24 Mar 03 12:38:29 PM PST 24 3219347261 ps
T355 /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.392793968 Mar 03 12:38:52 PM PST 24 Mar 03 12:38:57 PM PST 24 422200737 ps
T356 /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.862853460 Mar 03 12:37:47 PM PST 24 Mar 03 12:37:56 PM PST 24 504755138 ps
T357 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3394232943 Mar 03 12:38:11 PM PST 24 Mar 03 12:38:12 PM PST 24 70777882 ps
T358 /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.635480625 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:49 PM PST 24 4180095038 ps
T359 /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2456333242 Mar 03 12:38:53 PM PST 24 Mar 03 12:38:56 PM PST 24 314748272 ps
T360 /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1158969733 Mar 03 12:38:14 PM PST 24 Mar 03 12:38:19 PM PST 24 4830423751 ps
T361 /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1672772564 Mar 03 12:38:41 PM PST 24 Mar 03 12:38:47 PM PST 24 597459353 ps
T362 /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3576830583 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:48 PM PST 24 3637715868 ps
T363 /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1913337999 Mar 03 12:38:34 PM PST 24 Mar 03 12:38:37 PM PST 24 636121348 ps
T364 /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.808610981 Mar 03 12:38:34 PM PST 24 Mar 03 12:38:35 PM PST 24 247005543 ps
T365 /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.2061375568 Mar 03 12:38:52 PM PST 24 Mar 03 12:39:14 PM PST 24 23389931666 ps
T366 /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3463218246 Mar 03 12:38:30 PM PST 24 Mar 03 12:38:34 PM PST 24 109584598 ps
T367 /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1212673693 Mar 03 12:38:49 PM PST 24 Mar 03 12:39:15 PM PST 24 13779825056 ps
T368 /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3150650617 Mar 03 12:38:12 PM PST 24 Mar 03 12:38:16 PM PST 24 1417290630 ps
T369 /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3713681907 Mar 03 12:38:42 PM PST 24 Mar 03 12:38:43 PM PST 24 31381186 ps
T370 /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3179702369 Mar 03 12:38:42 PM PST 24 Mar 03 12:39:01 PM PST 24 1699596781 ps
T371 /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1935963597 Mar 03 12:38:52 PM PST 24 Mar 03 12:38:56 PM PST 24 181831619 ps
T372 /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2667782941 Mar 03 12:38:39 PM PST 24 Mar 03 12:38:44 PM PST 24 3624023166 ps
T373 /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2383364065 Mar 03 12:38:15 PM PST 24 Mar 03 12:38:17 PM PST 24 148528950 ps
T374 /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2369691469 Mar 03 12:38:34 PM PST 24 Mar 03 12:38:34 PM PST 24 111865142 ps
T375 /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.555253491 Mar 03 12:38:36 PM PST 24 Mar 03 12:38:39 PM PST 24 370475032 ps
T376 /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1528160441 Mar 03 12:38:38 PM PST 24 Mar 03 12:38:41 PM PST 24 64337025 ps

Test location /workspace/coverage/default/23.rv_dm_stress_all.583779970
Short name T4
Test name
Test status
Simulation time 824769939 ps
CPU time 3.29 seconds
Started Mar 03 12:34:36 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 203840 kb
Host smart-b4b1e40a-4780-4deb-819a-269a6ff3ba34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583779970 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_stress_all.583779970
Directory /workspace/23.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_errors.2498738583
Short name T75
Test name
Test status
Simulation time 375273073 ps
CPU time 5.37 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:58 PM PST 24
Peak memory 212612 kb
Host smart-f5dd6d8c-9521-4ae3-a266-d77e15335ed8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498738583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_errors.2498738583
Directory /workspace/19.rv_dm_tl_errors/latest

Test location /workspace/coverage/default/13.rv_dm_autoincr_sba_tl_access.4022278966
Short name T14
Test name
Test status
Simulation time 4193790934 ps
CPU time 8.63 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 204060 kb
Host smart-3e6b68c9-e8f0-4e17-966a-0ae81e9a1e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022278966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_autoincr_sba_tl_access.4022278966
Directory /workspace/13.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tap_fsm_rand_reset.3566124527
Short name T53
Test name
Test status
Simulation time 11255882433 ps
CPU time 39.25 seconds
Started Mar 03 12:38:01 PM PST 24
Finished Mar 03 12:38:40 PM PST 24
Peak memory 230088 kb
Host smart-e9e4f062-84f2-45e6-89c5-6f8235f465a4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566124527 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rv_dm_tap_fsm_rand_reset.3566124527
Directory /workspace/1.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/default/1.rv_dm_alert_test.2281236708
Short name T48
Test name
Test status
Simulation time 22616345 ps
CPU time 0.65 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:12 PM PST 24
Peak memory 203688 kb
Host smart-fecc64ed-0e58-43b5-8a4d-9c8a4d097b34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281236708 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_alert_test.2281236708
Directory /workspace/1.rv_dm_alert_test/latest

Test location /workspace/coverage/default/1.rv_dm_stress_all.3806276490
Short name T25
Test name
Test status
Simulation time 917214573 ps
CPU time 2.67 seconds
Started Mar 03 12:34:20 PM PST 24
Finished Mar 03 12:34:23 PM PST 24
Peak memory 203788 kb
Host smart-b1c5b9b7-c194-4149-9a58-8aff5fbe919a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806276490 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_stress_all.3806276490
Directory /workspace/1.rv_dm_stress_all/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_intg_err.1271085583
Short name T38
Test name
Test status
Simulation time 4317087365 ps
CPU time 19.76 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:38 PM PST 24
Peak memory 218696 kb
Host smart-5d4d984b-055f-4cea-80c2-703fe04a2ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271085583 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_intg_err.1271085583
Directory /workspace/3.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_busy.3092956331
Short name T10
Test name
Test status
Simulation time 2080487286 ps
CPU time 7.48 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:15 PM PST 24
Peak memory 203832 kb
Host smart-8ba3f7ed-0f96-4adf-84e1-2eec77f367d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092956331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_busy.3092956331
Directory /workspace/1.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_aliasing.1794855560
Short name T100
Test name
Test status
Simulation time 1138029949 ps
CPU time 66.38 seconds
Started Mar 03 12:38:19 PM PST 24
Finished Mar 03 12:39:26 PM PST 24
Peak memory 204432 kb
Host smart-dea4c3c7-c24d-436b-a050-fa67081e04fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794855560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 2.rv_dm_csr_aliasing.1794855560
Directory /workspace/2.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_intg_err.2460736220
Short name T124
Test name
Test status
Simulation time 570840630 ps
CPU time 16.26 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 212668 kb
Host smart-8299dc6d-aa54-4203-8aa9-4abb0f37f961
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460736220 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_intg_err.2
460736220
Directory /workspace/10.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_mem_rw_with_rand_reset.4009315404
Short name T41
Test name
Test status
Simulation time 1082051253 ps
CPU time 3.44 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:45 PM PST 24
Peak memory 212732 kb
Host smart-de1617f3-15e4-45db-a997-af9097e08b0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009315404 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.rv_dm_csr_mem_rw_with_rand_reset.4009315404
Directory /workspace/13.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/4.rv_dm_stress_all.2373895215
Short name T30
Test name
Test status
Simulation time 1705539855 ps
CPU time 5.79 seconds
Started Mar 03 12:34:15 PM PST 24
Finished Mar 03 12:34:21 PM PST 24
Peak memory 203868 kb
Host smart-a97a04b0-9050-4dd0-bd79-218f4c19932b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373895215 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_stress_all.2373895215
Directory /workspace/4.rv_dm_stress_all/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_not_supported.4268650952
Short name T3
Test name
Test status
Simulation time 4259179126 ps
CPU time 4.11 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:15 PM PST 24
Peak memory 203896 kb
Host smart-880a2be6-de52-4be2-8af9-2bcc372d169a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268650952 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_not_supported.4268650952
Directory /workspace/1.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/4.rv_dm_sec_cm.3549158937
Short name T34
Test name
Test status
Simulation time 67368052 ps
CPU time 0.98 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:37:28 PM PST 24
Peak memory 218580 kb
Host smart-03717549-f7f4-4ab4-9a6f-37dfcb824b76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549158937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sec_cm.3549158937
Directory /workspace/4.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_rom_read_access.956489551
Short name T22
Test name
Test status
Simulation time 28689893 ps
CPU time 0.76 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203688 kb
Host smart-c73fd6d4-bc95-4ab2-94d7-287d2f73692e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956489551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_rom_read_access.956489551
Directory /workspace/0.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_exception.4209017340
Short name T13
Test name
Test status
Simulation time 264137730 ps
CPU time 1.37 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:09 PM PST 24
Peak memory 203648 kb
Host smart-9267add0-7965-4b19-b455-74d47d5d4e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209017340 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_exception.4209017340
Directory /workspace/0.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_same_csr_outstanding.892977766
Short name T55
Test name
Test status
Simulation time 1619484427 ps
CPU time 7.56 seconds
Started Mar 03 12:38:40 PM PST 24
Finished Mar 03 12:38:49 PM PST 24
Peak memory 204380 kb
Host smart-dc7b81ea-eaea-42d5-b6d8-af35f06aff8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892977766 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_same_
csr_outstanding.892977766
Directory /workspace/15.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/default/1.rv_dm_autoincr_sba_tl_access.364229331
Short name T2
Test name
Test status
Simulation time 14709418773 ps
CPU time 33.31 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:45 PM PST 24
Peak memory 204064 kb
Host smart-c0610421-83ed-44c4-ac7e-91c68d930fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364229331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_autoincr_sba_tl_access.364229331
Directory /workspace/1.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_progbuf_busy.824185087
Short name T23
Test name
Test status
Simulation time 83135480 ps
CPU time 0.7 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:12 PM PST 24
Peak memory 203684 kb
Host smart-d0f597eb-8a4f-4a84-b91a-b7908279cd6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824185087 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_progbuf_busy.824185087
Directory /workspace/0.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_intg_err.828011713
Short name T37
Test name
Test status
Simulation time 905908026 ps
CPU time 9.06 seconds
Started Mar 03 12:38:16 PM PST 24
Finished Mar 03 12:38:26 PM PST 24
Peak memory 212484 kb
Host smart-ea13243d-16fa-4817-9717-dd37a908272e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828011713 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_intg_err.828011713
Directory /workspace/2.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_mem_rw_with_rand_reset.3695603195
Short name T59
Test name
Test status
Simulation time 4016476968 ps
CPU time 5.12 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:40 PM PST 24
Peak memory 220904 kb
Host smart-555ca409-eda1-44ae-a419-1f57ec8d4cdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695603195 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.rv_dm_csr_mem_rw_with_rand_reset.3695603195
Directory /workspace/10.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/47.rv_dm_stress_all.875707997
Short name T11
Test name
Test status
Simulation time 4919475839 ps
CPU time 5.05 seconds
Started Mar 03 12:34:44 PM PST 24
Finished Mar 03 12:34:50 PM PST 24
Peak memory 203880 kb
Host smart-28cc4da4-151a-4aae-bf47-0f4aab6aee5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875707997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_stress_all.875707997
Directory /workspace/47.rv_dm_stress_all/latest

Test location /workspace/coverage/default/17.rv_dm_alert_test.3251989666
Short name T44
Test name
Test status
Simulation time 64214715 ps
CPU time 0.62 seconds
Started Mar 03 12:34:40 PM PST 24
Finished Mar 03 12:34:41 PM PST 24
Peak memory 203704 kb
Host smart-6c68447e-a66d-4dee-93a6-adbcba31bb13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251989666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_alert_test.3251989666
Directory /workspace/17.rv_dm_alert_test/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_rw.3113124411
Short name T241
Test name
Test status
Simulation time 101110043 ps
CPU time 0.69 seconds
Started Mar 03 12:38:03 PM PST 24
Finished Mar 03 12:38:04 PM PST 24
Peak memory 203984 kb
Host smart-11e9755f-6890-4475-b3d0-03980c9416e4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113124411 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_csr_rw.3
113124411
Directory /workspace/0.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_mem_rw_with_rand_reset.97089819
Short name T331
Test name
Test status
Simulation time 1996874344 ps
CPU time 4.7 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:46 PM PST 24
Peak memory 220728 kb
Host smart-d9458929-7998-4428-9d94-77254b8ad1e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97089819 -assert nopostproc +UVM_TESTNAME=r
v_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log
/dev/null -cm_name 11.rv_dm_csr_mem_rw_with_rand_reset.97089819
Directory /workspace/11.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_intg_err.3346625818
Short name T128
Test name
Test status
Simulation time 944071280 ps
CPU time 18.18 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 213848 kb
Host smart-d3c24f1a-f2fa-4bbd-9619-1d80570c0fc8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346625818 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_intg_err.3
346625818
Directory /workspace/13.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_hw_reset.3467003917
Short name T89
Test name
Test status
Simulation time 673012875 ps
CPU time 1 seconds
Started Mar 03 12:38:12 PM PST 24
Finished Mar 03 12:38:13 PM PST 24
Peak memory 204244 kb
Host smart-dd258d0d-423c-4812-95b3-4990a7d71a08
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467003917 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_hw_reset.3467003917
Directory /workspace/0.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_halt_resume.1543423867
Short name T20
Test name
Test status
Simulation time 276116202 ps
CPU time 1.02 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203608 kb
Host smart-26247a0a-da9d-4cfc-9024-5ebb8f5375ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543423867 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_halt_resume.1543423867
Directory /workspace/0.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_same_csr_outstanding.4023831912
Short name T51
Test name
Test status
Simulation time 1625696666 ps
CPU time 7.14 seconds
Started Mar 03 12:38:06 PM PST 24
Finished Mar 03 12:38:13 PM PST 24
Peak memory 204464 kb
Host smart-1ce1f101-0c6c-4a65-89e3-d1a2dd93c87b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023831912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_same_
csr_outstanding.4023831912
Directory /workspace/0.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_same_csr_outstanding.4273159988
Short name T83
Test name
Test status
Simulation time 395937630 ps
CPU time 7 seconds
Started Mar 03 12:38:10 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 204368 kb
Host smart-46ed96f9-bfcc-47bf-886a-3697b0618e3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273159988 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_same_
csr_outstanding.4273159988
Directory /workspace/1.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_aliasing.1596891052
Short name T266
Test name
Test status
Simulation time 6139000888 ps
CPU time 30.46 seconds
Started Mar 03 12:37:41 PM PST 24
Finished Mar 03 12:38:12 PM PST 24
Peak memory 204384 kb
Host smart-9dc9d6a3-15fc-45ed-8b60-244495109526
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596891052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 0.rv_dm_csr_aliasing.1596891052
Directory /workspace/0.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_bit_bash.616663744
Short name T328
Test name
Test status
Simulation time 7014290088 ps
CPU time 27.86 seconds
Started Mar 03 12:37:59 PM PST 24
Finished Mar 03 12:38:27 PM PST 24
Peak memory 204292 kb
Host smart-4b80c927-e0ab-47fb-a5b4-92b6024bbe1c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616663744 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_bit_bash.616663744
Directory /workspace/0.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_hw_reset.4177864991
Short name T257
Test name
Test status
Simulation time 176697278 ps
CPU time 2.17 seconds
Started Mar 03 12:37:50 PM PST 24
Finished Mar 03 12:37:52 PM PST 24
Peak memory 204284 kb
Host smart-67dc5e57-08f3-4fd8-bc67-7e236040bb14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177864991 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_hw_reset.4177864991
Directory /workspace/0.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_mem_rw_with_rand_reset.1277596450
Short name T260
Test name
Test status
Simulation time 1712620091 ps
CPU time 3.43 seconds
Started Mar 03 12:37:48 PM PST 24
Finished Mar 03 12:37:56 PM PST 24
Peak memory 212660 kb
Host smart-45feece3-6a91-48af-9044-a6e9be0ba651
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277596450 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.rv_dm_csr_mem_rw_with_rand_reset.1277596450
Directory /workspace/0.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_csr_rw.65175128
Short name T102
Test name
Test status
Simulation time 1582852810 ps
CPU time 2.36 seconds
Started Mar 03 12:38:23 PM PST 24
Finished Mar 03 12:38:25 PM PST 24
Peak memory 204284 kb
Host smart-afd85383-697e-4d35-b4b3-861bbf746fed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65175128 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_csr_rw.65175128
Directory /workspace/0.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_aliasing.3655745777
Short name T300
Test name
Test status
Simulation time 9011913098 ps
CPU time 21.06 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:36 PM PST 24
Peak memory 204216 kb
Host smart-b390ed43-8b08-4118-9efe-bd8591aa7c5e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655745777 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_cs
r_aliasing.3655745777
Directory /workspace/0.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dmi_csr_rw.4063547582
Short name T314
Test name
Test status
Simulation time 367943962 ps
CPU time 1.88 seconds
Started Mar 03 12:37:44 PM PST 24
Finished Mar 03 12:37:46 PM PST 24
Peak memory 204236 kb
Host smart-405dd2ff-003e-4178-830f-321d7f9d635a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063547582 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_csr_rw.4
063547582
Directory /workspace/0.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_aliasing.3394232943
Short name T357
Test name
Test status
Simulation time 70777882 ps
CPU time 0.88 seconds
Started Mar 03 12:38:11 PM PST 24
Finished Mar 03 12:38:12 PM PST 24
Peak memory 203988 kb
Host smart-69b57e30-9da3-4b41-876f-6c8be12b0250
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394232943 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_aliasing.3394232943
Directory /workspace/0.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_bit_bash.3150650617
Short name T368
Test name
Test status
Simulation time 1417290630 ps
CPU time 3.31 seconds
Started Mar 03 12:38:12 PM PST 24
Finished Mar 03 12:38:16 PM PST 24
Peak memory 204224 kb
Host smart-9fc8ac47-2a98-4549-a239-beeccb9c5338
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150650617 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_bit_bash.3150650617
Directory /workspace/0.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_jtag_dtm_csr_hw_reset.1988569076
Short name T262
Test name
Test status
Simulation time 69886008 ps
CPU time 0.8 seconds
Started Mar 03 12:37:49 PM PST 24
Finished Mar 03 12:37:50 PM PST 24
Peak memory 204008 kb
Host smart-1caec50d-a6e2-4a47-a993-96159539f997
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988569076 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_cs
r_hw_reset.1988569076
Directory /workspace/0.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_partial_access.1312960330
Short name T259
Test name
Test status
Simulation time 41758067 ps
CPU time 0.63 seconds
Started Mar 03 12:37:55 PM PST 24
Finished Mar 03 12:37:56 PM PST 24
Peak memory 204064 kb
Host smart-4c39f122-3a84-440b-864b-2f352653ac90
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312960330 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_par
tial_access.1312960330
Directory /workspace/0.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_mem_walk.3303725289
Short name T291
Test name
Test status
Simulation time 50851472 ps
CPU time 0.61 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:19 PM PST 24
Peak memory 203988 kb
Host smart-c438ba52-fe3e-4cfa-9f90-fed870a6cc30
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303725289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_walk.3303725289
Directory /workspace/0.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tap_fsm_rand_reset.3532663964
Short name T58
Test name
Test status
Simulation time 6190993590 ps
CPU time 20.62 seconds
Started Mar 03 12:38:10 PM PST 24
Finished Mar 03 12:38:31 PM PST 24
Peak memory 220092 kb
Host smart-fb900185-d038-4110-a16d-611f2c54ffca
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532663964 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rv_dm_tap_fsm_rand_reset.3532663964
Directory /workspace/0.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_errors.191789849
Short name T343
Test name
Test status
Simulation time 826550522 ps
CPU time 5.34 seconds
Started Mar 03 12:38:06 PM PST 24
Finished Mar 03 12:38:12 PM PST 24
Peak memory 212760 kb
Host smart-b1728299-4f37-472b-92ca-c5c548700a2c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191789849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_errors.191789849
Directory /workspace/0.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rv_dm_tl_intg_err.862853460
Short name T356
Test name
Test status
Simulation time 504755138 ps
CPU time 8.26 seconds
Started Mar 03 12:37:47 PM PST 24
Finished Mar 03 12:37:56 PM PST 24
Peak memory 212504 kb
Host smart-65b2d0bb-c072-4ad1-9668-97852340a4fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862853460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rv_dm_tl_intg_err.862853460
Directory /workspace/0.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_aliasing.3640177685
Short name T103
Test name
Test status
Simulation time 6864094287 ps
CPU time 31.78 seconds
Started Mar 03 12:38:10 PM PST 24
Finished Mar 03 12:38:42 PM PST 24
Peak memory 204228 kb
Host smart-79e2663d-94f0-4c68-8bc0-8ae9ec2a99be
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640177685 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +
UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n
ame 1.rv_dm_csr_aliasing.3640177685
Directory /workspace/1.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_bit_bash.204403316
Short name T81
Test name
Test status
Simulation time 12664776774 ps
CPU time 54.55 seconds
Started Mar 03 12:37:57 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 204408 kb
Host smart-31ce17f6-26f4-4b85-8e90-a37816b5bba4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204403316 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_bit_bash.204403316
Directory /workspace/1.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_hw_reset.396071208
Short name T325
Test name
Test status
Simulation time 110418219 ps
CPU time 1.43 seconds
Started Mar 03 12:37:57 PM PST 24
Finished Mar 03 12:37:58 PM PST 24
Peak memory 204308 kb
Host smart-44968b71-a662-4fea-9522-58c78835c43c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396071208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_hw_reset.396071208
Directory /workspace/1.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_mem_rw_with_rand_reset.1158969733
Short name T360
Test name
Test status
Simulation time 4830423751 ps
CPU time 5.23 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:19 PM PST 24
Peak memory 220772 kb
Host smart-43f6db12-183d-4db3-9a3d-e3705388e262
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158969733 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.rv_dm_csr_mem_rw_with_rand_reset.1158969733
Directory /workspace/1.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_csr_rw.40873379
Short name T54
Test name
Test status
Simulation time 122882418 ps
CPU time 1.48 seconds
Started Mar 03 12:38:07 PM PST 24
Finished Mar 03 12:38:09 PM PST 24
Peak memory 204296 kb
Host smart-2961bad9-907a-4eab-8765-26de287e7fd6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40873379 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_csr_rw.40873379
Directory /workspace/1.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_aliasing.2781749961
Short name T270
Test name
Test status
Simulation time 9318606281 ps
CPU time 12.15 seconds
Started Mar 03 12:38:00 PM PST 24
Finished Mar 03 12:38:12 PM PST 24
Peak memory 204216 kb
Host smart-9c283ff6-a9fb-4bdf-9587-edb315ee4d20
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781749961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_aliasing.2781749961
Directory /workspace/1.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_bit_bash.3228936217
Short name T337
Test name
Test status
Simulation time 38282782270 ps
CPU time 127.52 seconds
Started Mar 03 12:38:02 PM PST 24
Finished Mar 03 12:40:09 PM PST 24
Peak memory 204308 kb
Host smart-bd107006-9a36-4799-baa7-5746a9f4cda1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228936217 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_bit_bash.3228936217
Directory /workspace/1.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_hw_reset.2656372151
Short name T242
Test name
Test status
Simulation time 1260430851 ps
CPU time 2.75 seconds
Started Mar 03 12:38:13 PM PST 24
Finished Mar 03 12:38:15 PM PST 24
Peak memory 204148 kb
Host smart-702f883b-0563-432c-86ff-62d71f9b8583
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656372151 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_cs
r_hw_reset.2656372151
Directory /workspace/1.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dmi_csr_rw.2164981009
Short name T238
Test name
Test status
Simulation time 168143364 ps
CPU time 0.98 seconds
Started Mar 03 12:37:55 PM PST 24
Finished Mar 03 12:37:56 PM PST 24
Peak memory 204212 kb
Host smart-0a328a63-032d-4a81-8cde-ffe29b56d086
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164981009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_csr_rw.2
164981009
Directory /workspace/1.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_aliasing.2832713592
Short name T265
Test name
Test status
Simulation time 83749973 ps
CPU time 0.87 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 203776 kb
Host smart-9740896c-fa3d-476e-a521-f1c6bf17176a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832713592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_aliasing.2832713592
Directory /workspace/1.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_bit_bash.160825187
Short name T254
Test name
Test status
Simulation time 671120277 ps
CPU time 1.23 seconds
Started Mar 03 12:38:06 PM PST 24
Finished Mar 03 12:38:07 PM PST 24
Peak memory 204152 kb
Host smart-dcf69b58-feeb-42b1-9020-47393b17ad32
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160825187 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr
_bit_bash.160825187
Directory /workspace/1.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_hw_reset.2727077425
Short name T252
Test name
Test status
Simulation time 42867188 ps
CPU time 0.72 seconds
Started Mar 03 12:38:20 PM PST 24
Finished Mar 03 12:38:21 PM PST 24
Peak memory 203996 kb
Host smart-0b0e701b-6f8f-4cc2-8751-f9949f1ec063
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727077425 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_cs
r_hw_reset.2727077425
Directory /workspace/1.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_jtag_dtm_csr_rw.4033313856
Short name T271
Test name
Test status
Simulation time 55815801 ps
CPU time 0.76 seconds
Started Mar 03 12:38:00 PM PST 24
Finished Mar 03 12:38:01 PM PST 24
Peak memory 203980 kb
Host smart-0c455890-8b0f-4a1f-b512-8ad2f2102749
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4033313856 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_csr_rw.4
033313856
Directory /workspace/1.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_partial_access.2394120642
Short name T273
Test name
Test status
Simulation time 59244839 ps
CPU time 0.62 seconds
Started Mar 03 12:37:55 PM PST 24
Finished Mar 03 12:38:01 PM PST 24
Peak memory 204060 kb
Host smart-2593ff3f-86fa-4e23-a32e-5a96a97e58cc
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394120642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_par
tial_access.2394120642
Directory /workspace/1.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_mem_walk.1136689544
Short name T333
Test name
Test status
Simulation time 50617666 ps
CPU time 0.7 seconds
Started Mar 03 12:37:59 PM PST 24
Finished Mar 03 12:38:04 PM PST 24
Peak memory 204008 kb
Host smart-8be53078-2bf3-4666-b923-aa759dd4a488
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136689544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_walk.1136689544
Directory /workspace/1.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_errors.3409379172
Short name T327
Test name
Test status
Simulation time 474912856 ps
CPU time 5.01 seconds
Started Mar 03 12:38:09 PM PST 24
Finished Mar 03 12:38:14 PM PST 24
Peak memory 204464 kb
Host smart-9d516767-e468-42ae-aae6-e29ee7121133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409379172 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_errors.3409379172
Directory /workspace/1.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.rv_dm_tl_intg_err.266461794
Short name T347
Test name
Test status
Simulation time 872604034 ps
CPU time 9.48 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:31 PM PST 24
Peak memory 212552 kb
Host smart-59cdd34b-f694-4c11-8487-e327f717e385
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266461794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rv_dm_tl_intg_err.266461794
Directory /workspace/1.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_csr_rw.3463218246
Short name T366
Test name
Test status
Simulation time 109584598 ps
CPU time 2.29 seconds
Started Mar 03 12:38:30 PM PST 24
Finished Mar 03 12:38:34 PM PST 24
Peak memory 212492 kb
Host smart-14c8200b-b734-4641-a978-eb34b4f82793
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463218246 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_csr_rw.3463218246
Directory /workspace/10.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dmi_csr_rw.535072809
Short name T276
Test name
Test status
Simulation time 725769240 ps
CPU time 2.14 seconds
Started Mar 03 12:38:31 PM PST 24
Finished Mar 03 12:38:34 PM PST 24
Peak memory 204180 kb
Host smart-69897db0-4d7c-430a-9db5-e8932c4b972c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535072809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dmi_csr_rw.535072809
Directory /workspace/10.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_jtag_dtm_csr_rw.388448586
Short name T255
Test name
Test status
Simulation time 77758191 ps
CPU time 0.74 seconds
Started Mar 03 12:38:31 PM PST 24
Finished Mar 03 12:38:32 PM PST 24
Peak memory 203924 kb
Host smart-17f6ba4c-01b2-4df4-8672-8af58fce8a4d
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388448586 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_jtag_dtm_csr_rw.388448586
Directory /workspace/10.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_same_csr_outstanding.2627855045
Short name T104
Test name
Test status
Simulation time 1870900582 ps
CPU time 7.86 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:43 PM PST 24
Peak memory 204264 kb
Host smart-f40d1181-8b4c-477a-8f56-69fd5f27f06b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627855045 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_same
_csr_outstanding.2627855045
Directory /workspace/10.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rv_dm_tl_errors.3600166541
Short name T305
Test name
Test status
Simulation time 242195906 ps
CPU time 2.84 seconds
Started Mar 03 12:38:29 PM PST 24
Finished Mar 03 12:38:34 PM PST 24
Peak memory 212616 kb
Host smart-9f10515a-dd8c-4201-b967-688dbdead998
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600166541 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rv_dm_tl_errors.3600166541
Directory /workspace/10.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_csr_rw.2516757387
Short name T56
Test name
Test status
Simulation time 40246753 ps
CPU time 2.11 seconds
Started Mar 03 12:38:33 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 212512 kb
Host smart-6d91b4c6-6a36-4138-8c70-f93e2f008c50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516757387 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_csr_rw.2516757387
Directory /workspace/11.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dmi_csr_rw.3886146928
Short name T248
Test name
Test status
Simulation time 389518008 ps
CPU time 2.12 seconds
Started Mar 03 12:38:33 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 204276 kb
Host smart-f15603ff-dbe9-4d6a-b9fb-a966667bf641
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886146928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dmi_csr_rw.
3886146928
Directory /workspace/11.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_jtag_dtm_csr_rw.2606236990
Short name T282
Test name
Test status
Simulation time 28104520 ps
CPU time 0.67 seconds
Started Mar 03 12:38:32 PM PST 24
Finished Mar 03 12:38:33 PM PST 24
Peak memory 204008 kb
Host smart-3d682daf-6533-4084-9350-a5561f25261a
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606236990 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_jtag_dtm_csr_rw.
2606236990
Directory /workspace/11.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_same_csr_outstanding.590034866
Short name T106
Test name
Test status
Simulation time 2719426798 ps
CPU time 6.99 seconds
Started Mar 03 12:38:32 PM PST 24
Finished Mar 03 12:38:40 PM PST 24
Peak memory 204372 kb
Host smart-e12f2afa-4207-4285-8dca-387fd28e72c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590034866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_same_
csr_outstanding.590034866
Directory /workspace/11.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_errors.245453024
Short name T119
Test name
Test status
Simulation time 263616735 ps
CPU time 4.22 seconds
Started Mar 03 12:38:30 PM PST 24
Finished Mar 03 12:38:36 PM PST 24
Peak memory 212640 kb
Host smart-9394d76b-4aeb-4f01-97b3-0ed4417ba6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245453024 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_errors.245453024
Directory /workspace/11.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.rv_dm_tl_intg_err.700957908
Short name T36
Test name
Test status
Simulation time 3289468510 ps
CPU time 19.5 seconds
Started Mar 03 12:38:32 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 216876 kb
Host smart-3bea92ae-923e-417f-8984-c8031dad706a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700957908 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rv_dm_tl_intg_err.700957908
Directory /workspace/11.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_mem_rw_with_rand_reset.2871531079
Short name T43
Test name
Test status
Simulation time 2314480175 ps
CPU time 5.45 seconds
Started Mar 03 12:38:43 PM PST 24
Finished Mar 03 12:38:48 PM PST 24
Peak memory 212692 kb
Host smart-59584cd6-d3a3-447d-95a9-381dae34513a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871531079 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.rv_dm_csr_mem_rw_with_rand_reset.2871531079
Directory /workspace/12.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_csr_rw.1970090697
Short name T339
Test name
Test status
Simulation time 378295619 ps
CPU time 2.33 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204296 kb
Host smart-8f0d4946-b4bc-488c-a34f-dd4584d76f74
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970090697 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_csr_rw.1970090697
Directory /workspace/12.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dmi_csr_rw.635396727
Short name T243
Test name
Test status
Simulation time 763620528 ps
CPU time 1.01 seconds
Started Mar 03 12:38:49 PM PST 24
Finished Mar 03 12:38:51 PM PST 24
Peak memory 204216 kb
Host smart-43aae73a-9e3f-41ca-94fa-17ee864300b6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635396727 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dmi_csr_rw.635396727
Directory /workspace/12.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_jtag_dtm_csr_rw.196558498
Short name T307
Test name
Test status
Simulation time 89094017 ps
CPU time 0.85 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:43 PM PST 24
Peak memory 204012 kb
Host smart-4c0e897e-9acb-4280-bd5e-779baa8d5418
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196558498 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_jtag_dtm_csr_rw.196558498
Directory /workspace/12.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_same_csr_outstanding.1672772564
Short name T361
Test name
Test status
Simulation time 597459353 ps
CPU time 6.27 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:47 PM PST 24
Peak memory 204380 kb
Host smart-457d3093-4e79-456c-a67d-c0cfd325455c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672772564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_same
_csr_outstanding.1672772564
Directory /workspace/12.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_errors.2916536626
Short name T310
Test name
Test status
Simulation time 51544054 ps
CPU time 1.79 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204784 kb
Host smart-8f9837a6-5367-40e1-b647-e721f0f5e00d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916536626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_errors.2916536626
Directory /workspace/12.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rv_dm_tl_intg_err.3179702369
Short name T370
Test name
Test status
Simulation time 1699596781 ps
CPU time 18.45 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 216012 kb
Host smart-4b180c16-42d3-44da-8c15-566089a2dc79
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179702369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rv_dm_tl_intg_err.3
179702369
Directory /workspace/12.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_csr_rw.3934943972
Short name T93
Test name
Test status
Simulation time 325936220 ps
CPU time 2.28 seconds
Started Mar 03 12:38:49 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 212416 kb
Host smart-e5ea5940-7cb2-4f1b-9df0-943c5f82ff56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934943972 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_csr_rw.3934943972
Directory /workspace/13.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dmi_csr_rw.292890928
Short name T237
Test name
Test status
Simulation time 570625764 ps
CPU time 2.69 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204200 kb
Host smart-7d33c5c1-d7ec-4436-85c5-90a61109f001
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292890928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dmi_csr_rw.292890928
Directory /workspace/13.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_jtag_dtm_csr_rw.3241872311
Short name T296
Test name
Test status
Simulation time 50415737 ps
CPU time 0.77 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:42 PM PST 24
Peak memory 203996 kb
Host smart-5be314a1-ec9d-4dff-8703-26befaf8af9e
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241872311 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_jtag_dtm_csr_rw.
3241872311
Directory /workspace/13.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_same_csr_outstanding.2667782941
Short name T372
Test name
Test status
Simulation time 3624023166 ps
CPU time 4.33 seconds
Started Mar 03 12:38:39 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204440 kb
Host smart-a2e16a3f-5009-4ab0-91b7-a2bfac32d787
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667782941 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_same
_csr_outstanding.2667782941
Directory /workspace/13.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rv_dm_tl_errors.1754036930
Short name T39
Test name
Test status
Simulation time 572221042 ps
CPU time 3.02 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204424 kb
Host smart-c00aa7dc-09b7-42c9-b04a-4d88c8ad3804
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754036930 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rv_dm_tl_errors.1754036930
Directory /workspace/13.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_mem_rw_with_rand_reset.3576830583
Short name T362
Test name
Test status
Simulation time 3637715868 ps
CPU time 6.6 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:48 PM PST 24
Peak memory 215460 kb
Host smart-9bcd1a22-2fef-414f-9be4-5269a6beb7dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3576830583 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.rv_dm_csr_mem_rw_with_rand_reset.3576830583
Directory /workspace/14.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_csr_rw.1603350404
Short name T351
Test name
Test status
Simulation time 114871489 ps
CPU time 2.39 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:45 PM PST 24
Peak memory 204224 kb
Host smart-1961fb72-891c-47ea-90bf-fddbda3997bd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603350404 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_csr_rw.1603350404
Directory /workspace/14.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dmi_csr_rw.3779912521
Short name T274
Test name
Test status
Simulation time 929735267 ps
CPU time 1.73 seconds
Started Mar 03 12:38:43 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204164 kb
Host smart-7b7509fe-6e1d-4e61-b5ec-0b3fe567ee64
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779912521 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dmi_csr_rw.
3779912521
Directory /workspace/14.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_jtag_dtm_csr_rw.675839963
Short name T279
Test name
Test status
Simulation time 52473842 ps
CPU time 0.65 seconds
Started Mar 03 12:38:43 PM PST 24
Finished Mar 03 12:38:43 PM PST 24
Peak memory 204008 kb
Host smart-1e65d456-9ca3-4514-b81b-791151bc9522
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675839963 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_jtag_dtm_csr_rw.675839963
Directory /workspace/14.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_same_csr_outstanding.2554026393
Short name T91
Test name
Test status
Simulation time 86020880 ps
CPU time 3.52 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:45 PM PST 24
Peak memory 204364 kb
Host smart-9c2dbf4d-f5ef-4fc4-b4f1-bfb11649bb25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554026393 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_same
_csr_outstanding.2554026393
Directory /workspace/14.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tap_fsm_rand_reset.2770881312
Short name T272
Test name
Test status
Simulation time 6268909304 ps
CPU time 20.49 seconds
Started Mar 03 12:38:40 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 212628 kb
Host smart-9ba594cc-0f7a-465c-8677-1ee7de11bac4
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770881312 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rv_dm_tap_fsm_rand_reset.2770881312
Directory /workspace/14.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_errors.137725023
Short name T165
Test name
Test status
Simulation time 276923108 ps
CPU time 5.15 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:48 PM PST 24
Peak memory 212616 kb
Host smart-31b1910c-0ab0-4f6a-abe4-92135a2ef66e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137725023 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_errors.137725023
Directory /workspace/14.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rv_dm_tl_intg_err.2132160733
Short name T342
Test name
Test status
Simulation time 1576964756 ps
CPU time 9.47 seconds
Started Mar 03 12:38:40 PM PST 24
Finished Mar 03 12:38:49 PM PST 24
Peak memory 212592 kb
Host smart-20de18a6-c05a-4277-95dc-fb1cc28ad17a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132160733 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rv_dm_tl_intg_err.2
132160733
Directory /workspace/14.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_mem_rw_with_rand_reset.1865008139
Short name T344
Test name
Test status
Simulation time 1521290521 ps
CPU time 2.64 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:45 PM PST 24
Peak memory 212552 kb
Host smart-f791918e-78a6-42c7-909f-fb2e2b242de6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865008139 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.rv_dm_csr_mem_rw_with_rand_reset.1865008139
Directory /workspace/15.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_csr_rw.278474965
Short name T98
Test name
Test status
Simulation time 321157304 ps
CPU time 2.33 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204328 kb
Host smart-dbb0cda3-d5ee-4514-b760-412e6f4f9209
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278474965 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_csr_rw.278474965
Directory /workspace/15.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dmi_csr_rw.2651600052
Short name T268
Test name
Test status
Simulation time 543256333 ps
CPU time 2.95 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204228 kb
Host smart-dae390c0-db6c-4a38-a75e-e9477f6e6c18
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651600052 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dmi_csr_rw.
2651600052
Directory /workspace/15.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_jtag_dtm_csr_rw.2315066642
Short name T302
Test name
Test status
Simulation time 32896362 ps
CPU time 0.7 seconds
Started Mar 03 12:38:44 PM PST 24
Finished Mar 03 12:38:45 PM PST 24
Peak memory 203968 kb
Host smart-8351826a-0477-4ce5-b3a4-7217a90c39cb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315066642 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_jtag_dtm_csr_rw.
2315066642
Directory /workspace/15.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tap_fsm_rand_reset.1856545785
Short name T295
Test name
Test status
Simulation time 11930690626 ps
CPU time 40.14 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:39:21 PM PST 24
Peak memory 220852 kb
Host smart-1cec6797-b872-4abf-aa7b-053f2878131c
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856545785 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rv_dm_tap_fsm_rand_reset.1856545785
Directory /workspace/15.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_errors.2086689650
Short name T304
Test name
Test status
Simulation time 1032346797 ps
CPU time 6.47 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:48 PM PST 24
Peak memory 204424 kb
Host smart-7a99e67a-600c-4e2a-8614-b146c4223baf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086689650 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_errors.2086689650
Directory /workspace/15.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rv_dm_tl_intg_err.1163493897
Short name T122
Test name
Test status
Simulation time 1572317286 ps
CPU time 18.59 seconds
Started Mar 03 12:38:40 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 215624 kb
Host smart-39523a89-3eed-45a6-9786-f13feb4037b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163493897 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rv_dm_tl_intg_err.1
163493897
Directory /workspace/15.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_mem_rw_with_rand_reset.635480625
Short name T358
Test name
Test status
Simulation time 4180095038 ps
CPU time 7.46 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:49 PM PST 24
Peak memory 220788 kb
Host smart-9e895063-beb5-4031-b5be-fb61eac92c92
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635480625 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 16.rv_dm_csr_mem_rw_with_rand_reset.635480625
Directory /workspace/16.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_csr_rw.3055691520
Short name T287
Test name
Test status
Simulation time 294102053 ps
CPU time 1.48 seconds
Started Mar 03 12:38:43 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 212448 kb
Host smart-9514ba3c-d023-43c8-a4f9-f9acf64d01fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055691520 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_csr_rw.3055691520
Directory /workspace/16.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dmi_csr_rw.1947224872
Short name T294
Test name
Test status
Simulation time 846477513 ps
CPU time 2.36 seconds
Started Mar 03 12:38:44 PM PST 24
Finished Mar 03 12:38:47 PM PST 24
Peak memory 204116 kb
Host smart-89a1179d-535c-49c5-bb90-be6ef295fd4b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1947224872 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dmi_csr_rw.
1947224872
Directory /workspace/16.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_jtag_dtm_csr_rw.3713681907
Short name T369
Test name
Test status
Simulation time 31381186 ps
CPU time 0.76 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:43 PM PST 24
Peak memory 204024 kb
Host smart-380c5dc3-072c-4ee8-9cf8-8c9fbc8046eb
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713681907 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_jtag_dtm_csr_rw.
3713681907
Directory /workspace/16.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_same_csr_outstanding.4003611456
Short name T332
Test name
Test status
Simulation time 472745203 ps
CPU time 4.3 seconds
Started Mar 03 12:38:42 PM PST 24
Finished Mar 03 12:38:47 PM PST 24
Peak memory 204464 kb
Host smart-e521803e-3ffa-47dd-bd05-ec8c609aaa3c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003611456 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_same
_csr_outstanding.4003611456
Directory /workspace/16.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tap_fsm_rand_reset.3419378249
Short name T350
Test name
Test status
Simulation time 4861899650 ps
CPU time 17.5 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:59 PM PST 24
Peak memory 212700 kb
Host smart-0322daaf-de90-4e08-abd7-272bc1ed0497
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419378249 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rv_dm_tap_fsm_rand_reset.3419378249
Directory /workspace/16.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_errors.2931638461
Short name T346
Test name
Test status
Simulation time 595552655 ps
CPU time 4.7 seconds
Started Mar 03 12:38:41 PM PST 24
Finished Mar 03 12:38:46 PM PST 24
Peak memory 204404 kb
Host smart-092e9f9b-f5ec-4a09-b36b-8f8963365b73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931638461 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_errors.2931638461
Directory /workspace/16.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.rv_dm_tl_intg_err.382453877
Short name T130
Test name
Test status
Simulation time 1706756620 ps
CPU time 9.01 seconds
Started Mar 03 12:38:40 PM PST 24
Finished Mar 03 12:38:49 PM PST 24
Peak memory 212496 kb
Host smart-b70edc2f-c58b-4887-b2cd-a771143aaa00
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382453877 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rv_dm_tl_intg_err.382453877
Directory /workspace/16.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_mem_rw_with_rand_reset.4292178189
Short name T284
Test name
Test status
Simulation time 756171182 ps
CPU time 3.81 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:57 PM PST 24
Peak memory 215536 kb
Host smart-5a1ea0d0-9130-49ef-9a32-06931fb7a3d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292178189 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.rv_dm_csr_mem_rw_with_rand_reset.4292178189
Directory /workspace/17.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_csr_rw.3155292911
Short name T42
Test name
Test status
Simulation time 62575057 ps
CPU time 1.53 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 212520 kb
Host smart-7fa1c79e-ec8a-4fb6-89cd-4f1eeaac59e4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155292911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_csr_rw.3155292911
Directory /workspace/17.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dmi_csr_rw.3533113035
Short name T290
Test name
Test status
Simulation time 341946102 ps
CPU time 2.08 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 204140 kb
Host smart-7df8bd94-8d38-40f1-bd8e-c17fc02d66f5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533113035 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dmi_csr_rw.
3533113035
Directory /workspace/17.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_jtag_dtm_csr_rw.2121324822
Short name T247
Test name
Test status
Simulation time 43371886 ps
CPU time 0.71 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 203968 kb
Host smart-380f35b8-7853-412e-a8fa-377e61a0ba72
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121324822 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_jtag_dtm_csr_rw.
2121324822
Directory /workspace/17.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_same_csr_outstanding.3738691483
Short name T96
Test name
Test status
Simulation time 1688508289 ps
CPU time 6.42 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 204388 kb
Host smart-5cd01be6-8c91-4585-bde8-40523c5ec776
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738691483 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_same
_csr_outstanding.3738691483
Directory /workspace/17.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_errors.1374853575
Short name T40
Test name
Test status
Simulation time 898628831 ps
CPU time 2.46 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 212564 kb
Host smart-f1bdf372-879f-4adc-8f0e-73e5e417ef33
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374853575 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_errors.1374853575
Directory /workspace/17.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rv_dm_tl_intg_err.1809836391
Short name T125
Test name
Test status
Simulation time 1922821999 ps
CPU time 15.69 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:39:06 PM PST 24
Peak memory 212680 kb
Host smart-69ff661d-4dce-4c00-b634-b5bffc29b915
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809836391 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rv_dm_tl_intg_err.1
809836391
Directory /workspace/17.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_mem_rw_with_rand_reset.3108977301
Short name T288
Test name
Test status
Simulation time 61975263 ps
CPU time 3.72 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 216976 kb
Host smart-444c49d3-fbd2-4082-96a8-a0475b1a7747
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108977301 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.rv_dm_csr_mem_rw_with_rand_reset.3108977301
Directory /workspace/18.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_csr_rw.2456333242
Short name T359
Test name
Test status
Simulation time 314748272 ps
CPU time 2.26 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 212436 kb
Host smart-30a7807c-d7dc-40ca-b424-42312a6d049e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456333242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_csr_rw.2456333242
Directory /workspace/18.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dmi_csr_rw.4195151566
Short name T264
Test name
Test status
Simulation time 211336027 ps
CPU time 0.91 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 204164 kb
Host smart-54023256-b375-469f-801f-3a8cde34e8fa
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195151566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dmi_csr_rw.
4195151566
Directory /workspace/18.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_jtag_dtm_csr_rw.2669669759
Short name T278
Test name
Test status
Simulation time 104122472 ps
CPU time 0.71 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 204020 kb
Host smart-57e23914-2711-4ef9-9fd3-05994a03d242
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669669759 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_jtag_dtm_csr_rw.
2669669759
Directory /workspace/18.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_same_csr_outstanding.365088439
Short name T105
Test name
Test status
Simulation time 1696636451 ps
CPU time 7.64 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:39:00 PM PST 24
Peak memory 204224 kb
Host smart-a05f84b3-fdec-4692-8942-2740372e5bdd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365088439 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_same_
csr_outstanding.365088439
Directory /workspace/18.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_errors.326063909
Short name T293
Test name
Test status
Simulation time 126862168 ps
CPU time 3.89 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 204352 kb
Host smart-1fe556b9-9358-4bb4-bd0c-c17452f21e5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326063909 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_errors.326063909
Directory /workspace/18.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rv_dm_tl_intg_err.4109873408
Short name T349
Test name
Test status
Simulation time 2080908844 ps
CPU time 10.29 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 212680 kb
Host smart-03a63185-69c1-4e94-a113-a8eb38251ed1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109873408 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rv_dm_tl_intg_err.4
109873408
Directory /workspace/18.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_mem_rw_with_rand_reset.392793968
Short name T355
Test name
Test status
Simulation time 422200737 ps
CPU time 4.96 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:57 PM PST 24
Peak memory 220784 kb
Host smart-6e759a71-57c1-4a52-8a0a-e31df6d98f9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392793968 -assert nopostproc +UVM_TESTNAME=
rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 19.rv_dm_csr_mem_rw_with_rand_reset.392793968
Directory /workspace/19.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_csr_rw.1935963597
Short name T371
Test name
Test status
Simulation time 181831619 ps
CPU time 2.56 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:38:56 PM PST 24
Peak memory 204400 kb
Host smart-caba1e20-1fd4-4c9b-b33b-e254fa9a7c41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935963597 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_csr_rw.1935963597
Directory /workspace/19.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dmi_csr_rw.26754798
Short name T321
Test name
Test status
Simulation time 1474020488 ps
CPU time 2.19 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 204168 kb
Host smart-8f91eabb-b106-4c6c-a064-6a0cae9c1366
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26754798 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dmi_csr_rw.26754798
Directory /workspace/19.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_jtag_dtm_csr_rw.1065105352
Short name T311
Test name
Test status
Simulation time 191026563 ps
CPU time 0.66 seconds
Started Mar 03 12:38:54 PM PST 24
Finished Mar 03 12:38:55 PM PST 24
Peak memory 203968 kb
Host smart-8c8d6be7-3217-45f3-8a13-aa685474d1cd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065105352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_jtag_dtm_csr_rw.
1065105352
Directory /workspace/19.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_same_csr_outstanding.1451468957
Short name T82
Test name
Test status
Simulation time 518176355 ps
CPU time 3.56 seconds
Started Mar 03 12:38:48 PM PST 24
Finished Mar 03 12:38:54 PM PST 24
Peak memory 204332 kb
Host smart-1415e382-2d23-4702-b478-6bd02282b288
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451468957 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_same
_csr_outstanding.1451468957
Directory /workspace/19.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tap_fsm_rand_reset.2061375568
Short name T365
Test name
Test status
Simulation time 23389931666 ps
CPU time 20.98 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:39:14 PM PST 24
Peak memory 220776 kb
Host smart-05e2b613-72c2-4aa5-b837-5338511d7c57
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061375568 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rv_dm_tap_fsm_rand_reset.2061375568
Directory /workspace/19.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rv_dm_tl_intg_err.3229783801
Short name T121
Test name
Test status
Simulation time 526791909 ps
CPU time 15.87 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:39:06 PM PST 24
Peak memory 212412 kb
Host smart-479606d7-509a-4fed-beca-57d58624ebb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3229783801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rv_dm_tl_intg_err.3
229783801
Directory /workspace/19.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_bit_bash.3442163718
Short name T80
Test name
Test status
Simulation time 4949676010 ps
CPU time 33.77 seconds
Started Mar 03 12:38:12 PM PST 24
Finished Mar 03 12:38:46 PM PST 24
Peak memory 204404 kb
Host smart-98e25bcf-d1f7-4b13-bb06-64ef564900aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442163718 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_bit_bash.3442163718
Directory /workspace/2.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_hw_reset.1619919864
Short name T286
Test name
Test status
Simulation time 60576127 ps
CPU time 2.16 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 204308 kb
Host smart-222b866e-7d49-4bb0-ad89-69ae96bb15b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619919864 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_hw_reset.1619919864
Directory /workspace/2.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_mem_rw_with_rand_reset.1788247796
Short name T289
Test name
Test status
Simulation time 1253618712 ps
CPU time 2.76 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 215768 kb
Host smart-7519df51-d8f3-4711-af7c-6ddd63d46834
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788247796 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.rv_dm_csr_mem_rw_with_rand_reset.1788247796
Directory /workspace/2.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_csr_rw.3314612626
Short name T97
Test name
Test status
Simulation time 113342686 ps
CPU time 2.22 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 204228 kb
Host smart-f4ec91bd-cd99-4447-be68-b5ac0d65f7e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314612626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_csr_rw.3314612626
Directory /workspace/2.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_aliasing.2981307371
Short name T309
Test name
Test status
Simulation time 14573301851 ps
CPU time 42.43 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 204236 kb
Host smart-4880c826-15cd-42cf-be59-71f1c3d7d76b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981307371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_aliasing.2981307371
Directory /workspace/2.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_bit_bash.1943608961
Short name T269
Test name
Test status
Simulation time 9003286062 ps
CPU time 21.37 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 204208 kb
Host smart-f300377c-aa9c-43d3-a6f1-53dd23a2d0a0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943608961 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_cs
r_bit_bash.1943608961
Directory /workspace/2.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_hw_reset.810581618
Short name T88
Test name
Test status
Simulation time 1200484167 ps
CPU time 1.9 seconds
Started Mar 03 12:38:13 PM PST 24
Finished Mar 03 12:38:15 PM PST 24
Peak memory 204292 kb
Host smart-502860d4-7ad5-4ae1-879e-900811608b5b
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810581618 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr
_hw_reset.810581618
Directory /workspace/2.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dmi_csr_rw.2447506525
Short name T301
Test name
Test status
Simulation time 593617817 ps
CPU time 1.55 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 204240 kb
Host smart-f73db0b5-e0ab-4eab-8fd5-74ca69f5147f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447506525 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dmi_csr_rw.2
447506525
Directory /workspace/2.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_aliasing.86232720
Short name T251
Test name
Test status
Simulation time 276899217 ps
CPU time 0.82 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 204020 kb
Host smart-e4510eec-8bba-4756-9e32-780e5f5fead0
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86232720 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_
aliasing.86232720
Directory /workspace/2.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_bit_bash.3626178499
Short name T72
Test name
Test status
Simulation time 2088759870 ps
CPU time 2.26 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 204216 kb
Host smart-8c3276e9-26d7-48f5-8829-d90b2ba2ecc6
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626178499 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_bit_bash.3626178499
Directory /workspace/2.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_hw_reset.2919891634
Short name T324
Test name
Test status
Simulation time 82499397 ps
CPU time 0.7 seconds
Started Mar 03 12:38:16 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 203968 kb
Host smart-0cf02940-dc26-4b80-8c2b-7ca3c90e79a4
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919891634 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_cs
r_hw_reset.2919891634
Directory /workspace/2.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_jtag_dtm_csr_rw.4048199627
Short name T246
Test name
Test status
Simulation time 171588918 ps
CPU time 0.81 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 204352 kb
Host smart-adab320c-2b41-496f-8056-1661938058a5
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048199627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_jtag_dtm_csr_rw.4
048199627
Directory /workspace/2.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_partial_access.2230178043
Short name T258
Test name
Test status
Simulation time 32974881 ps
CPU time 0.77 seconds
Started Mar 03 12:38:13 PM PST 24
Finished Mar 03 12:38:14 PM PST 24
Peak memory 204072 kb
Host smart-c9bc95d0-5370-4e21-aecc-1aef582b5e3c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230178043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_par
tial_access.2230178043
Directory /workspace/2.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_mem_walk.3517697883
Short name T236
Test name
Test status
Simulation time 48402178 ps
CPU time 0.67 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:16 PM PST 24
Peak memory 204008 kb
Host smart-b2ec7dc1-8a7c-4e21-9bde-1e00cafb0039
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517697883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_mem_walk.3517697883
Directory /workspace/2.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_same_csr_outstanding.2521918293
Short name T107
Test name
Test status
Simulation time 812276080 ps
CPU time 7.25 seconds
Started Mar 03 12:38:16 PM PST 24
Finished Mar 03 12:38:24 PM PST 24
Peak memory 204308 kb
Host smart-f623a8d7-39d2-48c6-971c-83cac7f66424
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521918293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_same_
csr_outstanding.2521918293
Directory /workspace/2.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rv_dm_tl_errors.1225727846
Short name T299
Test name
Test status
Simulation time 1096607605 ps
CPU time 6.39 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 212732 kb
Host smart-a13c123c-4829-4e37-8598-e4c96a8b06c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225727846 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rv_dm_tl_errors.1225727846
Directory /workspace/2.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.rv_dm_tap_fsm_rand_reset.1965188987
Short name T345
Test name
Test status
Simulation time 6141361381 ps
CPU time 19.2 seconds
Started Mar 03 12:38:50 PM PST 24
Finished Mar 03 12:39:10 PM PST 24
Peak memory 212868 kb
Host smart-ca98b32b-e368-44e0-afca-d73e62b95a31
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965188987 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 20.rv_dm_tap_fsm_rand_reset.1965188987
Directory /workspace/20.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/21.rv_dm_tap_fsm_rand_reset.871879626
Short name T334
Test name
Test status
Simulation time 13444081779 ps
CPU time 23.28 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:39:17 PM PST 24
Peak memory 220040 kb
Host smart-c65e7b42-a166-4899-aa98-027c2100976d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871879626 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 21.rv_dm_tap_fsm_rand_reset.871879626
Directory /workspace/21.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/26.rv_dm_tap_fsm_rand_reset.2369893119
Short name T131
Test name
Test status
Simulation time 6062902683 ps
CPU time 19.6 seconds
Started Mar 03 12:38:49 PM PST 24
Finished Mar 03 12:39:10 PM PST 24
Peak memory 212584 kb
Host smart-949828ce-17ba-41e1-9e9a-384072d28ce0
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369893119 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 26.rv_dm_tap_fsm_rand_reset.2369893119
Directory /workspace/26.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_aliasing.843838477
Short name T101
Test name
Test status
Simulation time 1290739526 ps
CPU time 69.01 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:39:24 PM PST 24
Peak memory 204268 kb
Host smart-66a646a1-7891-4181-af4b-6dd5249e6ca2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843838477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 3.rv_dm_csr_aliasing.843838477
Directory /workspace/3.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_bit_bash.1696169314
Short name T303
Test name
Test status
Simulation time 1177476599 ps
CPU time 26.35 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:42 PM PST 24
Peak memory 204232 kb
Host smart-1b5446a4-b8b9-4306-86be-3c2a54906838
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696169314 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_bit_bash.1696169314
Directory /workspace/3.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_hw_reset.1966839598
Short name T99
Test name
Test status
Simulation time 1519113116 ps
CPU time 2.4 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:19 PM PST 24
Peak memory 212124 kb
Host smart-e942d90d-7bc1-4b9a-85b0-4456b24a66d9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966839598 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_hw_reset.1966839598
Directory /workspace/3.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_mem_rw_with_rand_reset.3847376122
Short name T318
Test name
Test status
Simulation time 1801074009 ps
CPU time 3.89 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:19 PM PST 24
Peak memory 214912 kb
Host smart-68e58f2e-accf-4acf-899d-7d029389d3d0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847376122 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.rv_dm_csr_mem_rw_with_rand_reset.3847376122
Directory /workspace/3.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_csr_rw.2103256702
Short name T298
Test name
Test status
Simulation time 185344814 ps
CPU time 2.15 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 204308 kb
Host smart-260b697c-a0c4-4eca-82ae-8a89f19293e1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103256702 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_csr_rw.2103256702
Directory /workspace/3.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_aliasing.3508385243
Short name T253
Test name
Test status
Simulation time 29960783367 ps
CPU time 51.61 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:39:09 PM PST 24
Peak memory 204220 kb
Host smart-5019766b-d2ff-4b67-98b8-2aaf39c0ad57
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508385243 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_cs
r_aliasing.3508385243
Directory /workspace/3.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_hw_reset.561849689
Short name T87
Test name
Test status
Simulation time 2258779696 ps
CPU time 3.37 seconds
Started Mar 03 12:38:13 PM PST 24
Finished Mar 03 12:38:16 PM PST 24
Peak memory 204360 kb
Host smart-3fd1320f-a8fd-4333-9134-c1e4b5a2ec15
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561849689 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr
_hw_reset.561849689
Directory /workspace/3.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dmi_csr_rw.120522136
Short name T340
Test name
Test status
Simulation time 502040573 ps
CPU time 1.13 seconds
Started Mar 03 12:38:21 PM PST 24
Finished Mar 03 12:38:22 PM PST 24
Peak memory 204184 kb
Host smart-f281a1f5-020f-41dd-93d2-3951e49c8c82
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120522136 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dmi_csr_rw.120522136
Directory /workspace/3.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_aliasing.158409488
Short name T323
Test name
Test status
Simulation time 89763450 ps
CPU time 0.71 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:22 PM PST 24
Peak memory 204012 kb
Host smart-602adbd9-c553-415d-b2f3-dd4ab9467f70
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158409488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_cs
r_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr
_aliasing.158409488
Directory /workspace/3.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_bit_bash.1588668488
Short name T261
Test name
Test status
Simulation time 1217758004 ps
CPU time 4.29 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:22 PM PST 24
Peak memory 204180 kb
Host smart-a88bf07f-d57b-42b2-9d76-7cabe563733c
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588668488 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_bit_bash.1588668488
Directory /workspace/3.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_hw_reset.3334806840
Short name T73
Test name
Test status
Simulation time 37430082 ps
CPU time 0.74 seconds
Started Mar 03 12:38:16 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 204012 kb
Host smart-9f973adb-3af6-49e3-aabc-e68996f88ebf
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334806840 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_cs
r_hw_reset.3334806840
Directory /workspace/3.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_jtag_dtm_csr_rw.667216638
Short name T256
Test name
Test status
Simulation time 82216282 ps
CPU time 0.69 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:19 PM PST 24
Peak memory 204032 kb
Host smart-235d14a4-2fbc-4abd-ae09-3296da3eaab1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667216638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_jtag_dtm_csr_rw.667216638
Directory /workspace/3.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_partial_access.4003869544
Short name T330
Test name
Test status
Simulation time 20952786 ps
CPU time 0.66 seconds
Started Mar 03 12:38:19 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 204140 kb
Host smart-639776f0-79c6-4eb0-87d3-e3ee341dec0f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003869544 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_par
tial_access.4003869544
Directory /workspace/3.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_mem_walk.332061156
Short name T250
Test name
Test status
Simulation time 60749562 ps
CPU time 0.66 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:18 PM PST 24
Peak memory 204000 kb
Host smart-3004b054-69c8-4cb7-b381-72dfbbc390ee
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332061156 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_mem_walk.332061156
Directory /workspace/3.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_same_csr_outstanding.483685997
Short name T95
Test name
Test status
Simulation time 314072896 ps
CPU time 3.52 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:21 PM PST 24
Peak memory 204360 kb
Host smart-33c85721-aa8f-4fa2-b3dd-342ea812c7f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483685997 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_same_c
sr_outstanding.483685997
Directory /workspace/3.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tap_fsm_rand_reset.150978997
Short name T315
Test name
Test status
Simulation time 34902759382 ps
CPU time 22.87 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:40 PM PST 24
Peak memory 220776 kb
Host smart-1e7d49b6-9872-480b-8d4f-8b6a5bd75d75
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150978997 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rv_dm_tap_fsm_rand_reset.150978997
Directory /workspace/3.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rv_dm_tl_errors.4075866270
Short name T280
Test name
Test status
Simulation time 1261730291 ps
CPU time 2.03 seconds
Started Mar 03 12:38:14 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 204436 kb
Host smart-2860fa89-67bc-4ad5-9d89-8492f8f9fbd5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075866270 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rv_dm_tl_errors.4075866270
Directory /workspace/3.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.rv_dm_tap_fsm_rand_reset.3986178059
Short name T267
Test name
Test status
Simulation time 35608558792 ps
CPU time 24.51 seconds
Started Mar 03 12:38:49 PM PST 24
Finished Mar 03 12:39:15 PM PST 24
Peak memory 220300 kb
Host smart-30b9eaa0-ec07-40fe-9ff5-eefa2f39bc6e
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986178059 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 30.rv_dm_tap_fsm_rand_reset.3986178059
Directory /workspace/30.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/31.rv_dm_tap_fsm_rand_reset.1212673693
Short name T367
Test name
Test status
Simulation time 13779825056 ps
CPU time 24.93 seconds
Started Mar 03 12:38:49 PM PST 24
Finished Mar 03 12:39:15 PM PST 24
Peak memory 220616 kb
Host smart-77b9c2f6-c880-43c6-bf21-1c2ad85baf74
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212673693 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 31.rv_dm_tap_fsm_rand_reset.1212673693
Directory /workspace/31.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/32.rv_dm_tap_fsm_rand_reset.3912394141
Short name T320
Test name
Test status
Simulation time 15071591508 ps
CPU time 13.76 seconds
Started Mar 03 12:38:51 PM PST 24
Finished Mar 03 12:39:05 PM PST 24
Peak memory 212608 kb
Host smart-310b83ca-1711-404a-8751-bd19ef88c54d
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912394141 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 32.rv_dm_tap_fsm_rand_reset.3912394141
Directory /workspace/32.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/34.rv_dm_tap_fsm_rand_reset.3414687583
Short name T317
Test name
Test status
Simulation time 20918596851 ps
CPU time 22.02 seconds
Started Mar 03 12:38:54 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 220868 kb
Host smart-cf69edb9-994a-4526-8d8e-2496c3c83f69
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414687583 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 34.rv_dm_tap_fsm_rand_reset.3414687583
Directory /workspace/34.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/35.rv_dm_tap_fsm_rand_reset.151873171
Short name T285
Test name
Test status
Simulation time 22073794729 ps
CPU time 23.43 seconds
Started Mar 03 12:38:52 PM PST 24
Finished Mar 03 12:39:16 PM PST 24
Peak memory 220796 kb
Host smart-65c68d00-9dfd-4f69-9ac5-140abad8d901
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151873171 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 35.rv_dm_tap_fsm_rand_reset.151873171
Directory /workspace/35.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/39.rv_dm_tap_fsm_rand_reset.537379280
Short name T118
Test name
Test status
Simulation time 7396173084 ps
CPU time 21.61 seconds
Started Mar 03 12:38:53 PM PST 24
Finished Mar 03 12:39:15 PM PST 24
Peak memory 212688 kb
Host smart-d4d5fb82-7982-49fd-aff3-0ef63438db41
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537379280 -assert nopostproc +UVM_TESTNAM
E=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 39.rv_dm_tap_fsm_rand_reset.537379280
Directory /workspace/39.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_aliasing.165898333
Short name T140
Test name
Test status
Simulation time 575137466 ps
CPU time 26.13 seconds
Started Mar 03 12:38:17 PM PST 24
Finished Mar 03 12:38:44 PM PST 24
Peak memory 204288 kb
Host smart-e01b46c1-d398-4c9a-9ea3-40c05ff55d78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=100_000_000 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165898333 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +U
VM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_na
me 4.rv_dm_csr_aliasing.165898333
Directory /workspace/4.rv_dm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_bit_bash.2957025764
Short name T263
Test name
Test status
Simulation time 3439635936 ps
CPU time 35.14 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:39:01 PM PST 24
Peak memory 204296 kb
Host smart-38dbd83f-44c5-4870-8dc5-a2299e7384b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957025764 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_bit_bash.2957025764
Directory /workspace/4.rv_dm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_hw_reset.1711825369
Short name T94
Test name
Test status
Simulation time 310352758 ps
CPU time 1.52 seconds
Started Mar 03 12:38:21 PM PST 24
Finished Mar 03 12:38:22 PM PST 24
Peak memory 204312 kb
Host smart-adb5212e-ef96-46d4-85dc-4b927713f4a0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711825369 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_hw_reset.1711825369
Directory /workspace/4.rv_dm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_mem_rw_with_rand_reset.1913337999
Short name T363
Test name
Test status
Simulation time 636121348 ps
CPU time 3.58 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 220876 kb
Host smart-3d76839c-0d48-47fd-a9c0-1d1450b239dd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913337999 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.rv_dm_csr_mem_rw_with_rand_reset.1913337999
Directory /workspace/4.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_csr_rw.1870788937
Short name T84
Test name
Test status
Simulation time 86034524 ps
CPU time 1.42 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:38:28 PM PST 24
Peak memory 204324 kb
Host smart-19807bc3-81f9-446a-be5e-696ec302a8de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870788937 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_csr_rw.1870788937
Directory /workspace/4.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_aliasing.1119179166
Short name T354
Test name
Test status
Simulation time 3219347261 ps
CPU time 7.14 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:29 PM PST 24
Peak memory 204212 kb
Host smart-e2080b55-b2a4-4f82-a962-d707a335b207
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119179166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_aliasing.1119179166
Directory /workspace/4.rv_dm_jtag_dmi_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_bit_bash.3074257327
Short name T322
Test name
Test status
Simulation time 13655393182 ps
CPU time 27.93 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:50 PM PST 24
Peak memory 204296 kb
Host smart-e233db26-bc5f-4111-a2e4-de1684e480f3
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074257327 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_bit_bash.3074257327
Directory /workspace/4.rv_dm_jtag_dmi_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_hw_reset.1801574566
Short name T90
Test name
Test status
Simulation time 2536457117 ps
CPU time 2.9 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:25 PM PST 24
Peak memory 204412 kb
Host smart-f6cd745b-31d2-47bb-8e6e-21c11f6ccfa9
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801574566 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_cs
r_hw_reset.1801574566
Directory /workspace/4.rv_dm_jtag_dmi_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dmi_csr_rw.3765088167
Short name T283
Test name
Test status
Simulation time 428801913 ps
CPU time 1.41 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 204188 kb
Host smart-109a7801-7484-407b-80bd-33f0a4e385f1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765088167 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dmi_csr_rw.3
765088167
Directory /workspace/4.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_aliasing.2383364065
Short name T373
Test name
Test status
Simulation time 148528950 ps
CPU time 0.77 seconds
Started Mar 03 12:38:15 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 204124 kb
Host smart-2fdb1d8f-cda1-46f2-8cee-fce9fe740554
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_aliasing +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383364065 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_aliasing.2383364065
Directory /workspace/4.rv_dm_jtag_dtm_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_bit_bash.4183146256
Short name T275
Test name
Test status
Simulation time 844686957 ps
CPU time 3.52 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:21 PM PST 24
Peak memory 204240 kb
Host smart-e6f22683-44f2-4d61-a09a-36c6cd0708fc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_bit_bash +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183146256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_bit_bash.4183146256
Directory /workspace/4.rv_dm_jtag_dtm_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_hw_reset.3035009484
Short name T244
Test name
Test status
Simulation time 72844592 ps
CPU time 0.69 seconds
Started Mar 03 12:38:16 PM PST 24
Finished Mar 03 12:38:17 PM PST 24
Peak memory 203992 kb
Host smart-c3f6482d-0ae6-4d7e-8467-bbf196b7c664
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_hw_reset +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035009484 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_c
sr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_cs
r_hw_reset.3035009484
Directory /workspace/4.rv_dm_jtag_dtm_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_jtag_dtm_csr_rw.2079870552
Short name T277
Test name
Test status
Simulation time 50527976 ps
CPU time 0.68 seconds
Started Mar 03 12:38:19 PM PST 24
Finished Mar 03 12:38:20 PM PST 24
Peak memory 203912 kb
Host smart-38a7268f-afb3-418d-922b-f5d8a57abacc
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079870552 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_jtag_dtm_csr_rw.2
079870552
Directory /workspace/4.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_partial_access.1726193449
Short name T319
Test name
Test status
Simulation time 17504593 ps
CPU time 0.66 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:36 PM PST 24
Peak memory 204076 kb
Host smart-83f83671-f98f-4b31-a6cd-bfaf07fca865
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726193449 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_par
tial_access.1726193449
Directory /workspace/4.rv_dm_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_mem_walk.1785300365
Short name T297
Test name
Test status
Simulation time 34303471 ps
CPU time 0.69 seconds
Started Mar 03 12:38:22 PM PST 24
Finished Mar 03 12:38:22 PM PST 24
Peak memory 203992 kb
Host smart-11468203-4bdf-4361-9f04-25703ef64f94
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785300365 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_mem_walk.1785300365
Directory /workspace/4.rv_dm_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_same_csr_outstanding.3205826239
Short name T329
Test name
Test status
Simulation time 818498210 ps
CPU time 4.41 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:38:31 PM PST 24
Peak memory 204464 kb
Host smart-42d90260-7ed8-42fb-acf3-6babb9cada97
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205826239 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_same_
csr_outstanding.3205826239
Directory /workspace/4.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_errors.1629795331
Short name T143
Test name
Test status
Simulation time 997941305 ps
CPU time 4.89 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:38:31 PM PST 24
Peak memory 204756 kb
Host smart-9038ca5a-e0f6-4a50-8603-ebab364f31b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629795331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_errors.1629795331
Directory /workspace/4.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rv_dm_tl_intg_err.2757702477
Short name T126
Test name
Test status
Simulation time 726049747 ps
CPU time 14.82 seconds
Started Mar 03 12:38:18 PM PST 24
Finished Mar 03 12:38:33 PM PST 24
Peak memory 212408 kb
Host smart-92df73be-ebb6-4ffe-b9f4-c4c225b68848
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757702477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rv_dm_tl_intg_err.2757702477
Directory /workspace/4.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_mem_rw_with_rand_reset.2233144539
Short name T52
Test name
Test status
Simulation time 2018627180 ps
CPU time 3.28 seconds
Started Mar 03 12:38:24 PM PST 24
Finished Mar 03 12:38:27 PM PST 24
Peak memory 214692 kb
Host smart-46b8bfed-e146-4a91-9d42-76cc8fc0dfd3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233144539 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.rv_dm_csr_mem_rw_with_rand_reset.2233144539
Directory /workspace/5.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_csr_rw.2062298359
Short name T353
Test name
Test status
Simulation time 213687433 ps
CPU time 1.44 seconds
Started Mar 03 12:38:27 PM PST 24
Finished Mar 03 12:38:30 PM PST 24
Peak memory 204312 kb
Host smart-037c72f6-8b30-441d-9bff-b565276daf65
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062298359 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_csr_rw.2062298359
Directory /workspace/5.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dmi_csr_rw.1991722973
Short name T338
Test name
Test status
Simulation time 732492907 ps
CPU time 2.37 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:36 PM PST 24
Peak memory 204292 kb
Host smart-0bdb79f3-a65a-4be0-a344-1a4ff4ffb9fd
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991722973 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dmi_csr_rw.1
991722973
Directory /workspace/5.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_jtag_dtm_csr_rw.2369691469
Short name T374
Test name
Test status
Simulation time 111865142 ps
CPU time 0.71 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:34 PM PST 24
Peak memory 204056 kb
Host smart-bcbb5e3e-5f28-4e7f-8fe9-f1290d9ca099
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369691469 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_jtag_dtm_csr_rw.2
369691469
Directory /workspace/5.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_same_csr_outstanding.727967519
Short name T335
Test name
Test status
Simulation time 256367622 ps
CPU time 4.1 seconds
Started Mar 03 12:38:33 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 204432 kb
Host smart-e22c85ac-6ee3-474f-a5c2-1a746417df2a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727967519 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_same_c
sr_outstanding.727967519
Directory /workspace/5.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_errors.3863783261
Short name T77
Test name
Test status
Simulation time 36362877 ps
CPU time 1.99 seconds
Started Mar 03 12:38:23 PM PST 24
Finished Mar 03 12:38:25 PM PST 24
Peak memory 204384 kb
Host smart-62a3e1ce-301f-48c6-9fa3-870b05838175
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863783261 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_errors.3863783261
Directory /workspace/5.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rv_dm_tl_intg_err.3023579564
Short name T129
Test name
Test status
Simulation time 3800621444 ps
CPU time 16.87 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:53 PM PST 24
Peak memory 213344 kb
Host smart-74a82f0d-d8ac-43ea-bc63-044192c2dadf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023579564 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rv_dm_tl_intg_err.3023579564
Directory /workspace/5.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_mem_rw_with_rand_reset.2567496787
Short name T146
Test name
Test status
Simulation time 7375406468 ps
CPU time 13.87 seconds
Started Mar 03 12:38:23 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 216012 kb
Host smart-2201dea0-3a1a-4f3f-b040-1cdb058054b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567496787 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.rv_dm_csr_mem_rw_with_rand_reset.2567496787
Directory /workspace/6.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_csr_rw.1619591256
Short name T326
Test name
Test status
Simulation time 172261498 ps
CPU time 2.2 seconds
Started Mar 03 12:38:24 PM PST 24
Finished Mar 03 12:38:26 PM PST 24
Peak memory 204356 kb
Host smart-ad333fc9-0f0c-46b7-88c9-07a8e95a6f58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619591256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_csr_rw.1619591256
Directory /workspace/6.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dmi_csr_rw.2574765912
Short name T240
Test name
Test status
Simulation time 180610959 ps
CPU time 0.93 seconds
Started Mar 03 12:38:37 PM PST 24
Finished Mar 03 12:38:39 PM PST 24
Peak memory 204200 kb
Host smart-fdc7c2e0-24c0-493c-9e93-ac345eed1a74
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574765912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dmi_csr_rw.2
574765912
Directory /workspace/6.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_jtag_dtm_csr_rw.764030734
Short name T308
Test name
Test status
Simulation time 71658059 ps
CPU time 0.66 seconds
Started Mar 03 12:38:33 PM PST 24
Finished Mar 03 12:38:34 PM PST 24
Peak memory 204076 kb
Host smart-219a4e5d-219c-412c-ab4a-93345434ca03
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=764030734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_jtag_dtm_csr_rw.764030734
Directory /workspace/6.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_same_csr_outstanding.3206327769
Short name T109
Test name
Test status
Simulation time 535261448 ps
CPU time 6.28 seconds
Started Mar 03 12:38:35 PM PST 24
Finished Mar 03 12:38:42 PM PST 24
Peak memory 204368 kb
Host smart-3c54f233-eb3e-47aa-a374-0a55c08f92b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206327769 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_same_
csr_outstanding.3206327769
Directory /workspace/6.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_errors.3618343126
Short name T249
Test name
Test status
Simulation time 245247885 ps
CPU time 6.38 seconds
Started Mar 03 12:38:28 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 212604 kb
Host smart-e2960035-e17c-433d-b196-64b531b51d8c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618343126 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_errors.3618343126
Directory /workspace/6.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rv_dm_tl_intg_err.69078294
Short name T306
Test name
Test status
Simulation time 257867016 ps
CPU time 7.75 seconds
Started Mar 03 12:38:29 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 212504 kb
Host smart-74336b21-4789-4bed-9333-67e323fbf030
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69078294 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rv_dm_tl_intg_err.69078294
Directory /workspace/6.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_mem_rw_with_rand_reset.2009360293
Short name T281
Test name
Test status
Simulation time 1542609014 ps
CPU time 3.82 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:38:30 PM PST 24
Peak memory 220148 kb
Host smart-12c74447-86f8-4db9-b6ed-82051286d95b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009360293 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.rv_dm_csr_mem_rw_with_rand_reset.2009360293
Directory /workspace/7.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_csr_rw.226535078
Short name T313
Test name
Test status
Simulation time 85999036 ps
CPU time 1.4 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 204324 kb
Host smart-e783aea5-6f86-443f-a137-d37c9385a5b8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226535078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_csr_rw.226535078
Directory /workspace/7.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dmi_csr_rw.555253491
Short name T375
Test name
Test status
Simulation time 370475032 ps
CPU time 1.33 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:39 PM PST 24
Peak memory 204172 kb
Host smart-59e867ff-fbe9-46ff-a43a-55afa2b6ebfe
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555253491 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dmi_csr_rw.555253491
Directory /workspace/7.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_jtag_dtm_csr_rw.871511638
Short name T336
Test name
Test status
Simulation time 94245270 ps
CPU time 0.67 seconds
Started Mar 03 12:38:38 PM PST 24
Finished Mar 03 12:38:40 PM PST 24
Peak memory 203960 kb
Host smart-779462d5-1836-422e-b8b6-d96d16316227
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871511638 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_jtag_dtm_csr_rw.871511638
Directory /workspace/7.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_same_csr_outstanding.1972847815
Short name T312
Test name
Test status
Simulation time 265631769 ps
CPU time 4.17 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:42 PM PST 24
Peak memory 204248 kb
Host smart-b549e8c0-4e8d-4fb4-8a83-5861831a5a29
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972847815 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_d
m_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_same_
csr_outstanding.1972847815
Directory /workspace/7.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_errors.38841285
Short name T148
Test name
Test status
Simulation time 92148073 ps
CPU time 2.25 seconds
Started Mar 03 12:38:24 PM PST 24
Finished Mar 03 12:38:26 PM PST 24
Peak memory 212732 kb
Host smart-412c2bc4-b10a-4b43-9665-9e39c2a3da85
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38841285 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_errors.38841285
Directory /workspace/7.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rv_dm_tl_intg_err.2711065715
Short name T123
Test name
Test status
Simulation time 2731933537 ps
CPU time 14.44 seconds
Started Mar 03 12:38:26 PM PST 24
Finished Mar 03 12:38:41 PM PST 24
Peak memory 212928 kb
Host smart-0cddcf61-9604-426c-be9b-d40cdd92ce90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711065715 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rv_dm_tl_intg_err.2711065715
Directory /workspace/7.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_mem_rw_with_rand_reset.1528160441
Short name T376
Test name
Test status
Simulation time 64337025 ps
CPU time 2.11 seconds
Started Mar 03 12:38:38 PM PST 24
Finished Mar 03 12:38:41 PM PST 24
Peak memory 213904 kb
Host smart-958bef7f-5dab-4ee2-8b6c-b9646074467b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528160441 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.rv_dm_csr_mem_rw_with_rand_reset.1528160441
Directory /workspace/8.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_csr_rw.2042819644
Short name T92
Test name
Test status
Simulation time 33985514 ps
CPU time 1.42 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:39 PM PST 24
Peak memory 212484 kb
Host smart-5fef5011-1b15-4cbf-a2da-002fbc145bfa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042819644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_csr_rw.2042819644
Directory /workspace/8.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dmi_csr_rw.1102199353
Short name T239
Test name
Test status
Simulation time 641902047 ps
CPU time 1.9 seconds
Started Mar 03 12:38:27 PM PST 24
Finished Mar 03 12:38:31 PM PST 24
Peak memory 204240 kb
Host smart-04d61058-abad-4aed-8894-c2783cfff302
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102199353 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dmi_csr_rw.1
102199353
Directory /workspace/8.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_jtag_dtm_csr_rw.3964584911
Short name T71
Test name
Test status
Simulation time 80742700 ps
CPU time 0.71 seconds
Started Mar 03 12:38:27 PM PST 24
Finished Mar 03 12:38:27 PM PST 24
Peak memory 204012 kb
Host smart-897ca8a4-e306-4241-a3f4-51269934947f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964584911 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_jtag_dtm_csr_rw.3
964584911
Directory /workspace/8.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_same_csr_outstanding.935423293
Short name T316
Test name
Test status
Simulation time 480341934 ps
CPU time 7.27 seconds
Started Mar 03 12:38:29 PM PST 24
Finished Mar 03 12:38:37 PM PST 24
Peak memory 204356 kb
Host smart-710f082d-fb6f-41ce-9e46-af29b13a0638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935423293 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_same_c
sr_outstanding.935423293
Directory /workspace/8.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_errors.827060968
Short name T76
Test name
Test status
Simulation time 471922253 ps
CPU time 6.32 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:43 PM PST 24
Peak memory 212624 kb
Host smart-3453307e-5e83-4d0a-8537-16a2cac91809
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827060968 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_errors.827060968
Directory /workspace/8.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rv_dm_tl_intg_err.751439192
Short name T120
Test name
Test status
Simulation time 7631580873 ps
CPU time 14.83 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:52 PM PST 24
Peak memory 212168 kb
Host smart-daa064d0-5f2f-471b-b815-cb995edaea52
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751439192 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rv_dm_tl_intg_err.751439192
Directory /workspace/8.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_mem_rw_with_rand_reset.4050602343
Short name T292
Test name
Test status
Simulation time 153961881 ps
CPU time 3.9 seconds
Started Mar 03 12:38:31 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 216684 kb
Host smart-260a0cad-98ae-4099-ad4f-6b6eba1a327d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050602343 -assert nopostproc +UVM_TESTNAME
=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.rv_dm_csr_mem_rw_with_rand_reset.4050602343
Directory /workspace/9.rv_dm_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_csr_rw.4012056507
Short name T352
Test name
Test status
Simulation time 135988340 ps
CPU time 2.21 seconds
Started Mar 03 12:38:32 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 204288 kb
Host smart-3154e476-f694-45b9-802e-f7a5f3d17a46
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012056507 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_csr_rw.4012056507
Directory /workspace/9.rv_dm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dmi_csr_rw.808610981
Short name T364
Test name
Test status
Simulation time 247005543 ps
CPU time 1.15 seconds
Started Mar 03 12:38:34 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 204236 kb
Host smart-7f967b01-b249-43a7-9979-bf70774309c1
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808610981 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_csr_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dmi_csr_rw.808610981
Directory /workspace/9.rv_dm_jtag_dmi_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_jtag_dtm_csr_rw.4217755237
Short name T348
Test name
Test status
Simulation time 68710473 ps
CPU time 0.78 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:38 PM PST 24
Peak memory 203464 kb
Host smart-816e00d5-4341-4ffb-ab29-6dec813ce09f
User root
Command /workspace/cover_reg_top/simv +en_scb=0 +csr_rw +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217755237 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_csr_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_jtag_dtm_csr_rw.4
217755237
Directory /workspace/9.rv_dm_jtag_dtm_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_same_csr_outstanding.37999280
Short name T108
Test name
Test status
Simulation time 161540610 ps
CPU time 3.72 seconds
Started Mar 03 12:38:31 PM PST 24
Finished Mar 03 12:38:35 PM PST 24
Peak memory 204344 kb
Host smart-b36a5f8c-b85b-4f70-9dd6-050e4dd09920
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37999280 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_same_cs
r_outstanding.37999280
Directory /workspace/9.rv_dm_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tap_fsm_rand_reset.2318927824
Short name T245
Test name
Test status
Simulation time 14594113493 ps
CPU time 12.69 seconds
Started Mar 03 12:38:36 PM PST 24
Finished Mar 03 12:38:50 PM PST 24
Peak memory 212692 kb
Host smart-334d6adb-5ed6-444d-9478-42c4b106d456
User root
Command /workspace/cover_reg_top/simv +run_stress_all_with_rand_reset +stress_seq=rv_dm_tap_fsm_vseq +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318927824 -assert nopostproc +UVM_TESTNA
ME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rv_dm_tap_fsm_rand_reset.2318927824
Directory /workspace/9.rv_dm_tap_fsm_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_errors.3993047949
Short name T341
Test name
Test status
Simulation time 138203593 ps
CPU time 4.4 seconds
Started Mar 03 12:38:23 PM PST 24
Finished Mar 03 12:38:28 PM PST 24
Peak memory 212652 kb
Host smart-a0a41ff6-8037-4662-ab8e-7be2f1709ec6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993047949 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_errors.3993047949
Directory /workspace/9.rv_dm_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rv_dm_tl_intg_err.1401076211
Short name T127
Test name
Test status
Simulation time 2128465003 ps
CPU time 18.48 seconds
Started Mar 03 12:38:33 PM PST 24
Finished Mar 03 12:38:51 PM PST 24
Peak memory 213436 kb
Host smart-1686920e-9add-430b-8f29-1f16e58d89a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401076211 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rv_dm_tl_intg_err.1401076211
Directory /workspace/9.rv_dm_tl_intg_err/latest

Test location /workspace/coverage/default/0.rv_dm_alert_test.213071902
Short name T230
Test name
Test status
Simulation time 27475910 ps
CPU time 0.68 seconds
Started Mar 03 12:34:24 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 203648 kb
Host smart-493ddbd0-feb3-454f-b137-65fa89df661e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213071902 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_alert_test.213071902
Directory /workspace/0.rv_dm_alert_test/latest

Test location /workspace/coverage/default/0.rv_dm_autoincr_sba_tl_access.3191017125
Short name T233
Test name
Test status
Simulation time 1114953431 ps
CPU time 2.95 seconds
Started Mar 03 12:34:27 PM PST 24
Finished Mar 03 12:34:30 PM PST 24
Peak memory 203956 kb
Host smart-ea0b53f7-aaa1-40cd-9384-d635bb4dbdfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3191017125 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_autoincr_sba_tl_access.3191017125
Directory /workspace/0.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_bad_sba_tl_access.1604399001
Short name T224
Test name
Test status
Simulation time 3826097194 ps
CPU time 6.8 seconds
Started Mar 03 12:33:57 PM PST 24
Finished Mar 03 12:34:10 PM PST 24
Peak memory 204032 kb
Host smart-beb3b348-585f-40fa-aa8e-0217f78fffaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604399001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_bad_sba_tl_access.1604399001
Directory /workspace/0.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_busy.3960791843
Short name T9
Test name
Test status
Simulation time 2436421063 ps
CPU time 7.86 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 203852 kb
Host smart-ae4805ba-83fd-4d6e-90a5-66d198753e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960791843 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_busy_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_busy.3960791843
Directory /workspace/0.rv_dm_cmderr_busy/latest

Test location /workspace/coverage/default/0.rv_dm_cmderr_not_supported.1868475869
Short name T18
Test name
Test status
Simulation time 3325496133 ps
CPU time 3.24 seconds
Started Mar 03 12:34:01 PM PST 24
Finished Mar 03 12:34:04 PM PST 24
Peak memory 203916 kb
Host smart-a0dbd123-78b7-4f17-a323-0c128179d2b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868475869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_not_supported_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_cmderr_not_supported.1868475869
Directory /workspace/0.rv_dm_cmderr_not_supported/latest

Test location /workspace/coverage/default/0.rv_dm_dataaddr_rw_access.2928075794
Short name T19
Test name
Test status
Simulation time 67585774 ps
CPU time 0.83 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 203724 kb
Host smart-8f4864fa-76e0-41da-8691-7b32d4f168f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928075794 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_dataaddr_rw_access.2928075794
Directory /workspace/0.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/0.rv_dm_delayed_resp_sba_tl_access.2866712351
Short name T166
Test name
Test status
Simulation time 2165288051 ps
CPU time 7.46 seconds
Started Mar 03 12:34:14 PM PST 24
Finished Mar 03 12:34:32 PM PST 24
Peak memory 204076 kb
Host smart-9375b321-5bac-4cf7-b210-04d7d0be4de0
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2866712351 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_delayed_resp_sba_t
l_access.2866712351
Directory /workspace/0.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_halt_resume_whereto.1932570647
Short name T78
Test name
Test status
Simulation time 164833287 ps
CPU time 0.85 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203656 kb
Host smart-658d6656-d4f0-43cb-8177-2974d2c31262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932570647 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_halt_resume_whereto.1932570647
Directory /workspace/0.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/0.rv_dm_hart_unavail.3037446568
Short name T189
Test name
Test status
Simulation time 35942891 ps
CPU time 0.7 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203568 kb
Host smart-a881ce1e-1cb8-4f80-be67-d0eeed2fe482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037446568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_hart_unavail.3037446568
Directory /workspace/0.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dmi_dm_inactive.2441761009
Short name T235
Test name
Test status
Simulation time 85713652 ps
CPU time 0.78 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203612 kb
Host smart-d139b5f4-e166-49cd-b46b-9c50a20b0313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441761009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dmi_dm_inactive.2441761009
Directory /workspace/0.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_hard_reset.2192495358
Short name T192
Test name
Test status
Simulation time 115584314 ps
CPU time 0.71 seconds
Started Mar 03 12:34:20 PM PST 24
Finished Mar 03 12:34:21 PM PST 24
Peak memory 203616 kb
Host smart-72bc6952-b954-4b8e-9499-71924ef79958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192495358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_hard_reset.2192495358
Directory /workspace/0.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/0.rv_dm_jtag_dtm_idle_hint.4051726131
Short name T60
Test name
Test status
Simulation time 93490338 ps
CPU time 0.72 seconds
Started Mar 03 12:34:35 PM PST 24
Finished Mar 03 12:34:37 PM PST 24
Peak memory 203372 kb
Host smart-d7dcd4c1-d926-47c6-8b45-c22999f8162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051726131 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_jtag_dtm_idle_hint.4051726131
Directory /workspace/0.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_halted.2516158016
Short name T136
Test name
Test status
Simulation time 66338918 ps
CPU time 0.78 seconds
Started Mar 03 12:34:02 PM PST 24
Finished Mar 03 12:34:03 PM PST 24
Peak memory 203704 kb
Host smart-d484809b-5556-4cb3-9a6f-69759bb0dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516158016 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_halted.2516158016
Directory /workspace/0.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/0.rv_dm_mem_tl_access_resuming.2319276666
Short name T183
Test name
Test status
Simulation time 1119599492 ps
CPU time 1.54 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:12 PM PST 24
Peak memory 203788 kb
Host smart-5c19a1a4-6e54-41ae-9621-956b514eb205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319276666 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_mem_tl_access_resuming.2319276666
Directory /workspace/0.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/0.rv_dm_ndmreset_req.345934928
Short name T134
Test name
Test status
Simulation time 1074358714 ps
CPU time 2.41 seconds
Started Mar 03 12:34:41 PM PST 24
Finished Mar 03 12:34:43 PM PST 24
Peak memory 203720 kb
Host smart-b79b7f6d-0168-45d0-84df-d31b3e641048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345934928 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_ndmreset_req.345934928
Directory /workspace/0.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/0.rv_dm_sba_tl_access.960011345
Short name T169
Test name
Test status
Simulation time 435332585 ps
CPU time 2.67 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203944 kb
Host smart-2d6de31e-69c1-4a8e-b7be-1d020f744c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960011345 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sba_tl_access.960011345
Directory /workspace/0.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/0.rv_dm_sec_cm.4022202236
Short name T62
Test name
Test status
Simulation time 94989379 ps
CPU time 1.08 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:18 PM PST 24
Peak memory 218620 kb
Host smart-51d482b6-eb69-4a98-93b1-6d8c742817b1
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022202236 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_sec_cm.4022202236
Directory /workspace/0.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/0.rv_dm_smoke.4213617388
Short name T207
Test name
Test status
Simulation time 292389956 ps
CPU time 1.07 seconds
Started Mar 03 12:34:03 PM PST 24
Finished Mar 03 12:34:05 PM PST 24
Peak memory 203376 kb
Host smart-15ba44db-8a6c-433e-b27b-92b9a1517f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4213617388 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_smoke.4213617388
Directory /workspace/0.rv_dm_smoke/latest

Test location /workspace/coverage/default/0.rv_dm_tap_fsm.3211147001
Short name T57
Test name
Test status
Simulation time 2760005973 ps
CPU time 3.19 seconds
Started Mar 03 12:34:00 PM PST 24
Finished Mar 03 12:34:04 PM PST 24
Peak memory 203788 kb
Host smart-d77b6f0e-0545-456d-9758-5b3e2fee940b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211147001 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_tap_fsm_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rv_dm_tap_fsm.3211147001
Directory /workspace/0.rv_dm_tap_fsm/latest

Test location /workspace/coverage/default/1.rv_dm_bad_sba_tl_access.950829853
Short name T68
Test name
Test status
Simulation time 936826986 ps
CPU time 2.36 seconds
Started Mar 03 12:34:23 PM PST 24
Finished Mar 03 12:34:27 PM PST 24
Peak memory 204340 kb
Host smart-979ec600-2548-4336-b1ef-34cdf56b184a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950829853 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_bad_sba_tl_access.950829853
Directory /workspace/1.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_exception.1551820560
Short name T24
Test name
Test status
Simulation time 160706740 ps
CPU time 1 seconds
Started Mar 03 12:34:04 PM PST 24
Finished Mar 03 12:34:05 PM PST 24
Peak memory 203688 kb
Host smart-c0fbc357-244e-4f28-b8cd-e7771f1cea62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551820560 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_exception_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_exception.1551820560
Directory /workspace/1.rv_dm_cmderr_exception/latest

Test location /workspace/coverage/default/1.rv_dm_cmderr_halt_resume.475980312
Short name T21
Test name
Test status
Simulation time 93096168 ps
CPU time 0.85 seconds
Started Mar 03 12:34:23 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 203344 kb
Host smart-71bb8228-f748-4b99-8e4f-f41aaf576494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475980312 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_cmderr_halt_resume_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_cmderr_halt_resume.475980312
Directory /workspace/1.rv_dm_cmderr_halt_resume/latest

Test location /workspace/coverage/default/1.rv_dm_dataaddr_rw_access.1861619331
Short name T217
Test name
Test status
Simulation time 193592994 ps
CPU time 0.67 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203500 kb
Host smart-c7b5138f-4ae9-4912-8d79-9401f9820de6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861619331 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_dataaddr_rw_access_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_dataaddr_rw_access.1861619331
Directory /workspace/1.rv_dm_dataaddr_rw_access/latest

Test location /workspace/coverage/default/1.rv_dm_delayed_resp_sba_tl_access.1421665426
Short name T212
Test name
Test status
Simulation time 12446929910 ps
CPU time 38.41 seconds
Started Mar 03 12:34:19 PM PST 24
Finished Mar 03 12:34:58 PM PST 24
Peak memory 204048 kb
Host smart-8bef7e8e-fd57-480c-9b03-9e6d5ae9dcd7
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1421665426 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_delayed_resp_sba_t
l_access.1421665426
Directory /workspace/1.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_halt_resume_whereto.740567920
Short name T132
Test name
Test status
Simulation time 469328977 ps
CPU time 1.48 seconds
Started Mar 03 12:34:24 PM PST 24
Finished Mar 03 12:34:26 PM PST 24
Peak memory 203852 kb
Host smart-d59fdb57-4183-476c-8d43-fbc3a0d765b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740567920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_halt_resume_whereto_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_halt_resume_whereto.740567920
Directory /workspace/1.rv_dm_halt_resume_whereto/latest

Test location /workspace/coverage/default/1.rv_dm_hart_unavail.2747380644
Short name T201
Test name
Test status
Simulation time 81101653 ps
CPU time 0.69 seconds
Started Mar 03 12:34:20 PM PST 24
Finished Mar 03 12:34:21 PM PST 24
Peak memory 203612 kb
Host smart-ef9d58f8-2137-4d40-8f70-77eb1b39b8fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747380644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_hart_unavail.2747380644
Directory /workspace/1.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_debug_disabled.1433071796
Short name T204
Test name
Test status
Simulation time 345536486 ps
CPU time 1.17 seconds
Started Mar 03 12:34:06 PM PST 24
Finished Mar 03 12:34:08 PM PST 24
Peak memory 203792 kb
Host smart-da9ee33c-5267-41ed-aca9-bf064286714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433071796 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_debug_disabled_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_debug_disabled.1433071796
Directory /workspace/1.rv_dm_jtag_dmi_debug_disabled/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dmi_dm_inactive.4106713446
Short name T234
Test name
Test status
Simulation time 146308775 ps
CPU time 0.74 seconds
Started Mar 03 12:34:16 PM PST 24
Finished Mar 03 12:34:18 PM PST 24
Peak memory 203476 kb
Host smart-0fcf859a-94f8-49cc-bbd0-d2fd77c7534a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106713446 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dmi_dm_inactive_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dmi_dm_inactive.4106713446
Directory /workspace/1.rv_dm_jtag_dmi_dm_inactive/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_hard_reset.1292347059
Short name T17
Test name
Test status
Simulation time 311711975 ps
CPU time 0.81 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203644 kb
Host smart-1667c130-5403-4748-a563-210c0b2266c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292347059 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_hard_reset_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_hard_reset.1292347059
Directory /workspace/1.rv_dm_jtag_dtm_hard_reset/latest

Test location /workspace/coverage/default/1.rv_dm_jtag_dtm_idle_hint.4032751380
Short name T221
Test name
Test status
Simulation time 41448622 ps
CPU time 0.69 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 203656 kb
Host smart-c08b34f4-e21b-4a22-8b24-aadeeb278c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032751380 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_jtag_dtm_idle_hint_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_jtag_dtm_idle_hint.4032751380
Directory /workspace/1.rv_dm_jtag_dtm_idle_hint/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_halted.2062333295
Short name T74
Test name
Test status
Simulation time 253904428 ps
CPU time 0.86 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:12 PM PST 24
Peak memory 203688 kb
Host smart-9b696697-8297-4260-9e11-339cc8e2f10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062333295 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_halted_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_halted.2062333295
Directory /workspace/1.rv_dm_mem_tl_access_halted/latest

Test location /workspace/coverage/default/1.rv_dm_mem_tl_access_resuming.237918260
Short name T137
Test name
Test status
Simulation time 158371431 ps
CPU time 0.92 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203700 kb
Host smart-f5787008-5c8f-44c0-8b53-d8aec90b1ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237918260 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_mem_tl_access_resuming_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_mem_tl_access_resuming.237918260
Directory /workspace/1.rv_dm_mem_tl_access_resuming/latest

Test location /workspace/coverage/default/1.rv_dm_ndmreset_req.1673415632
Short name T135
Test name
Test status
Simulation time 517054218 ps
CPU time 2.31 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:14 PM PST 24
Peak memory 203828 kb
Host smart-76cc3c69-c71a-45cc-96b1-6eab0f05d273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673415632 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_ndmreset_req_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_ndmreset_req.1673415632
Directory /workspace/1.rv_dm_ndmreset_req/latest

Test location /workspace/coverage/default/1.rv_dm_progbuf_busy.3829826643
Short name T7
Test name
Test status
Simulation time 226746709 ps
CPU time 1.28 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:14 PM PST 24
Peak memory 203692 kb
Host smart-716b9985-752e-44bf-a3e8-76ed0f1be24b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829826643 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_progbuf_busy_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_progbuf_busy.3829826643
Directory /workspace/1.rv_dm_progbuf_busy/latest

Test location /workspace/coverage/default/1.rv_dm_rom_read_access.643053453
Short name T8
Test name
Test status
Simulation time 44505646 ps
CPU time 0.73 seconds
Started Mar 03 12:34:31 PM PST 24
Finished Mar 03 12:34:32 PM PST 24
Peak memory 203716 kb
Host smart-6643d12d-dac8-4c87-8286-cd98b7dfb0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643053453 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_rom_read_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_rom_read_access.643053453
Directory /workspace/1.rv_dm_rom_read_access/latest

Test location /workspace/coverage/default/1.rv_dm_sba_tl_access.2252283390
Short name T65
Test name
Test status
Simulation time 4678976380 ps
CPU time 6.16 seconds
Started Mar 03 12:34:02 PM PST 24
Finished Mar 03 12:34:08 PM PST 24
Peak memory 204020 kb
Host smart-bec60685-b180-41b6-ba25-04b731c4beb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252283390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sba_tl_access.2252283390
Directory /workspace/1.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/1.rv_dm_sec_cm.2822085323
Short name T35
Test name
Test status
Simulation time 112735976 ps
CPU time 0.94 seconds
Started Mar 03 12:34:04 PM PST 24
Finished Mar 03 12:34:05 PM PST 24
Peak memory 218420 kb
Host smart-c3e2ea86-57b7-4db5-a91c-e1f80e0e2bbe
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822085323 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_sec_cm.2822085323
Directory /workspace/1.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/1.rv_dm_smoke.2886915489
Short name T194
Test name
Test status
Simulation time 264186171 ps
CPU time 1.35 seconds
Started Mar 03 12:34:27 PM PST 24
Finished Mar 03 12:34:28 PM PST 24
Peak memory 203372 kb
Host smart-19df99e1-0a4a-46a1-8b6c-7ae69d341329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886915489 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rv_dm_smoke.2886915489
Directory /workspace/1.rv_dm_smoke/latest

Test location /workspace/coverage/default/10.rv_dm_alert_test.26061123
Short name T150
Test name
Test status
Simulation time 22467316 ps
CPU time 0.61 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:23 PM PST 24
Peak memory 203596 kb
Host smart-6348d2e3-b264-477c-9642-3de822bbc31d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26061123 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_alert_test.26061123
Directory /workspace/10.rv_dm_alert_test/latest

Test location /workspace/coverage/default/10.rv_dm_autoincr_sba_tl_access.1917143811
Short name T167
Test name
Test status
Simulation time 19485038847 ps
CPU time 45.24 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:57 PM PST 24
Peak memory 204032 kb
Host smart-a7316f96-2f15-460a-b07c-7b103013185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917143811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_autoincr_sba_tl_access.1917143811
Directory /workspace/10.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_bad_sba_tl_access.3387818832
Short name T86
Test name
Test status
Simulation time 2094105310 ps
CPU time 4.34 seconds
Started Mar 03 12:34:30 PM PST 24
Finished Mar 03 12:34:35 PM PST 24
Peak memory 204072 kb
Host smart-f37435af-d4ae-4780-b97e-67335511a693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387818832 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_bad_sba_tl_access.3387818832
Directory /workspace/10.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_delayed_resp_sba_tl_access.974695811
Short name T226
Test name
Test status
Simulation time 6375079728 ps
CPU time 7.23 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:20 PM PST 24
Peak memory 204004 kb
Host smart-677dee95-7f06-4a87-8f9c-abcbbaa56d1e
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=974695811 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_delayed_resp_sba_t
l_access.974695811
Directory /workspace/10.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_sba_tl_access.21840630
Short name T231
Test name
Test status
Simulation time 9303853068 ps
CPU time 16.25 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:29 PM PST 24
Peak memory 204064 kb
Host smart-e262f3fe-3921-45e2-af4d-fff1db1ea3bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21840630 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_sba_tl_access.21840630
Directory /workspace/10.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/10.rv_dm_stress_all.2307869107
Short name T79
Test name
Test status
Simulation time 3082557486 ps
CPU time 3.82 seconds
Started Mar 03 12:34:25 PM PST 24
Finished Mar 03 12:34:29 PM PST 24
Peak memory 203956 kb
Host smart-f9387712-1f52-4304-82db-d9eba2ed4ba5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307869107 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rv_dm_stress_all.2307869107
Directory /workspace/10.rv_dm_stress_all/latest

Test location /workspace/coverage/default/11.rv_dm_alert_test.2432700626
Short name T154
Test name
Test status
Simulation time 32743421 ps
CPU time 0.7 seconds
Started Mar 03 12:34:27 PM PST 24
Finished Mar 03 12:34:28 PM PST 24
Peak memory 203708 kb
Host smart-b3b48bd5-cd9c-4109-9176-b6a7b521531d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432700626 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_alert_test.2432700626
Directory /workspace/11.rv_dm_alert_test/latest

Test location /workspace/coverage/default/11.rv_dm_bad_sba_tl_access.4006110274
Short name T195
Test name
Test status
Simulation time 11651336000 ps
CPU time 12.05 seconds
Started Mar 03 12:34:31 PM PST 24
Finished Mar 03 12:34:43 PM PST 24
Peak memory 204032 kb
Host smart-9e0169d8-e35b-42ff-ae60-a009663aeedf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006110274 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_bad_sba_tl_access.4006110274
Directory /workspace/11.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_delayed_resp_sba_tl_access.4087553922
Short name T213
Test name
Test status
Simulation time 416639915 ps
CPU time 1.67 seconds
Started Mar 03 12:34:07 PM PST 24
Finished Mar 03 12:34:09 PM PST 24
Peak memory 204376 kb
Host smart-33161e69-6920-4543-a5c3-b16a12881c81
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4087553922 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_delayed_resp_sba_
tl_access.4087553922
Directory /workspace/11.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/11.rv_dm_sba_tl_access.3427567242
Short name T28
Test name
Test status
Simulation time 2213411627 ps
CPU time 4.83 seconds
Started Mar 03 12:34:38 PM PST 24
Finished Mar 03 12:34:43 PM PST 24
Peak memory 204136 kb
Host smart-b65330fe-053c-4351-9c2d-338e7dc099a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427567242 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rv_dm_sba_tl_access.3427567242
Directory /workspace/11.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_alert_test.1094674590
Short name T205
Test name
Test status
Simulation time 36742804 ps
CPU time 0.64 seconds
Started Mar 03 12:34:28 PM PST 24
Finished Mar 03 12:34:29 PM PST 24
Peak memory 203652 kb
Host smart-5c3f0319-1369-412b-90c1-d4dae163abd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094674590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_alert_test.1094674590
Directory /workspace/12.rv_dm_alert_test/latest

Test location /workspace/coverage/default/12.rv_dm_autoincr_sba_tl_access.838573081
Short name T181
Test name
Test status
Simulation time 49732789665 ps
CPU time 133.35 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:39:41 PM PST 24
Peak memory 203996 kb
Host smart-fc561536-15b9-4765-8c4d-599917cdc6c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838573081 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_autoincr_sba_tl_access.838573081
Directory /workspace/12.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_bad_sba_tl_access.1072276734
Short name T170
Test name
Test status
Simulation time 456998110 ps
CPU time 1.52 seconds
Started Mar 03 12:34:44 PM PST 24
Finished Mar 03 12:34:46 PM PST 24
Peak memory 203968 kb
Host smart-9c676a30-d7a1-43a9-b008-e15287e5d5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072276734 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_bad_sba_tl_access.1072276734
Directory /workspace/12.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_delayed_resp_sba_tl_access.1485410932
Short name T29
Test name
Test status
Simulation time 4652934011 ps
CPU time 11.91 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 204444 kb
Host smart-8daa0af4-7f56-4f8a-a9c1-d080faac2472
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1485410932 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_delayed_resp_sba_
tl_access.1485410932
Directory /workspace/12.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_sba_tl_access.513793467
Short name T12
Test name
Test status
Simulation time 3770785579 ps
CPU time 4.43 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:18 PM PST 24
Peak memory 204068 kb
Host smart-1f141fd6-f4af-470d-a95d-4b76360b61e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513793467 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_sba_tl_access.513793467
Directory /workspace/12.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/12.rv_dm_stress_all.1007327824
Short name T6
Test name
Test status
Simulation time 3420290169 ps
CPU time 4.45 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:17 PM PST 24
Peak memory 203940 kb
Host smart-ba612fb8-4595-4dc5-9ee9-779ec615e902
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007327824 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rv_dm_stress_all.1007327824
Directory /workspace/12.rv_dm_stress_all/latest

Test location /workspace/coverage/default/13.rv_dm_alert_test.3574502985
Short name T216
Test name
Test status
Simulation time 50301886 ps
CPU time 0.63 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:37:28 PM PST 24
Peak memory 203652 kb
Host smart-332fd2cf-a32f-4828-b41b-b44f9530a529
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574502985 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_alert_test.3574502985
Directory /workspace/13.rv_dm_alert_test/latest

Test location /workspace/coverage/default/13.rv_dm_bad_sba_tl_access.2510155465
Short name T220
Test name
Test status
Simulation time 8011527220 ps
CPU time 24.51 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:33 PM PST 24
Peak memory 204076 kb
Host smart-a69b7a19-0740-4d54-a5fe-efad19b8926a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510155465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_bad_sba_tl_access.2510155465
Directory /workspace/13.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_delayed_resp_sba_tl_access.935828816
Short name T70
Test name
Test status
Simulation time 15739949637 ps
CPU time 46.6 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:35:04 PM PST 24
Peak memory 204032 kb
Host smart-78e8f8f8-0d36-41f9-a917-264647bcaf42
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=935828816 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_delayed_resp_sba_t
l_access.935828816
Directory /workspace/13.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/13.rv_dm_sba_tl_access.3122978358
Short name T210
Test name
Test status
Simulation time 9388166306 ps
CPU time 10.57 seconds
Started Mar 03 12:34:38 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 204040 kb
Host smart-9d66e437-b3a5-4fb6-a8c5-054573427b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122978358 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rv_dm_sba_tl_access.3122978358
Directory /workspace/13.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_alert_test.1244996878
Short name T69
Test name
Test status
Simulation time 213739426 ps
CPU time 0.65 seconds
Started Mar 03 12:34:07 PM PST 24
Finished Mar 03 12:34:08 PM PST 24
Peak memory 203556 kb
Host smart-f4f274e8-f9bc-47e4-b240-70abe5959440
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244996878 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_alert_test.1244996878
Directory /workspace/14.rv_dm_alert_test/latest

Test location /workspace/coverage/default/14.rv_dm_sba_tl_access.3928499731
Short name T203
Test name
Test status
Simulation time 2914506589 ps
CPU time 4.7 seconds
Started Mar 03 12:34:30 PM PST 24
Finished Mar 03 12:34:35 PM PST 24
Peak memory 204084 kb
Host smart-264da752-8c5e-4232-87a8-f24e3950fa3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928499731 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_sba_tl_access.3928499731
Directory /workspace/14.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/14.rv_dm_stress_all.1407907417
Short name T16
Test name
Test status
Simulation time 3318080126 ps
CPU time 9.53 seconds
Started Mar 03 12:34:09 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 203920 kb
Host smart-6edb2e7e-f5e2-46cc-bf60-2baaf8d163ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407907417 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rv_dm_stress_all.1407907417
Directory /workspace/14.rv_dm_stress_all/latest

Test location /workspace/coverage/default/15.rv_dm_alert_test.548099966
Short name T64
Test name
Test status
Simulation time 28742986 ps
CPU time 0.64 seconds
Started Mar 03 12:35:00 PM PST 24
Finished Mar 03 12:35:01 PM PST 24
Peak memory 203652 kb
Host smart-545a7b09-fc00-4e6c-86d0-bc1050b88185
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548099966 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_alert_test.548099966
Directory /workspace/15.rv_dm_alert_test/latest

Test location /workspace/coverage/default/15.rv_dm_delayed_resp_sba_tl_access.3026082462
Short name T215
Test name
Test status
Simulation time 277557267 ps
CPU time 1.11 seconds
Started Mar 03 12:34:24 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 204072 kb
Host smart-c1911df8-1936-491c-8570-218aae4cfb28
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3026082462 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_delayed_resp_sba_
tl_access.3026082462
Directory /workspace/15.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/15.rv_dm_sba_tl_access.234247371
Short name T211
Test name
Test status
Simulation time 3544930045 ps
CPU time 12.64 seconds
Started Mar 03 12:34:19 PM PST 24
Finished Mar 03 12:34:32 PM PST 24
Peak memory 204132 kb
Host smart-7467c1e4-ef9b-4bbb-a19b-b9d60214d3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234247371 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rv_dm_sba_tl_access.234247371
Directory /workspace/15.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_alert_test.2694759307
Short name T145
Test name
Test status
Simulation time 62852700 ps
CPU time 0.64 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203680 kb
Host smart-17335eab-3b05-4d05-8a05-c25f1675ddb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694759307 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_alert_test.2694759307
Directory /workspace/16.rv_dm_alert_test/latest

Test location /workspace/coverage/default/16.rv_dm_delayed_resp_sba_tl_access.2940228009
Short name T187
Test name
Test status
Simulation time 1075399587 ps
CPU time 2.68 seconds
Started Mar 03 12:34:15 PM PST 24
Finished Mar 03 12:34:18 PM PST 24
Peak memory 204008 kb
Host smart-4c15ead9-cd71-488f-bcdb-30eef2f9582b
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2940228009 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_delayed_resp_sba_
tl_access.2940228009
Directory /workspace/16.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/16.rv_dm_sba_tl_access.2461013698
Short name T175
Test name
Test status
Simulation time 5546798736 ps
CPU time 6.38 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:34:24 PM PST 24
Peak memory 203968 kb
Host smart-1cd93845-6e9a-4f26-b88d-6177fd24510e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461013698 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rv_dm_sba_tl_access.2461013698
Directory /workspace/16.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_bad_sba_tl_access.3926495247
Short name T227
Test name
Test status
Simulation time 1287646076 ps
CPU time 5.58 seconds
Started Mar 03 12:34:32 PM PST 24
Finished Mar 03 12:34:38 PM PST 24
Peak memory 203960 kb
Host smart-4e3dbb8f-7df1-42d5-af76-9c70351c0dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926495247 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_bad_sba_tl_access.3926495247
Directory /workspace/17.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/17.rv_dm_sba_tl_access.3330079542
Short name T190
Test name
Test status
Simulation time 3334081096 ps
CPU time 12.59 seconds
Started Mar 03 12:34:34 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 204184 kb
Host smart-7a35f71a-73bc-4ea7-bf4c-c0b71ea5e59d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330079542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rv_dm_sba_tl_access.3330079542
Directory /workspace/17.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_alert_test.345327842
Short name T113
Test name
Test status
Simulation time 36252430 ps
CPU time 0.67 seconds
Started Mar 03 12:34:39 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 203708 kb
Host smart-20a4c30a-4cd9-4296-a29f-92e57a0a84c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345327842 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_alert_test.345327842
Directory /workspace/18.rv_dm_alert_test/latest

Test location /workspace/coverage/default/18.rv_dm_autoincr_sba_tl_access.3972589043
Short name T223
Test name
Test status
Simulation time 13258006093 ps
CPU time 23.95 seconds
Started Mar 03 12:34:27 PM PST 24
Finished Mar 03 12:34:51 PM PST 24
Peak memory 204028 kb
Host smart-641145ce-5b29-4a42-8d32-e5af0342c37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972589043 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_autoincr_sba_tl_access.3972589043
Directory /workspace/18.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_bad_sba_tl_access.3485241216
Short name T219
Test name
Test status
Simulation time 21115676703 ps
CPU time 29.48 seconds
Started Mar 03 12:34:14 PM PST 24
Finished Mar 03 12:34:44 PM PST 24
Peak memory 204140 kb
Host smart-35e2ede9-c253-45d7-8300-a01b3c0d2ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485241216 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_bad_sba_tl_access.3485241216
Directory /workspace/18.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_delayed_resp_sba_tl_access.724665252
Short name T222
Test name
Test status
Simulation time 7938046417 ps
CPU time 7.77 seconds
Started Mar 03 12:34:33 PM PST 24
Finished Mar 03 12:34:41 PM PST 24
Peak memory 204480 kb
Host smart-9f278735-feab-41ea-a202-3b540a6faf61
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=724665252 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_access
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_delayed_resp_sba_t
l_access.724665252
Directory /workspace/18.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/18.rv_dm_sba_tl_access.3672223255
Short name T184
Test name
Test status
Simulation time 2330197071 ps
CPU time 4.85 seconds
Started Mar 03 12:34:17 PM PST 24
Finished Mar 03 12:34:22 PM PST 24
Peak memory 204400 kb
Host smart-8544e96a-c90d-4817-ae3d-12bac6691ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672223255 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rv_dm_sba_tl_access.3672223255
Directory /workspace/18.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_alert_test.2940333971
Short name T155
Test name
Test status
Simulation time 15670345 ps
CPU time 0.62 seconds
Started Mar 03 12:34:24 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 203648 kb
Host smart-156d882a-c8be-4907-859b-f36bbee2dd02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940333971 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_alert_test.2940333971
Directory /workspace/19.rv_dm_alert_test/latest

Test location /workspace/coverage/default/19.rv_dm_autoincr_sba_tl_access.1062192078
Short name T193
Test name
Test status
Simulation time 15259964546 ps
CPU time 68.7 seconds
Started Mar 03 12:34:35 PM PST 24
Finished Mar 03 12:35:45 PM PST 24
Peak memory 204004 kb
Host smart-820bbf9d-d760-4af8-9a78-b5af865ed736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062192078 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_autoincr_sba_tl_access.1062192078
Directory /workspace/19.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_bad_sba_tl_access.3525863512
Short name T115
Test name
Test status
Simulation time 1905326549 ps
CPU time 4.64 seconds
Started Mar 03 12:34:37 PM PST 24
Finished Mar 03 12:34:41 PM PST 24
Peak memory 203964 kb
Host smart-77125db8-141a-4c0b-9d1d-d225b2898d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525863512 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_bad_sba_tl_access.3525863512
Directory /workspace/19.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_delayed_resp_sba_tl_access.3058049264
Short name T197
Test name
Test status
Simulation time 6720228333 ps
CPU time 8.67 seconds
Started Mar 03 12:34:23 PM PST 24
Finished Mar 03 12:34:33 PM PST 24
Peak memory 203916 kb
Host smart-721eb99a-ea49-4b88-a573-967bbf4b79af
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3058049264 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_delayed_resp_sba_
tl_access.3058049264
Directory /workspace/19.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/19.rv_dm_sba_tl_access.28718884
Short name T196
Test name
Test status
Simulation time 1676234425 ps
CPU time 5.97 seconds
Started Mar 03 12:34:34 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 204112 kb
Host smart-9350b174-0e8c-4c3e-940d-6adb702184f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28718884 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rv_dm_sba_tl_access.28718884
Directory /workspace/19.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_alert_test.779250695
Short name T158
Test name
Test status
Simulation time 46392148 ps
CPU time 0.64 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:16 PM PST 24
Peak memory 203692 kb
Host smart-34f226a7-abfe-4077-b9b1-54ccf4a8fdab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779250695 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_alert_test.779250695
Directory /workspace/2.rv_dm_alert_test/latest

Test location /workspace/coverage/default/2.rv_dm_autoincr_sba_tl_access.1591555154
Short name T15
Test name
Test status
Simulation time 9381367939 ps
CPU time 40.02 seconds
Started Mar 03 12:34:34 PM PST 24
Finished Mar 03 12:35:14 PM PST 24
Peak memory 204004 kb
Host smart-0da257eb-3e79-45bb-b3b6-58684a9c0d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591555154 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_autoincr_sba_tl_access.1591555154
Directory /workspace/2.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_bad_sba_tl_access.3875209849
Short name T208
Test name
Test status
Simulation time 4129477885 ps
CPU time 9.69 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:20 PM PST 24
Peak memory 204056 kb
Host smart-120d5295-f164-4d34-bf06-50652dc3b3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875209849 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_bad_sba_tl_access.3875209849
Directory /workspace/2.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_delayed_resp_sba_tl_access.2217063465
Short name T66
Test name
Test status
Simulation time 995776293 ps
CPU time 2.17 seconds
Started Mar 03 12:34:41 PM PST 24
Finished Mar 03 12:34:44 PM PST 24
Peak memory 203952 kb
Host smart-67ac4ff0-49ad-43b4-accb-5c7d263f4ab3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2217063465 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_delayed_resp_sba_t
l_access.2217063465
Directory /workspace/2.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_hart_unavail.2998052079
Short name T209
Test name
Test status
Simulation time 177736359 ps
CPU time 0.69 seconds
Started Mar 03 12:34:23 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 202824 kb
Host smart-e4891271-790f-442f-93b6-2d28d7041ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998052079 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_hart_unavail.2998052079
Directory /workspace/2.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/2.rv_dm_sba_tl_access.4184027592
Short name T229
Test name
Test status
Simulation time 1654653284 ps
CPU time 2.55 seconds
Started Mar 03 12:34:20 PM PST 24
Finished Mar 03 12:34:23 PM PST 24
Peak memory 203952 kb
Host smart-716163af-5007-421e-a9b5-2f753c108e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184027592 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sba_tl_access.4184027592
Directory /workspace/2.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/2.rv_dm_sec_cm.3117522208
Short name T63
Test name
Test status
Simulation time 101272476 ps
CPU time 0.97 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:15 PM PST 24
Peak memory 219408 kb
Host smart-bfdd448a-7d17-498c-80f8-0e2dca968615
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117522208 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rv_dm_sec_cm.3117522208
Directory /workspace/2.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/20.rv_dm_alert_test.765839542
Short name T180
Test name
Test status
Simulation time 18666177 ps
CPU time 0.67 seconds
Started Mar 03 12:34:31 PM PST 24
Finished Mar 03 12:34:32 PM PST 24
Peak memory 203692 kb
Host smart-003f2ceb-2934-4512-a6f3-f4b817ea0501
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765839542 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rv_dm_alert_test.765839542
Directory /workspace/20.rv_dm_alert_test/latest

Test location /workspace/coverage/default/21.rv_dm_alert_test.1451335975
Short name T144
Test name
Test status
Simulation time 27209982 ps
CPU time 0.72 seconds
Started Mar 03 12:34:33 PM PST 24
Finished Mar 03 12:34:34 PM PST 24
Peak memory 203816 kb
Host smart-f51b320d-d8ff-4d05-9c15-a56a80f7542e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451335975 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rv_dm_alert_test.1451335975
Directory /workspace/21.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_alert_test.3240072869
Short name T149
Test name
Test status
Simulation time 54937488 ps
CPU time 0.66 seconds
Started Mar 03 12:34:39 PM PST 24
Finished Mar 03 12:34:39 PM PST 24
Peak memory 203708 kb
Host smart-ae94ff2d-c8eb-44ae-a378-20898351a4cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240072869 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_alert_test.3240072869
Directory /workspace/22.rv_dm_alert_test/latest

Test location /workspace/coverage/default/22.rv_dm_stress_all.2345388322
Short name T133
Test name
Test status
Simulation time 2163546922 ps
CPU time 3.23 seconds
Started Mar 03 12:34:19 PM PST 24
Finished Mar 03 12:34:23 PM PST 24
Peak memory 204020 kb
Host smart-5f29f1ca-ef9f-4ecc-8022-41a7e4995103
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345388322 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rv_dm_stress_all.2345388322
Directory /workspace/22.rv_dm_stress_all/latest

Test location /workspace/coverage/default/23.rv_dm_alert_test.3405292166
Short name T191
Test name
Test status
Simulation time 13905947 ps
CPU time 0.62 seconds
Started Mar 03 12:34:39 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 203704 kb
Host smart-353c7cf5-1bfc-4051-8839-6d4dcc131d71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3405292166 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rv_dm_alert_test.3405292166
Directory /workspace/23.rv_dm_alert_test/latest

Test location /workspace/coverage/default/24.rv_dm_alert_test.3936947765
Short name T162
Test name
Test status
Simulation time 57849879 ps
CPU time 0.66 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:47 PM PST 24
Peak memory 203708 kb
Host smart-d16c76ca-f4a0-44fe-a827-5fb083e11b32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936947765 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rv_dm_alert_test.3936947765
Directory /workspace/24.rv_dm_alert_test/latest

Test location /workspace/coverage/default/25.rv_dm_alert_test.649127137
Short name T46
Test name
Test status
Simulation time 15727444 ps
CPU time 0.66 seconds
Started Mar 03 12:34:29 PM PST 24
Finished Mar 03 12:34:30 PM PST 24
Peak memory 203652 kb
Host smart-e05a77eb-3782-4e34-95e2-185bb22d2cc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649127137 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rv_dm_alert_test.649127137
Directory /workspace/25.rv_dm_alert_test/latest

Test location /workspace/coverage/default/26.rv_dm_alert_test.1933023568
Short name T161
Test name
Test status
Simulation time 19246307 ps
CPU time 0.66 seconds
Started Mar 03 12:34:30 PM PST 24
Finished Mar 03 12:34:30 PM PST 24
Peak memory 203708 kb
Host smart-05c42523-a5f5-43b6-854c-1035a4dd4485
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933023568 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rv_dm_alert_test.1933023568
Directory /workspace/26.rv_dm_alert_test/latest

Test location /workspace/coverage/default/27.rv_dm_alert_test.63554289
Short name T147
Test name
Test status
Simulation time 61860319 ps
CPU time 0.64 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 203820 kb
Host smart-a8d019ed-d864-4544-a156-6ac3352455df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63554289 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rv_dm_alert_test.63554289
Directory /workspace/27.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_alert_test.158391831
Short name T164
Test name
Test status
Simulation time 49699124 ps
CPU time 0.67 seconds
Started Mar 03 12:34:46 PM PST 24
Finished Mar 03 12:34:47 PM PST 24
Peak memory 203804 kb
Host smart-6b16abc2-d6cf-4b9a-aba9-1b6569ce53ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158391831 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_alert_test.158391831
Directory /workspace/28.rv_dm_alert_test/latest

Test location /workspace/coverage/default/28.rv_dm_stress_all.1095357458
Short name T61
Test name
Test status
Simulation time 722527930 ps
CPU time 3.04 seconds
Started Mar 03 12:34:35 PM PST 24
Finished Mar 03 12:34:39 PM PST 24
Peak memory 204264 kb
Host smart-9f770bb7-3f90-4d15-903e-bafd3c416381
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095357458 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rv_dm_stress_all.1095357458
Directory /workspace/28.rv_dm_stress_all/latest

Test location /workspace/coverage/default/29.rv_dm_alert_test.360838335
Short name T47
Test name
Test status
Simulation time 47046632 ps
CPU time 0.68 seconds
Started Mar 03 12:34:40 PM PST 24
Finished Mar 03 12:34:41 PM PST 24
Peak memory 203672 kb
Host smart-aa2f1744-5c9f-4002-8973-f456815990e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360838335 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rv_dm_alert_test.360838335
Directory /workspace/29.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_alert_test.594889477
Short name T114
Test name
Test status
Simulation time 31729472 ps
CPU time 0.66 seconds
Started Mar 03 12:34:14 PM PST 24
Finished Mar 03 12:34:15 PM PST 24
Peak memory 203660 kb
Host smart-eaf82f6f-55ac-4ebd-b067-f3df146be4e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594889477 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_alert_test.594889477
Directory /workspace/3.rv_dm_alert_test/latest

Test location /workspace/coverage/default/3.rv_dm_delayed_resp_sba_tl_access.3651749064
Short name T177
Test name
Test status
Simulation time 648868939 ps
CPU time 2.21 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203944 kb
Host smart-e46ec07d-ae59-4ab3-8f78-8ec895f897c9
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3651749064 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_delayed_resp_sba_t
l_access.3651749064
Directory /workspace/3.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_hart_unavail.188429135
Short name T182
Test name
Test status
Simulation time 140999810 ps
CPU time 0.76 seconds
Started Mar 03 12:34:19 PM PST 24
Finished Mar 03 12:34:20 PM PST 24
Peak memory 203628 kb
Host smart-af2b0ddf-7941-4c90-b465-2c490a363d13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188429135 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_hart_unavail.188429135
Directory /workspace/3.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/3.rv_dm_sba_tl_access.204069590
Short name T27
Test name
Test status
Simulation time 294768269 ps
CPU time 1.33 seconds
Started Mar 03 12:34:26 PM PST 24
Finished Mar 03 12:34:28 PM PST 24
Peak memory 203972 kb
Host smart-2c1a25e2-5fce-49ee-8eaf-e1b578bf4686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204069590 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sba_tl_access.204069590
Directory /workspace/3.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/3.rv_dm_sec_cm.3713794275
Short name T33
Test name
Test status
Simulation time 218807869 ps
CPU time 1.23 seconds
Started Mar 03 12:34:14 PM PST 24
Finished Mar 03 12:34:15 PM PST 24
Peak memory 219884 kb
Host smart-18bdc0f0-cdef-4959-b235-4f70aff39495
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713794275 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_sec_cm.3713794275
Directory /workspace/3.rv_dm_sec_cm/latest

Test location /workspace/coverage/default/3.rv_dm_stress_all.3453893862
Short name T117
Test name
Test status
Simulation time 3912748619 ps
CPU time 4.87 seconds
Started Mar 03 12:34:20 PM PST 24
Finished Mar 03 12:34:26 PM PST 24
Peak memory 204056 kb
Host smart-cc0e5d61-3a2c-4bd9-a679-f874cd28b68d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453893862 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rv_dm_stress_all.3453893862
Directory /workspace/3.rv_dm_stress_all/latest

Test location /workspace/coverage/default/30.rv_dm_alert_test.1069769761
Short name T111
Test name
Test status
Simulation time 24621256 ps
CPU time 0.72 seconds
Started Mar 03 12:34:53 PM PST 24
Finished Mar 03 12:34:53 PM PST 24
Peak memory 203652 kb
Host smart-f07595ff-f3d4-4d52-9bd4-95ac98e58623
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069769761 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rv_dm_alert_test.1069769761
Directory /workspace/30.rv_dm_alert_test/latest

Test location /workspace/coverage/default/31.rv_dm_alert_test.2255321919
Short name T45
Test name
Test status
Simulation time 31540611 ps
CPU time 0.64 seconds
Started Mar 03 12:34:36 PM PST 24
Finished Mar 03 12:34:37 PM PST 24
Peak memory 203708 kb
Host smart-ff8115e9-d330-459a-bca5-31072dac15c8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255321919 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rv_dm_alert_test.2255321919
Directory /workspace/31.rv_dm_alert_test/latest

Test location /workspace/coverage/default/32.rv_dm_alert_test.2897785912
Short name T157
Test name
Test status
Simulation time 37013825 ps
CPU time 0.65 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:34:19 PM PST 24
Peak memory 203816 kb
Host smart-3064703e-8c47-46a0-9454-425c1ef95a62
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897785912 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rv_dm_alert_test.2897785912
Directory /workspace/32.rv_dm_alert_test/latest

Test location /workspace/coverage/default/33.rv_dm_alert_test.3312582603
Short name T49
Test name
Test status
Simulation time 19198264 ps
CPU time 0.67 seconds
Started Mar 03 12:34:56 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 203716 kb
Host smart-bb1671c7-692e-4a27-b8a6-deeb8b18826c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312582603 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rv_dm_alert_test.3312582603
Directory /workspace/33.rv_dm_alert_test/latest

Test location /workspace/coverage/default/34.rv_dm_alert_test.1375139750
Short name T156
Test name
Test status
Simulation time 49297861 ps
CPU time 0.66 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:45 PM PST 24
Peak memory 203708 kb
Host smart-141422d4-8b97-4e80-bfa3-18a41ffac1ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375139750 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rv_dm_alert_test.1375139750
Directory /workspace/34.rv_dm_alert_test/latest

Test location /workspace/coverage/default/35.rv_dm_alert_test.880172948
Short name T159
Test name
Test status
Simulation time 69919143 ps
CPU time 0.66 seconds
Started Mar 03 12:34:30 PM PST 24
Finished Mar 03 12:34:30 PM PST 24
Peak memory 203704 kb
Host smart-232467fa-fb4a-4855-9735-2096b9ed2527
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880172948 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rv_dm_alert_test.880172948
Directory /workspace/35.rv_dm_alert_test/latest

Test location /workspace/coverage/default/36.rv_dm_alert_test.3952551450
Short name T112
Test name
Test status
Simulation time 18161988 ps
CPU time 0.65 seconds
Started Mar 03 12:34:54 PM PST 24
Finished Mar 03 12:34:55 PM PST 24
Peak memory 203712 kb
Host smart-3ddc5dd3-5641-4d62-9a55-b9822dc70189
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952551450 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rv_dm_alert_test.3952551450
Directory /workspace/36.rv_dm_alert_test/latest

Test location /workspace/coverage/default/37.rv_dm_alert_test.2070038230
Short name T153
Test name
Test status
Simulation time 131105100 ps
CPU time 0.69 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:34:50 PM PST 24
Peak memory 203692 kb
Host smart-e938172d-3cfd-4582-aa88-d4156f5911c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070038230 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rv_dm_alert_test.2070038230
Directory /workspace/37.rv_dm_alert_test/latest

Test location /workspace/coverage/default/38.rv_dm_alert_test.3110877390
Short name T160
Test name
Test status
Simulation time 50806537 ps
CPU time 0.63 seconds
Started Mar 03 12:34:39 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 203708 kb
Host smart-9c6b51d8-2ddc-43d6-8662-b08591a04398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110877390 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rv_dm_alert_test.3110877390
Directory /workspace/38.rv_dm_alert_test/latest

Test location /workspace/coverage/default/39.rv_dm_alert_test.2285723861
Short name T151
Test name
Test status
Simulation time 15636313 ps
CPU time 0.64 seconds
Started Mar 03 12:34:37 PM PST 24
Finished Mar 03 12:34:37 PM PST 24
Peak memory 203620 kb
Host smart-8d6dcf84-1d95-4ed1-a3da-c68f51343e6f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285723861 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rv_dm_alert_test.2285723861
Directory /workspace/39.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_alert_test.2075664836
Short name T178
Test name
Test status
Simulation time 30801409 ps
CPU time 0.66 seconds
Started Mar 03 12:34:49 PM PST 24
Finished Mar 03 12:34:50 PM PST 24
Peak memory 203648 kb
Host smart-d83c2412-1bfd-4662-9658-f407e9ed0379
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075664836 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_alert_test.2075664836
Directory /workspace/4.rv_dm_alert_test/latest

Test location /workspace/coverage/default/4.rv_dm_bad_sba_tl_access.1535666627
Short name T116
Test name
Test status
Simulation time 3413551443 ps
CPU time 4.33 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:18 PM PST 24
Peak memory 204096 kb
Host smart-c490d85d-039e-4e8a-b2d0-3d83f0980d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535666627 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_bad_sba_tl_access.1535666627
Directory /workspace/4.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_delayed_resp_sba_tl_access.1690120741
Short name T232
Test name
Test status
Simulation time 817496940 ps
CPU time 3.76 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 203968 kb
Host smart-1d7a694b-69cc-4c1a-b06b-c33775527275
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1690120741 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_delayed_resp_sba_t
l_access.1690120741
Directory /workspace/4.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/4.rv_dm_hart_unavail.513807460
Short name T199
Test name
Test status
Simulation time 140732164 ps
CPU time 0.66 seconds
Started Mar 03 12:34:12 PM PST 24
Finished Mar 03 12:34:13 PM PST 24
Peak memory 203452 kb
Host smart-97c6725b-3669-43da-90c5-0016fad734bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513807460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_hart_unavail_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_hart_unavail.513807460
Directory /workspace/4.rv_dm_hart_unavail/latest

Test location /workspace/coverage/default/4.rv_dm_sba_tl_access.3192717397
Short name T173
Test name
Test status
Simulation time 3038272042 ps
CPU time 3.17 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:14 PM PST 24
Peak memory 204016 kb
Host smart-a5854eb0-a2cc-4d32-8e7b-9fd373cb2cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192717397 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rv_dm_sba_tl_access.3192717397
Directory /workspace/4.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/40.rv_dm_alert_test.2508455234
Short name T67
Test name
Test status
Simulation time 32940947 ps
CPU time 0.67 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 203808 kb
Host smart-0c92ecb6-ae19-4352-98f3-9c956b0a36c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508455234 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rv_dm_alert_test.2508455234
Directory /workspace/40.rv_dm_alert_test/latest

Test location /workspace/coverage/default/41.rv_dm_alert_test.820823017
Short name T138
Test name
Test status
Simulation time 37257288 ps
CPU time 0.68 seconds
Started Mar 03 12:34:37 PM PST 24
Finished Mar 03 12:34:38 PM PST 24
Peak memory 203684 kb
Host smart-f9304fdb-ea7c-470e-8c74-b0ac85d751af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820823017 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rv_dm_alert_test.820823017
Directory /workspace/41.rv_dm_alert_test/latest

Test location /workspace/coverage/default/42.rv_dm_alert_test.1443874513
Short name T152
Test name
Test status
Simulation time 55471283 ps
CPU time 0.66 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 203728 kb
Host smart-0e0677b3-8bbd-4f49-aded-f863ec756573
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443874513 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rv_dm_alert_test.1443874513
Directory /workspace/42.rv_dm_alert_test/latest

Test location /workspace/coverage/default/43.rv_dm_alert_test.1921315920
Short name T218
Test name
Test status
Simulation time 19970349 ps
CPU time 0.68 seconds
Started Mar 03 12:34:41 PM PST 24
Finished Mar 03 12:34:42 PM PST 24
Peak memory 203680 kb
Host smart-5f57d638-8374-4905-9c73-f6c9497b0037
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921315920 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rv_dm_alert_test.1921315920
Directory /workspace/43.rv_dm_alert_test/latest

Test location /workspace/coverage/default/44.rv_dm_alert_test.1510971256
Short name T179
Test name
Test status
Simulation time 75862240 ps
CPU time 0.64 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:45 PM PST 24
Peak memory 203644 kb
Host smart-50b66e88-7787-44de-bd37-c71a03bf4181
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510971256 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rv_dm_alert_test.1510971256
Directory /workspace/44.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_alert_test.761215888
Short name T50
Test name
Test status
Simulation time 100814704 ps
CPU time 0.64 seconds
Started Mar 03 12:34:40 PM PST 24
Finished Mar 03 12:34:40 PM PST 24
Peak memory 203812 kb
Host smart-e486320b-cd28-469a-afc9-677b04c02cda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761215888 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_alert_test.761215888
Directory /workspace/45.rv_dm_alert_test/latest

Test location /workspace/coverage/default/45.rv_dm_stress_all.2048163899
Short name T5
Test name
Test status
Simulation time 2188866527 ps
CPU time 7.7 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:56 PM PST 24
Peak memory 203952 kb
Host smart-6b9a69df-c795-4458-9e29-b5c54fc8de9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048163899 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rv_dm_stress_all.2048163899
Directory /workspace/45.rv_dm_stress_all/latest

Test location /workspace/coverage/default/46.rv_dm_alert_test.2990605722
Short name T32
Test name
Test status
Simulation time 42471447 ps
CPU time 0.64 seconds
Started Mar 03 12:34:47 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 203652 kb
Host smart-2d9726c0-3036-4a67-9de0-1c9ae3e51284
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990605722 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rv_dm_alert_test.2990605722
Directory /workspace/46.rv_dm_alert_test/latest

Test location /workspace/coverage/default/47.rv_dm_alert_test.2824503352
Short name T188
Test name
Test status
Simulation time 14963548 ps
CPU time 0.66 seconds
Started Mar 03 12:34:36 PM PST 24
Finished Mar 03 12:34:37 PM PST 24
Peak memory 203816 kb
Host smart-25adf232-f66a-4ae6-9d49-1418ca520b28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824503352 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rv_dm_alert_test.2824503352
Directory /workspace/47.rv_dm_alert_test/latest

Test location /workspace/coverage/default/48.rv_dm_alert_test.1317564475
Short name T26
Test name
Test status
Simulation time 63577645 ps
CPU time 0.68 seconds
Started Mar 03 12:34:48 PM PST 24
Finished Mar 03 12:34:49 PM PST 24
Peak memory 203684 kb
Host smart-d06c615b-a2aa-4649-8eb2-b52b3dcb58c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317564475 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rv_dm_alert_test.1317564475
Directory /workspace/48.rv_dm_alert_test/latest

Test location /workspace/coverage/default/49.rv_dm_alert_test.1331314561
Short name T141
Test name
Test status
Simulation time 54384349 ps
CPU time 0.69 seconds
Started Mar 03 12:35:01 PM PST 24
Finished Mar 03 12:35:02 PM PST 24
Peak memory 203652 kb
Host smart-dd863328-a986-4d07-b0bd-f7684e331264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331314561 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rv_dm_alert_test.1331314561
Directory /workspace/49.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_alert_test.256247999
Short name T142
Test name
Test status
Simulation time 41133415 ps
CPU time 0.72 seconds
Started Mar 03 12:34:45 PM PST 24
Finished Mar 03 12:34:46 PM PST 24
Peak memory 203708 kb
Host smart-0f9dd791-64a0-4019-b20e-8d51808b994e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256247999 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_alert_test.256247999
Directory /workspace/5.rv_dm_alert_test/latest

Test location /workspace/coverage/default/5.rv_dm_bad_sba_tl_access.877451801
Short name T200
Test name
Test status
Simulation time 3353690762 ps
CPU time 13.33 seconds
Started Mar 03 12:34:34 PM PST 24
Finished Mar 03 12:34:50 PM PST 24
Peak memory 204072 kb
Host smart-7a765fca-1e14-4aa8-9e52-964b898d2cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877451801 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_bad_sba_tl_access.877451801
Directory /workspace/5.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_delayed_resp_sba_tl_access.4028069324
Short name T174
Test name
Test status
Simulation time 1131219008 ps
CPU time 4.54 seconds
Started Mar 03 12:34:28 PM PST 24
Finished Mar 03 12:34:33 PM PST 24
Peak memory 203968 kb
Host smart-127d9e44-cae4-425f-81b6-f8958a861fdd
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028069324 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_delayed_resp_sba_t
l_access.4028069324
Directory /workspace/5.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/5.rv_dm_sba_tl_access.1813958551
Short name T186
Test name
Test status
Simulation time 4255855599 ps
CPU time 10.54 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:24 PM PST 24
Peak memory 204016 kb
Host smart-2ab3f49d-4858-472f-aea8-ffc9add97223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813958551 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rv_dm_sba_tl_access.1813958551
Directory /workspace/5.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_alert_test.4087216913
Short name T139
Test name
Test status
Simulation time 83995826 ps
CPU time 0.63 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:12 PM PST 24
Peak memory 203668 kb
Host smart-dbfef6d9-4d5b-4a98-a3ed-7eaa5177ed34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087216913 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_alert_test.4087216913
Directory /workspace/6.rv_dm_alert_test/latest

Test location /workspace/coverage/default/6.rv_dm_autoincr_sba_tl_access.2783798652
Short name T228
Test name
Test status
Simulation time 46791271297 ps
CPU time 157.06 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:36:49 PM PST 24
Peak memory 203992 kb
Host smart-f6d164ad-dad4-4531-8873-2e4b7394e177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783798652 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_autoincr_sba_tl_access_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_autoincr_sba_tl_access.2783798652
Directory /workspace/6.rv_dm_autoincr_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_bad_sba_tl_access.969066108
Short name T171
Test name
Test status
Simulation time 4327142244 ps
CPU time 13.84 seconds
Started Mar 03 12:34:13 PM PST 24
Finished Mar 03 12:34:27 PM PST 24
Peak memory 204048 kb
Host smart-e377a435-f179-43c0-9ed5-9c3355042374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969066108 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_bad_sba_tl_access.969066108
Directory /workspace/6.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_delayed_resp_sba_tl_access.2242824866
Short name T168
Test name
Test status
Simulation time 2183101528 ps
CPU time 8.48 seconds
Started Mar 03 12:37:27 PM PST 24
Finished Mar 03 12:37:36 PM PST 24
Peak memory 204000 kb
Host smart-bae19300-86c1-43fc-80ee-504ad0bcf5d1
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2242824866 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_delayed_resp_sba_t
l_access.2242824866
Directory /workspace/6.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/6.rv_dm_sba_tl_access.1565362232
Short name T206
Test name
Test status
Simulation time 2490435571 ps
CPU time 8.03 seconds
Started Mar 03 12:34:43 PM PST 24
Finished Mar 03 12:34:53 PM PST 24
Peak memory 204016 kb
Host smart-ce8eea42-5b42-4be7-881a-176e7c10644a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565362232 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rv_dm_sba_tl_access.1565362232
Directory /workspace/6.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_alert_test.1953276905
Short name T163
Test name
Test status
Simulation time 101376640 ps
CPU time 0.66 seconds
Started Mar 03 12:34:22 PM PST 24
Finished Mar 03 12:34:23 PM PST 24
Peak memory 203708 kb
Host smart-958068d4-f7c6-4081-8f4f-651eb8b6d184
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953276905 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_alert_test.1953276905
Directory /workspace/7.rv_dm_alert_test/latest

Test location /workspace/coverage/default/7.rv_dm_bad_sba_tl_access.2760198197
Short name T85
Test name
Test status
Simulation time 11230464144 ps
CPU time 35.99 seconds
Started Mar 03 12:34:11 PM PST 24
Finished Mar 03 12:34:48 PM PST 24
Peak memory 204012 kb
Host smart-979136dc-4823-4f6e-9393-86963f7c21ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760198197 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_bad_sba_tl_access.2760198197
Directory /workspace/7.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_delayed_resp_sba_tl_access.4271010644
Short name T214
Test name
Test status
Simulation time 3426477363 ps
CPU time 13.1 seconds
Started Mar 03 12:37:29 PM PST 24
Finished Mar 03 12:37:43 PM PST 24
Peak memory 204132 kb
Host smart-3f568fd3-b9b5-4f1d-9964-9fd410aee929
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4271010644 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_delayed_resp_sba_t
l_access.4271010644
Directory /workspace/7.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/7.rv_dm_sba_tl_access.3011489844
Short name T198
Test name
Test status
Simulation time 3099225287 ps
CPU time 5.81 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:16 PM PST 24
Peak memory 204024 kb
Host smart-0217ef3d-b344-4e11-8833-f91fb0348fb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011489844 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rv_dm_sba_tl_access.3011489844
Directory /workspace/7.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_alert_test.3362987416
Short name T31
Test name
Test status
Simulation time 28355684 ps
CPU time 0.66 seconds
Started Mar 03 12:34:08 PM PST 24
Finished Mar 03 12:34:14 PM PST 24
Peak memory 203624 kb
Host smart-8fb9bfca-214c-418e-99b1-b42665805095
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362987416 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_alert_test.3362987416
Directory /workspace/8.rv_dm_alert_test/latest

Test location /workspace/coverage/default/8.rv_dm_bad_sba_tl_access.898035883
Short name T172
Test name
Test status
Simulation time 7357323506 ps
CPU time 10.54 seconds
Started Mar 03 12:34:14 PM PST 24
Finished Mar 03 12:34:25 PM PST 24
Peak memory 204040 kb
Host smart-2b8fe0a4-1ea3-44af-bb9d-20b5e2b29dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898035883 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_bad_sba_tl_access.898035883
Directory /workspace/8.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_delayed_resp_sba_tl_access.1011866756
Short name T176
Test name
Test status
Simulation time 4800018916 ps
CPU time 4.46 seconds
Started Mar 03 12:34:29 PM PST 24
Finished Mar 03 12:34:33 PM PST 24
Peak memory 203944 kb
Host smart-34385171-1b58-49e2-abfb-3e004d578ec3
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1011866756 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_delayed_resp_sba_t
l_access.1011866756
Directory /workspace/8.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/8.rv_dm_sba_tl_access.109451144
Short name T202
Test name
Test status
Simulation time 2630506487 ps
CPU time 4.17 seconds
Started Mar 03 12:34:28 PM PST 24
Finished Mar 03 12:34:32 PM PST 24
Peak memory 204072 kb
Host smart-e3526769-8995-41f4-9385-e9d546e690ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109451144 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rv_dm_sba_tl_access.109451144
Directory /workspace/8.rv_dm_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_alert_test.265220998
Short name T110
Test name
Test status
Simulation time 157648708 ps
CPU time 0.66 seconds
Started Mar 03 12:34:10 PM PST 24
Finished Mar 03 12:34:11 PM PST 24
Peak memory 203704 kb
Host smart-decd20d4-df4b-4fed-92bd-06aeddf76219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265220998 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_alert_test.265220998
Directory /workspace/9.rv_dm_alert_test/latest

Test location /workspace/coverage/default/9.rv_dm_bad_sba_tl_access.9772460
Short name T185
Test name
Test status
Simulation time 3225925362 ps
CPU time 7.28 seconds
Started Mar 03 12:34:29 PM PST 24
Finished Mar 03 12:34:36 PM PST 24
Peak memory 204096 kb
Host smart-3885b29c-3482-42a3-a45a-13b33745b085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9772460 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_bad_sba_tl_access_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_bad_sba_tl_access.9772460
Directory /workspace/9.rv_dm_bad_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_delayed_resp_sba_tl_access.3174499809
Short name T1
Test name
Test status
Simulation time 2727436530 ps
CPU time 5.98 seconds
Started Mar 03 12:34:18 PM PST 24
Finished Mar 03 12:34:24 PM PST 24
Peak memory 204012 kb
Host smart-e34f21eb-d5d0-48de-b148-40676e24cf8c
User root
Command /workspace/default/simv +zero_delays=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3174499809 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_delayed_resp_sba_tl_acces
s_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_delayed_resp_sba_t
l_access.3174499809
Directory /workspace/9.rv_dm_delayed_resp_sba_tl_access/latest

Test location /workspace/coverage/default/9.rv_dm_sba_tl_access.3824599272
Short name T225
Test name
Test status
Simulation time 3902711108 ps
CPU time 7.98 seconds
Started Mar 03 12:34:38 PM PST 24
Finished Mar 03 12:34:46 PM PST 24
Peak memory 204088 kb
Host smart-80012509-3728-4cbc-a91c-032d782990ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824599272 -assert nopostproc +UVM_TESTNAME=rv_dm_base_test +UVM_TEST_SEQ=rv_dm_sba_tl_access_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rv_dm_sba_tl_access.3824599272
Directory /workspace/9.rv_dm_sba_tl_access/latest
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