Unified Coverage Report :: Group :: cip_base_pkg::tl_errors_cg_wrap::tl_errors

Group : cip_base_pkg::tl_errors_cg_wrap::tl_errors_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
86.67	96.15	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_errors_cgs_wrap[rv_dm_mem_reg_block]	92.31	1	100	1	64	64
tl_errors_cgs_wrap[rv_dm_regs_reg_block]	100.00	1	100	1	64	64

Group Instance : tl_errors_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
92.31	1	100	1	64	64

Summary for Group Instance tl_errors_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	2	13	92.31

Variables for Group Instance tl_errors_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	1	1	50.00	100	1	1	2
cp_mem_ro_err	2	0	2	100.00	100	1	1	2
cp_mem_wo_err	2	1	1	50.00	100	0	0	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	0	2	100.00	100	1	1	2
cp_write_w_instr_type_err	2	0	2	100.00	100	1	1	2

Group Instance : tl_errors_cgs_wrap[rv_dm_regs_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance tl_errors_cgs_wrap[rv_dm_regs_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	4	11	100.00

Variables for Group Instance tl_errors_cgs_wrap[rv_dm_regs_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_csr_size_err	2	0	2	100.00	100	1	1	2
cp_instr_type_err	2	0	2	100.00	100	1	1	2
cp_mem_byte_access_err	2	1	1	50.00	100	0	0	2
cp_mem_ro_err	2	1	1	50.00	100	0	0	2
cp_mem_wo_err	2	1	1	50.00	100	0	0	2
cp_tl_protocol_err	1	0	1	100.00	100	1	1	0
cp_unmapped_err	2	1	1	50.00	100	0	0	2
cp_write_w_instr_type_err	2	0	2	100.00	100	1	1	2

Summary for Variable cp_csr_size_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_csr_size_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	3689	1	T66	97	T40	2	T37	3
auto[1]	4504	1	T66	144	T41	8	T80	188

Summary for Variable cp_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_instr_type_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	6792	1	T66	230	T40	1	T37	3
auto[1]	1401	1	T66	11	T40	1	T41	2

Summary for Variable cp_mem_byte_access_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_byte_access_err

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER
[auto[1]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	8193	1		T66	241		T40	2		T37	3

Summary for Variable cp_mem_ro_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_mem_ro_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	8189	1	T66	241	T40	2	T37	3
auto[1]	4	1	T122	2	T123	1	T124	1

Summary for Variable cp_mem_wo_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for cp_mem_wo_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
[auto[1]]	0	0	-	-	-	-	-	-
auto[0]	8193	0	T66	241	T40	2	T37	3

Summary for Variable cp_tl_protocol_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_tl_protocol_err

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
covered	1302	1		T66	62		T41	11		T80	44

Summary for Variable cp_unmapped_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_unmapped_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	8017	1	T66	231	T40	2	T37	3
auto[1]	176	1	T66	10	T80	12	T42	1

Summary for Variable cp_write_w_instr_type_err

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write_w_instr_type_err

Bins

NAME	COUNT	AT LEAST	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0]	7472	1	T66	227	T40	1	T37	3
auto[1]	721	1	T66	14	T40	1	T41	4