SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
100.00 | 100.00 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
tl_intg_err_cgs_wrap[rv_dm_mem_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
tl_intg_err_cgs_wrap[rv_dm_regs_reg_block] | 100.00 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 0 | 14 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 14 | 1 | 13 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_is_mem | 2 | 1 | 1 | 50.00 | 100 | 0 | 0 | 2 | |
cp_num_cmd_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_num_data_err_bits | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 | |
cp_tl_intg_err_type | 4 | 0 | 4 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[0] | 801338 | 1 | T7 | 63 | T8 | 10 | T9 | 6 | |||
auto[1] | 16061 | 1 | T25 | 80 | T26 | 80 | T66 | 464 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 817215 | 1 | T7 | 63 | T8 | 10 | T9 | 6 | |||
values[1] | 18 | 1 | T37 | 1 | T38 | 1 | T39 | 1 | |||
values[2] | 5 | 1 | T39 | 2 | T78 | 2 | T125 | 1 | |||
values[3] | 103 | 1 | T37 | 6 | T38 | 6 | T39 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 817213 | 1 | T7 | 63 | T8 | 10 | T9 | 6 | |||
values[1] | 22 | 1 | T39 | 3 | T79 | 2 | T126 | 2 | |||
values[2] | 10 | 1 | T39 | 1 | T78 | 1 | T79 | 1 | |||
values[3] | 89 | 1 | T37 | 5 | T38 | 10 | T39 | 2 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 817119 | 1 | T7 | 63 | T8 | 10 | T9 | 6 | |||
auto[TlIntgErrCmd] | 94 | 1 | T37 | 3 | T38 | 4 | T39 | 3 | |||
auto[TlIntgErrData] | 96 | 1 | T37 | 3 | T38 | 8 | T39 | 4 | |||
auto[TlIntgErrBoth] | 90 | 1 | T37 | 4 | T38 | 8 | T39 | 3 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 2 | 1 | 1 | 50.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
[auto[1]] | 0 | 0 | - | - | - | - | - | - | |||
auto[0] | 25556 | 0 | T2 | 5 | T30 | 9 | T31 | 1 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 25361 | 1 | T2 | 5 | T30 | 9 | T31 | 1 | |||
values[1] | 24 | 1 | T38 | 1 | T39 | 1 | T78 | 1 | |||
values[2] | 1 | 1 | T127 | 1 | - | - | - | - | |||
values[3] | 98 | 1 | T37 | 5 | T38 | 11 | T39 | 6 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
values[0] | 25372 | 1 | T2 | 5 | T30 | 9 | T31 | 1 | |||
values[1] | 23 | 1 | T37 | 1 | T38 | 1 | T39 | 3 | |||
values[2] | 5 | 1 | T128 | 1 | T129 | 1 | T130 | 1 | |||
values[3] | 85 | 1 | T38 | 2 | T39 | 3 | T78 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 4 | 0 | 4 | 100.00 |
NAME | COUNT | AT LEAST | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[TlIntgErrNone] | 25276 | 1 | T2 | 5 | T30 | 9 | T31 | 1 | |||
auto[TlIntgErrCmd] | 96 | 1 | T37 | 7 | T38 | 10 | T39 | 3 | |||
auto[TlIntgErrData] | 85 | 1 | T37 | 2 | T38 | 4 | T39 | 2 | |||
auto[TlIntgErrBoth] | 99 | 1 | T37 | 1 | T38 | 6 | T39 | 5 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |