Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[rv_dm_mem_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
partial	255137	1		T7	36		T8	8		T9	5
full_word	562262	1		T7	27		T8	2		T9	1

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	817119	1		T7	63		T8	10		T9	6
auto[TlIntgErrCmd]	94	1		T37	3		T38	4		T39	3
auto[TlIntgErrData]	96	1		T37	3		T38	8		T39	4
auto[TlIntgErrBoth]	90	1		T37	4		T38	8		T39	3

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	507260	1		T7	27		T6	9		T19	14
auto[1]	310139	1		T7	36		T8	10		T9	6

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	210600	1		T7	14		T6	4		T19	9
auto[TlIntgErrNone]	partial	auto[1]	44281	1		T7	22		T8	8		T9	5
auto[TlIntgErrNone]	full_word	auto[0]	296538	1		T7	13		T6	5		T19	5
auto[TlIntgErrNone]	full_word	auto[1]	265700	1		T7	14		T8	2		T9	1
auto[TlIntgErrCmd]	partial	auto[0]	35	1		T37	2		T39	2		T78	1
auto[TlIntgErrCmd]	partial	auto[1]	51	1		T37	1		T38	4		T39	1
auto[TlIntgErrCmd]	full_word	auto[0]	3	1		T128	1		T131	1		T132	1
auto[TlIntgErrCmd]	full_word	auto[1]	5	1		T78	1		T79	1		T133	1
auto[TlIntgErrData]	partial	auto[0]	40	1		T37	1		T38	6		T39	1
auto[TlIntgErrData]	partial	auto[1]	45	1		T37	2		T38	1		T39	3
auto[TlIntgErrData]	full_word	auto[0]	8	1		T79	2		T133	1		T134	1
auto[TlIntgErrData]	full_word	auto[1]	3	1		T38	1		T130	1		T135	1
auto[TlIntgErrBoth]	partial	auto[0]	35	1		T37	2		T38	2		T39	1
auto[TlIntgErrBoth]	partial	auto[1]	50	1		T37	2		T38	5		T39	2
auto[TlIntgErrBoth]	full_word	auto[0]	1	1		T132	1		-	-		-	-
auto[TlIntgErrBoth]	full_word	auto[1]	4	1		T38	1		T136	2		T128	1