Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_mem_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rv_dm_regs_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	218060	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	560893	1		T7	27		T8	2		T9	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	505655	1		T7	27		T6	9		T19	14
values[0x0]	134391	1		T7	24		T8	7		T9	4
values[0x1]	138907	1		T7	12		T8	3		T9	2

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	165980	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	612973	1		T7	34		T8	3		T9	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3610	1		T14	1		T26	1		T43	5
valid_sources[0x01]	3126	1		T19	1		T138	1		T100	227
valid_sources[0x02]	2848	1		T5	1		T25	1		T61	1
valid_sources[0x03]	3004	1		T61	1		T43	10		T100	182
valid_sources[0x04]	2887	1		T6	3		T19	1		T14	1
valid_sources[0x05]	2965	1		T4	1		T25	2		T14	1
valid_sources[0x06]	2879	1		T27	1		T61	1		T43	11
valid_sources[0x07]	2781	1		T5	1		T14	1		T43	10
valid_sources[0x08]	2954	1		T5	1		T138	1		T43	19
valid_sources[0x09]	2884	1		T25	1		T138	1		T43	18
valid_sources[0x0a]	2909	1		T9	1		T4	1		T43	9
valid_sources[0x0b]	3292	1		T14	1		T61	1		T138	2
valid_sources[0x0c]	3084	1		T9	1		T27	1		T14	2
valid_sources[0x0d]	3338	1		T138	1		T43	51		T66	3
valid_sources[0x0e]	2887	1		T100	235		T37	22		T41	6
valid_sources[0x0f]	2942	1		T61	1		T100	185		T40	1
valid_sources[0x10]	2851	1		T25	1		T14	1		T138	2
valid_sources[0x11]	3374	1		T14	1		T61	1		T138	1
valid_sources[0x12]	3353	1		T4	1		T61	1		T138	1
valid_sources[0x13]	2907	1		T25	1		T14	2		T66	10
valid_sources[0x14]	3193	1		T43	19		T100	230		T40	1
valid_sources[0x15]	3230	1		T19	1		T43	34		T66	7
valid_sources[0x16]	2998	1		T27	1		T43	15		T100	207
valid_sources[0x17]	3148	1		T14	1		T61	2		T43	16
valid_sources[0x18]	3261	1		T100	198		T40	6		T37	19
valid_sources[0x19]	2740	1		T4	1		T25	1		T100	226
valid_sources[0x1a]	3417	1		T43	8		T100	228		T41	2
valid_sources[0x1b]	3040	1		T27	2		T139	20		T14	1
valid_sources[0x1c]	4044	1		T14	1		T43	5		T100	191
valid_sources[0x1d]	2984	1		T19	1		T14	2		T138	2
valid_sources[0x1e]	2886	1		T5	1		T25	1		T61	1
valid_sources[0x1f]	2882	1		T25	1		T61	1		T43	27
valid_sources[0x20]	3051	1		T5	2		T61	1		T100	211
valid_sources[0x21]	3135	1		T5	1		T100	229		T40	3
valid_sources[0x22]	2911	1		T4	2		T100	235		T40	3
valid_sources[0x23]	2885	1		T43	6		T100	212		T40	9
valid_sources[0x24]	3039	1		T4	1		T5	3		T19	1
valid_sources[0x25]	2894	1		T4	1		T5	1		T100	201
valid_sources[0x26]	3246	1		T5	1		T138	1		T43	47
valid_sources[0x27]	3204	1		T43	68		T66	13		T100	192
valid_sources[0x28]	3048	1		T25	1		T14	1		T61	1
valid_sources[0x29]	2840	1		T25	1		T26	2		T140	1
valid_sources[0x2a]	2966	1		T14	1		T61	2		T43	7
valid_sources[0x2b]	3098	1		T66	9		T100	252		T40	6
valid_sources[0x2c]	3125	1		T4	1		T5	2		T28	2
valid_sources[0x2d]	3193	1		T66	2		T100	227		T40	1
valid_sources[0x2e]	3168	1		T43	38		T100	221		T40	1
valid_sources[0x2f]	2916	1		T5	1		T61	3		T62	2
valid_sources[0x30]	2850	1		T5	1		T62	4		T138	1
valid_sources[0x31]	2902	1		T6	2		T14	2		T100	190
valid_sources[0x32]	2914	1		T28	1		T62	1		T43	35
valid_sources[0x33]	3032	1		T27	1		T14	1		T43	4
valid_sources[0x34]	3074	1		T4	1		T61	1		T43	1
valid_sources[0x35]	2820	1		T138	1		T43	13		T100	218
valid_sources[0x36]	2851	1		T25	1		T14	1		T138	1
valid_sources[0x37]	2988	1		T14	1		T61	1		T43	8
valid_sources[0x38]	2817	1		T7	63		T6	1		T14	1
valid_sources[0x39]	3029	1		T43	9		T100	213		T40	3
valid_sources[0x3a]	2953	1		T4	1		T25	1		T61	1
valid_sources[0x3b]	2877	1		T61	1		T62	7		T43	3
valid_sources[0x3c]	2938	1		T4	2		T61	1		T100	198
valid_sources[0x3d]	3487	1		T5	1		T14	1		T61	1
valid_sources[0x3e]	2877	1		T25	3		T138	1		T43	24
valid_sources[0x3f]	3031	1		T43	34		T100	194		T40	3
valid_sources[0x40]	3068	1		T14	1		T43	6		T100	204
valid_sources[0x41]	2921	1		T27	3		T14	1		T43	8
valid_sources[0x42]	3099	1		T43	14		T66	9		T100	187
valid_sources[0x43]	2729	1		T19	2		T14	1		T43	23
valid_sources[0x44]	2980	1		T14	2		T138	1		T140	2
valid_sources[0x45]	3052	1		T4	1		T25	1		T43	23
valid_sources[0x46]	3036	1		T25	1		T100	255		T40	1
valid_sources[0x47]	2950	1		T4	1		T61	1		T100	240
valid_sources[0x48]	4019	1		T5	2		T25	1		T14	2
valid_sources[0x49]	2871	1		T62	1		T43	33		T100	241
valid_sources[0x4a]	2859	1		T19	1		T43	11		T66	3
valid_sources[0x4b]	2990	1		T19	1		T27	1		T61	1
valid_sources[0x4c]	2944	1		T61	1		T43	3		T100	217
valid_sources[0x4d]	3136	1		T25	1		T14	1		T61	1
valid_sources[0x4e]	3356	1		T5	1		T25	1		T14	1
valid_sources[0x4f]	2958	1		T25	1		T43	31		T100	218
valid_sources[0x50]	2677	1		T19	1		T100	219		T40	12
valid_sources[0x51]	3112	1		T6	6		T26	6		T43	16
valid_sources[0x52]	2970	1		T61	2		T43	10		T100	194
valid_sources[0x53]	3446	1		T19	1		T43	23		T100	185
valid_sources[0x54]	3126	1		T26	1		T43	83		T100	189
valid_sources[0x55]	3542	1		T5	1		T26	1		T43	17
valid_sources[0x56]	4035	1		T25	3		T138	2		T100	237
valid_sources[0x57]	3299	1		T14	1		T138	1		T100	218
valid_sources[0x58]	3559	1		T14	2		T26	1		T61	1
valid_sources[0x59]	2789	1		T6	1		T25	2		T100	208
valid_sources[0x5a]	3085	1		T6	1		T25	1		T26	1
valid_sources[0x5b]	2863	1		T27	3		T100	158		T40	6
valid_sources[0x5c]	4331	1		T5	1		T61	1		T43	35
valid_sources[0x5d]	3056	1		T6	1		T19	1		T25	1
valid_sources[0x5e]	3556	1		T4	1		T14	1		T138	1
valid_sources[0x5f]	2905	1		T138	1		T43	8		T100	196
valid_sources[0x60]	3223	1		T25	1		T138	1		T43	5
valid_sources[0x61]	2888	1		T27	1		T14	2		T61	1
valid_sources[0x62]	2893	1		T4	1		T27	1		T61	1
valid_sources[0x63]	3534	1		T61	2		T138	1		T43	30
valid_sources[0x64]	3243	1		T6	3		T25	1		T43	19
valid_sources[0x65]	2755	1		T4	1		T138	1		T43	3
valid_sources[0x66]	3089	1		T100	218		T40	4		T41	11
valid_sources[0x67]	2913	1		T25	2		T14	1		T61	1
valid_sources[0x68]	2916	1		T9	1		T14	1		T62	11
valid_sources[0x69]	3000	1		T14	2		T138	1		T66	2
valid_sources[0x6a]	2971	1		T4	1		T6	1		T14	1
valid_sources[0x6b]	3295	1		T66	3		T100	199		T40	3
valid_sources[0x6c]	2710	1		T138	1		T43	2		T100	215
valid_sources[0x6d]	2708	1		T8	1		T19	2		T138	1
valid_sources[0x6e]	3262	1		T66	2		T100	242		T40	5
valid_sources[0x6f]	2809	1		T26	4		T138	1		T43	4
valid_sources[0x70]	3693	1		T28	3		T61	1		T140	1
valid_sources[0x71]	2764	1		T14	1		T61	1		T62	10
valid_sources[0x72]	2860	1		T14	1		T138	1		T43	5
valid_sources[0x73]	2826	1		T14	1		T138	4		T43	24
valid_sources[0x74]	2891	1		T5	1		T16	1		T14	1
valid_sources[0x75]	2875	1		T5	1		T138	1		T140	1
valid_sources[0x76]	3422	1		T4	1		T25	1		T43	13
valid_sources[0x77]	2793	1		T28	4		T61	1		T66	10
valid_sources[0x78]	3023	1		T8	2		T25	1		T62	1
valid_sources[0x79]	3047	1		T43	23		T66	5		T100	197
valid_sources[0x7a]	3361	1		T43	25		T100	218		T40	2
valid_sources[0x7b]	3073	1		T14	1		T62	1		T43	15
valid_sources[0x7c]	2766	1		T19	2		T100	237		T40	5
valid_sources[0x7d]	2962	1		T138	3		T43	12		T100	230
valid_sources[0x7e]	2827	1		T14	1		T43	5		T100	178
valid_sources[0x7f]	2943	1		T25	1		T43	28		T100	211
valid_sources[0x80]	2596	1		T4	1		T5	1		T14	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

296404

1

T7

13

T6

5

T19

5

values[0x0]

all_enables

biggest_size

132525

1

T7

10

T8

2

T9

1

values[0x1]

all_enables

biggest_size

131964

1

T7

4

T4

2

T5

4

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1943	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_enables	14924	1		T2	1		T30	2		T31	1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	5192	1		T43	2		T66	87		T40	38
values[0x0]	5730	1		T30	2		T31	1		T45	3
values[0x1]	5945	1		T2	5		T30	7		T45	4

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1440	Excluded

Covered bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
biggest_size	15427	1		T2	1		T30	4		T31	1

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	44	1		T85	7		T81	1		T79	2
valid_sources[0x01]	83	1		T46	1		T51	1		T82	2
valid_sources[0x02]	83	1		T141	1		T41	12		T82	1
valid_sources[0x03]	47	1		T46	1		T142	1		T37	2
valid_sources[0x04]	60	1		T54	3		T55	1		T81	5
valid_sources[0x05]	45	1		T38	2		T58	2		T78	1
valid_sources[0x06]	50	1		T41	2		T55	3		T82	1
valid_sources[0x07]	61	1		T80	3		T55	2		T137	2
valid_sources[0x08]	41	1		T46	1		T84	1		T81	2
valid_sources[0x09]	67	1		T142	2		T55	2		T81	1
valid_sources[0x0a]	47	1		T30	1		T66	3		T81	2
valid_sources[0x0b]	43	1		T143	1		T53	3		T55	1
valid_sources[0x0c]	88	1		T84	1		T41	5		T80	3
valid_sources[0x0d]	78	1		T144	1		T66	5		T41	12
valid_sources[0x0e]	56	1		T142	1		T55	1		T81	2
valid_sources[0x0f]	69	1		T82	2		T87	2		T137	8
valid_sources[0x10]	39	1		T2	3		T47	1		T37	1
valid_sources[0x11]	54	1		T55	1		T82	1		T93	5
valid_sources[0x12]	70	1		T145	1		T41	3		T55	1
valid_sources[0x13]	37	1		T30	1		T51	1		T143	2
valid_sources[0x14]	58	1		T146	1		T143	1		T55	2
valid_sources[0x15]	74	1		T80	6		T55	1		T58	1
valid_sources[0x16]	38	1		T55	3		T81	1		T82	1
valid_sources[0x17]	35	1		T38	1		T81	4		T82	1
valid_sources[0x18]	49	1		T45	4		T53	4		T147	2
valid_sources[0x19]	66	1		T148	6		T80	13		T55	2
valid_sources[0x1a]	186	1		T30	1		T80	23		T137	3
valid_sources[0x1b]	79	1		T80	18		T38	1		T82	2
valid_sources[0x1c]	63	1		T66	11		T80	1		T55	2
valid_sources[0x1d]	49	1		T47	2		T149	2		T150	5
valid_sources[0x1e]	84	1		T55	1		T81	1		T82	1
valid_sources[0x1f]	82	1		T37	8		T53	3		T58	1
valid_sources[0x20]	53	1		T51	1		T55	1		T137	7
valid_sources[0x21]	108	1		T151	1		T37	1		T55	1
valid_sources[0x22]	64	1		T47	1		T152	1		T66	5
valid_sources[0x23]	37	1		T47	1		T38	1		T137	4
valid_sources[0x24]	111	1		T66	3		T80	25		T38	1
valid_sources[0x25]	31	1		T142	2		T55	2		T88	1
valid_sources[0x26]	54	1		T82	1		T58	1		T78	1
valid_sources[0x27]	67	1		T153	1		T80	17		T88	1
valid_sources[0x28]	87	1		T38	1		T55	1		T81	3
valid_sources[0x29]	44	1		T153	1		T82	2		T93	1
valid_sources[0x2a]	65	1		T66	23		T82	2		T79	2
valid_sources[0x2b]	60	1		T154	2		T78	1		T137	5
valid_sources[0x2c]	50	1		T55	5		T39	1		T83	1
valid_sources[0x2d]	43	1		T48	1		T55	2		T78	2
valid_sources[0x2e]	32	1		T78	1		T155	1		T156	4
valid_sources[0x2f]	30	1		T38	1		T55	2		T58	1
valid_sources[0x30]	36	1		T55	2		T81	1		T82	1
valid_sources[0x31]	49	1		T145	1		T55	1		T81	2
valid_sources[0x32]	58	1		T41	11		T42	4		T55	1
valid_sources[0x33]	37	1		T157	2		T81	1		T78	1
valid_sources[0x34]	62	1		T152	1		T55	2		T81	1
valid_sources[0x35]	60	1		T41	18		T58	1		T137	3
valid_sources[0x36]	67	1		T46	1		T144	1		T55	1
valid_sources[0x37]	48	1		T55	2		T78	1		T93	1
valid_sources[0x38]	47	1		T55	1		T82	2		T58	1
valid_sources[0x39]	35	1		T46	1		T142	1		T149	1
valid_sources[0x3a]	45	1		T55	1		T82	1		T39	1
valid_sources[0x3b]	45	1		T82	1		T88	1		T78	1
valid_sources[0x3c]	43	1		T146	1		T55	1		T87	1
valid_sources[0x3d]	87	1		T55	2		T81	1		T93	4
valid_sources[0x3e]	51	1		T158	7		T66	3		T53	7
valid_sources[0x3f]	56	1		T159	1		T66	4		T55	3
valid_sources[0x40]	72	1		T47	1		T49	8		T160	1
valid_sources[0x41]	48	1		T161	2		T52	1		T55	1
valid_sources[0x42]	105	1		T82	2		T79	1		T114	3
valid_sources[0x43]	51	1		T55	2		T81	1		T82	1
valid_sources[0x44]	90	1		T146	1		T55	1		T82	1
valid_sources[0x45]	122	1		T144	1		T161	1		T80	24
valid_sources[0x46]	48	1		T162	1		T66	6		T55	2
valid_sources[0x47]	46	1		T30	1		T43	1		T37	4
valid_sources[0x48]	56	1		T143	1		T41	17		T58	1
valid_sources[0x49]	123	1		T41	10		T53	2		T38	1
valid_sources[0x4a]	81	1		T41	7		T80	2		T91	1
valid_sources[0x4b]	48	1		T47	1		T161	2		T66	9
valid_sources[0x4c]	65	1		T162	3		T55	1		T82	1
valid_sources[0x4d]	83	1		T41	11		T38	2		T55	2
valid_sources[0x4e]	52	1		T161	1		T55	2		T82	2
valid_sources[0x4f]	78	1		T152	1		T41	14		T38	1
valid_sources[0x50]	245	1		T41	1		T38	3		T55	1
valid_sources[0x51]	64	1		T46	2		T66	5		T52	1
valid_sources[0x52]	39	1		T55	2		T82	1		T137	1
valid_sources[0x53]	65	1		T46	2		T163	8		T87	2
valid_sources[0x54]	86	1		T153	1		T66	14		T82	1
valid_sources[0x55]	185	1		T80	17		T93	1		T164	3
valid_sources[0x56]	70	1		T84	1		T152	6		T66	12
valid_sources[0x57]	46	1		T55	1		T58	1		T137	1
valid_sources[0x58]	64	1		T145	1		T38	2		T55	1
valid_sources[0x59]	42	1		T58	1		T137	3		T93	1
valid_sources[0x5a]	53	1		T84	1		T55	1		T137	3
valid_sources[0x5b]	70	1		T165	3		T80	20		T55	3
valid_sources[0x5c]	45	1		T66	1		T55	2		T88	1
valid_sources[0x5d]	54	1		T55	2		T58	3		T164	2
valid_sources[0x5e]	56	1		T84	1		T166	6		T55	1
valid_sources[0x5f]	76	1		T80	17		T58	1		T79	1
valid_sources[0x60]	38	1		T51	1		T82	2		T156	7
valid_sources[0x61]	93	1		T45	3		T82	1		T137	6
valid_sources[0x62]	41	1		T2	1		T161	1		T55	1
valid_sources[0x63]	47	1		T144	1		T41	7		T80	1
valid_sources[0x64]	48	1		T149	1		T55	2		T58	1
valid_sources[0x65]	53	1		T167	16		T55	2		T81	1
valid_sources[0x66]	170	1		T30	1		T165	2		T80	11
valid_sources[0x67]	46	1		T2	1		T55	1		T82	1
valid_sources[0x68]	64	1		T46	1		T161	1		T55	2
valid_sources[0x69]	76	1		T51	1		T72	1		T66	9
valid_sources[0x6a]	47	1		T66	9		T55	2		T82	1
valid_sources[0x6b]	101	1		T47	1		T38	1		T55	6
valid_sources[0x6c]	51	1		T93	1		T156	1		T168	1
valid_sources[0x6d]	95	1		T30	1		T80	3		T55	1
valid_sources[0x6e]	52	1		T81	4		T169	1		T79	1
valid_sources[0x6f]	156	1		T170	1		T38	1		T82	1
valid_sources[0x70]	56	1		T153	1		T55	1		T82	1
valid_sources[0x71]	44	1		T46	2		T66	1		T55	4
valid_sources[0x72]	52	1		T80	14		T53	1		T78	1
valid_sources[0x73]	81	1		T84	1		T80	11		T55	1
valid_sources[0x74]	45	1		T160	1		T82	1		T78	1
valid_sources[0x75]	40	1		T72	1		T160	2		T82	1
valid_sources[0x76]	25	1		T55	1		T82	1		T79	1
valid_sources[0x77]	57	1		T80	20		T53	3		T38	1
valid_sources[0x78]	47	1		T51	1		T170	2		T144	1
valid_sources[0x79]	53	1		T51	1		T55	2		T137	3
valid_sources[0x7a]	52	1		T31	1		T142	1		T54	2
valid_sources[0x7b]	69	1		T137	3		T169	2		T164	2
valid_sources[0x7c]	40	1		T53	1		T55	2		T92	8
valid_sources[0x7d]	54	1		T38	1		T55	2		T137	1
valid_sources[0x7e]	58	1		T66	4		T81	1		T169	1
valid_sources[0x7f]	53	1		T72	1		T144	1		T43	1
valid_sources[0x80]	46	1		T38	2		T55	2		T81	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

4310

1

T43

2

T66

87

T40

36

values[0x0]

all_enables

biggest_size

5321

1

T30

1

T31

1

T45

2

values[0x1]

all_enables

biggest_size

5293

1

T2

1

T30

1

T46

1