SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_lc_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_pm_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_sba.u_err_en_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_tlul_lc_gate_rom.u_err_en_sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
88.73 | 100.00 | 75.86 | 91.55 | 87.50 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
68.13 | 86.27 | 72.22 | 57.14 | 75.00 | 50.00 | u_tlul_lc_gate_sba |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
81.44 | 96.08 | 77.78 | 100.00 | 83.33 | 50.00 | u_tlul_lc_gate_rom |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 668 | 668 | 0 | 0 |
OutputsKnown_A | 88814772 | 88651056 | 0 | 0 |
gen_flops.OutputDelay_A | 44407386 | 44321802 | 0 | 1002 |
gen_no_flops.OutputDelay_A | 44407386 | 44325528 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 668 | 668 | 0 | 0 |
T1 | 4 | 4 | 0 | 0 |
T2 | 4 | 4 | 0 | 0 |
T3 | 4 | 4 | 0 | 0 |
T7 | 4 | 4 | 0 | 0 |
T10 | 4 | 4 | 0 | 0 |
T11 | 4 | 4 | 0 | 0 |
T12 | 4 | 4 | 0 | 0 |
T15 | 4 | 4 | 0 | 0 |
T30 | 4 | 4 | 0 | 0 |
T31 | 4 | 4 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 88814772 | 88651056 | 0 | 0 |
T1 | 2010360 | 2004796 | 0 | 0 |
T2 | 8696 | 8464 | 0 | 0 |
T3 | 243968 | 241876 | 0 | 0 |
T7 | 73104 | 72792 | 0 | 0 |
T10 | 33440 | 33184 | 0 | 0 |
T11 | 13160 | 12836 | 0 | 0 |
T12 | 14988 | 14696 | 0 | 0 |
T15 | 430868 | 429244 | 0 | 0 |
T30 | 4188 | 3860 | 0 | 0 |
T31 | 5960 | 5640 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44407386 | 44321802 | 0 | 1002 |
T1 | 1005180 | 1002272 | 0 | 6 |
T2 | 4348 | 4226 | 0 | 6 |
T3 | 121984 | 120884 | 0 | 6 |
T7 | 36552 | 36390 | 0 | 6 |
T10 | 16720 | 16586 | 0 | 6 |
T11 | 6580 | 6412 | 0 | 6 |
T12 | 7494 | 7342 | 0 | 6 |
T15 | 215434 | 214586 | 0 | 6 |
T30 | 2094 | 1924 | 0 | 6 |
T31 | 2980 | 2814 | 0 | 6 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 44407386 | 44325528 | 0 | 0 |
T1 | 1005180 | 1002398 | 0 | 0 |
T2 | 4348 | 4232 | 0 | 0 |
T3 | 121984 | 120938 | 0 | 0 |
T7 | 36552 | 36396 | 0 | 0 |
T10 | 16720 | 16592 | 0 | 0 |
T11 | 6580 | 6418 | 0 | 0 |
T12 | 7494 | 7348 | 0 | 0 |
T15 | 215434 | 214622 | 0 | 0 |
T30 | 2094 | 1930 | 0 | 0 |
T31 | 2980 | 2820 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 6 | 6 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 5 | 5 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 22203693 | 22162764 | 0 | 0 |
gen_flops.OutputDelay_A | 22203693 | 22160901 | 0 | 501 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22160901 | 0 | 501 |
T1 | 502590 | 501136 | 0 | 3 |
T2 | 2174 | 2113 | 0 | 3 |
T3 | 60992 | 60442 | 0 | 3 |
T7 | 18276 | 18195 | 0 | 3 |
T10 | 8360 | 8293 | 0 | 3 |
T11 | 3290 | 3206 | 0 | 3 |
T12 | 3747 | 3671 | 0 | 3 |
T15 | 107717 | 107293 | 0 | 3 |
T30 | 1047 | 962 | 0 | 3 |
T31 | 1490 | 1407 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 22203693 | 22162764 | 0 | 0 |
gen_flops.OutputDelay_A | 22203693 | 22160901 | 0 | 501 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22160901 | 0 | 501 |
T1 | 502590 | 501136 | 0 | 3 |
T2 | 2174 | 2113 | 0 | 3 |
T3 | 60992 | 60442 | 0 | 3 |
T7 | 18276 | 18195 | 0 | 3 |
T10 | 8360 | 8293 | 0 | 3 |
T11 | 3290 | 3206 | 0 | 3 |
T12 | 3747 | 3671 | 0 | 3 |
T15 | 107717 | 107293 | 0 | 3 |
T30 | 1047 | 962 | 0 | 3 |
T31 | 1490 | 1407 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 22203693 | 22162764 | 0 | 0 |
gen_no_flops.OutputDelay_A | 22203693 | 22162764 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 167 | 167 | 0 | 0 |
OutputsKnown_A | 22203693 | 22162764 | 0 | 0 |
gen_no_flops.OutputDelay_A | 22203693 | 22162764 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 167 | 167 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T7 | 1 | 1 | 0 | 0 |
T10 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T30 | 1 | 1 | 0 | 0 |
T31 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 22203693 | 22162764 | 0 | 0 |
T1 | 502590 | 501199 | 0 | 0 |
T2 | 2174 | 2116 | 0 | 0 |
T3 | 60992 | 60469 | 0 | 0 |
T7 | 18276 | 18198 | 0 | 0 |
T10 | 8360 | 8296 | 0 | 0 |
T11 | 3290 | 3209 | 0 | 0 |
T12 | 3747 | 3674 | 0 | 0 |
T15 | 107717 | 107311 | 0 | 0 |
T30 | 1047 | 965 | 0 | 0 |
T31 | 1490 | 1410 | 0 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |